1 /*==========================================================================
5 // HAL misc board support code for EA LPC2468 OEM board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2008 eCosCentric Limited
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
36 // -------------------------------------------
37 //####ECOSGPLCOPYRIGHTEND####
38 //==========================================================================
39 //#####DESCRIPTIONBEGIN####
41 // Author(s): Uwe Kindler
42 // Contributors: Uwe Kindler
44 // Purpose: HAL board support
45 // Description: Implementations of HAL board interfaces
47 //####DESCRIPTIONEND####
49 //========================================================================*/
52 //===========================================================================
54 //===========================================================================
55 #include <pkgconf/hal.h>
56 #include <pkgconf/hal_arm_lpc24xx_ea2468.h>
57 #include <cyg/hal/hal_diag.h>
58 #include <cyg/hal/hal_io.h> // IO macros
60 #include <cyg/infra/cyg_type.h> // base types
61 #include <cyg/infra/cyg_ass.h> // assertion macros
62 #include <cyg/hal/var_io.h>
63 #include <cyg/hal/plf_io.h>
64 #include <pkgconf/hal.h>
66 #include <cyg/hal/hal_arch.h>
67 #include <cyg/hal/hal_intr.h>
74 //===========================================================================
76 //===========================================================================
77 #define SCB_BASE CYGARC_HAL_LPC24XX_REG_SCB_BASE
78 #define EMC_BASE CYGARC_HAL_LPC24XX_REG_EMC_BASE
79 #define PIN_BASE CYGARC_HAL_LPC24XX_REG_PIN_BASE
80 #define IO_BASE CYGARC_HAL_LPC24XX_REG_IO_BASE
81 #define FIO_BASE CYGARC_HAL_LPC24XX_REG_FIO_BASE
82 #define SDRAM_BASE 0xA0000000
84 extern void cyg_hal_plf_serial_init(void);
87 //===========================================================================
88 // Initialize communication channels
89 //===========================================================================
90 void cyg_hal_plf_comms_init(void)
92 static int initialized = 0;
98 cyg_hal_plf_serial_init();
102 //===========================================================================
103 // Finalize hardware initialisation of platform
104 //===========================================================================
105 void hal_plf_hardware_init(void)
111 //===========================================================================
113 //===========================================================================
114 void hal_gpio_init(void)
119 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050);
120 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0);
121 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0);
122 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0);
123 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0);
124 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0);
125 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0);
126 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff);
127 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0);
128 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0);
129 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0);
131 HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0);
132 HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0);
133 HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff);
134 HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff);
136 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0);
137 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0);
138 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0);
139 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0);
140 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0);
142 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff);
143 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff);
144 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff);
145 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff);
146 HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff);
150 //===========================================================================
151 // hal_pll_init - initialize pll and all clocks
152 //===========================================================================
153 void hal_pll_init(void)
157 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
158 if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)
161 // Enable PLL, disconnected
163 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
164 CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
165 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
166 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
170 // Disable PLL, disconnected
172 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, 0x00);
173 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
174 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
177 // Enables main oscillator and wait until it is usable
179 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS,
180 CYGARC_HAL_LPC24XX_REG_SCS_OSCEN);
183 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval);
184 } while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT));
187 // select main OSC, 12MHz, as the PLL clock source
189 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL,
190 CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN);
193 // Configure PLL multiplier and pre divider according to
194 // configuration values
196 regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) |
197 (CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16);
198 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG, regval);
199 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
200 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
203 // Enable PLL, disconnected
205 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
206 CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
207 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
208 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
211 // Set CPU clock divider
213 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
214 CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1);
217 // Set USB clock divider
219 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
220 CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1);
223 // Check lock bit status
227 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
228 } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK));
231 // Enable PLL and connect
233 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
234 CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE |
235 CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC);
236 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
237 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
240 // Check connect bit status
244 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
245 } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC));
248 // entry for JTAG debugger- enable this while loop as a stop for
249 // the JTAG debugger - the JTAG debugger only works after the PLL is
250 // initialized properly
258 //===========================================================================
259 // hal_mem_init - initialize external memory interface
260 //===========================================================================
261 void hal_mem_init(void)
263 volatile unsigned int i;
264 volatile unsigned int dummy;
265 volatile cyg_uint32 regval;
268 // Enable external memory interface
270 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL,
271 CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN);
272 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, regval);
273 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP,
274 regval | CYGARC_HAL_LPC24XX_REG_PCONP_EMC);
277 // Setup pin functions
279 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000);
280 #if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
281 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115);
282 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555);
284 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555);
286 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555);
287 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555);
288 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555);
290 #if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
291 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 1);
292 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
293 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 5);
294 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 1);
295 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
296 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
297 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
298 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
299 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 5);
300 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
301 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 1);
302 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
303 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
305 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
308 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 2);
309 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
310 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 7);
311 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 2);
312 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
313 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
314 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
315 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
316 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 7);
317 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
318 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 2);
319 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
320 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
322 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
327 // Wait 100 ms and then send command: NOP
329 HAL_DELAY_US(100000);
330 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
334 // wait 200 ms and then send command: PRECHARGE-ALL, shortest
335 // possible refresh period
337 HAL_DELAY_US(200000);
338 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
340 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH,
344 // wait 128 ABH clock cycles
346 for(i = 0; i < 64; i++)
348 asm volatile(" nop");
352 // Set correct refresh period and the send command MODE
354 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28);
355 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
359 // Set mode register in SDRAM
361 #if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
362 dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x22 << 11)));
364 dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x33 << 12)));
368 //Send command: NORMAL, enable buffer and wait for 1 second
370 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
372 HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval);
373 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
374 regval | 0x00080000);
377 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2);
378 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2);
379 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0, 0x1f);
380 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f);
381 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0, 0x1f);
382 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf);
383 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0,
386 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2);
387 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2);
388 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1, 0x8);
389 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f);
390 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1, 0x8);
391 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf);
392 HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1,
397 //===========================================================================
399 //===========================================================================
400 void hal_plf_startup(void)
405 // Set clock speed of all peripherals to reset value (CPU speed / 4)
407 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000);
408 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000);
411 // Setup memory acceleration module
413 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0);
414 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4);
422 //===========================================================================
423 // hal_lpc2xxx_set_leds
424 //===========================================================================
425 void hal_lpc24xx_set_leds (int mask)
428 // implement function for setting diagnostic leds
433 #ifdef CYGPKG_DEVS_CAN_LPC2XXX
434 //===========================================================================
435 // Configure CAN pins
436 //===========================================================================
437 void hal_lpc_can_init(cyg_uint8 can_chan_no)
439 CYG_ASSERT(can_chan_no < 2, "CAN channel number out of bounds");
441 cyg_uint32 pinsel0_val;
442 cyg_uint32 pconp_val;
443 HAL_READ_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, pinsel0_val);
444 HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, pconp_val);
448 CYGARC_HAL_LPC24XX_SET_PIN_FUN(pinsel0_val, 0, 1);
449 CYGARC_HAL_LPC24XX_SET_PIN_FUN(pinsel0_val, 1, 1);
450 pconp_val |= CYGARC_HAL_LPC24XX_REG_PCONP_CAN1;
454 CYGARC_HAL_LPC24XX_SET_PIN_FUN(pinsel0_val, 4, 2);
455 CYGARC_HAL_LPC24XX_SET_PIN_FUN(pinsel0_val, 5, 2);
456 pconp_val |= CYGARC_HAL_LPC24XX_REG_PCONP_CAN2;
459 HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, pinsel0_val);
460 HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCONP, pconp_val);
462 #endif // #ifdef CYGPKG_DEVS_CAN_LPC2XXX
464 //--------------------------------------------------------------------------