1 /*==========================================================================
5 // HAL misc variant support code for Philips LPC2xxx
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
13 // Copyright (C) 2004 eCosCentric Limited
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
37 // -------------------------------------------
38 //####ECOSGPLCOPYRIGHTEND####
39 //==========================================================================
40 //#####DESCRIPTIONBEGIN####
43 // Contributors: gthomas, jskov, nickg, tkoeller
45 // Purpose: HAL board support
46 // Description: Implementations of HAL board interfaces
48 //####DESCRIPTIONEND####
50 //========================================================================*/
52 #include <pkgconf/hal.h>
54 #include <cyg/infra/cyg_type.h> // base types
55 #include <cyg/infra/cyg_trac.h> // tracing macros
56 #include <cyg/infra/cyg_ass.h> // assertion macros
58 #include <cyg/hal/hal_io.h> // IO macros
59 #include <cyg/hal/hal_arch.h> // Register state info
60 #include <cyg/hal/hal_diag.h>
61 #include <cyg/hal/hal_intr.h> // necessary?
62 #include <cyg/hal/hal_cache.h>
63 #include <cyg/hal/hal_if.h> // calling interface
64 #include <cyg/hal/hal_misc.h> // helper functions
65 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
66 #include <cyg/hal/drv_api.h> // HAL ISR support
68 #include <cyg/hal/var_io.h> // platform registers
70 static cyg_uint32 lpc_cclk; //CPU clock frequency
71 static cyg_uint32 lpc_pclk; //peripheral devices clock speed
72 //(equal to, half, or quarter of CPU
75 cyg_uint32 hal_lpc_get_pclk(void)
79 // -------------------------------------------------------------------------
82 static cyg_uint32 _period;
84 void hal_clock_initialize(cyg_uint32 period)
86 CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
88 period = period/(lpc_cclk/lpc_pclk);
90 // Disable and reset counter
91 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
93 // set prescale register to 0
94 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxPR, 0);
96 // Set up match register
97 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMR0, period);
99 // Reset and generate interrupt on match
100 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMCR,
101 CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_INT |
102 CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET);
105 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 1);
108 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
110 CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
112 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxIR,
113 CYGARC_HAL_LPC2XXX_REG_TxIR_MR0); // Clear interrupt
115 if (period != _period) {
116 hal_clock_initialize(period);
122 void hal_clock_read(cyg_uint32 *pvalue)
124 CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
127 HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, val);
131 // -------------------------------------------------------------------------
133 // Delay for some number of micro-seconds
136 void hal_delay_us(cyg_int32 usecs)
138 CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
142 // Calculate how many timer ticks the required number of
143 // microseconds equate to. We do this calculation in 64 bit
144 // arithmetic to avoid overflow.
145 ticks = (((cyg_uint64)usecs) * ((cyg_uint64)lpc_pclk))/1000000LL;
147 // Disable and reset counter
148 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
151 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMR0, ticks);
152 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxMCR,
153 CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_STOP |
154 CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET);
156 //set prescale register to 0
157 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxPR, 0);
160 HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 1);
162 // Wait for the match
164 HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, stat);
165 } while (stat < ticks);
168 // -------------------------------------------------------------------------
171 // Return value of VPBDIV register. According to errata doc
172 // we need to read twice consecutively to get correct value
173 cyg_uint32 lpc_get_vpbdiv(void)
176 HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
177 CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
178 HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
179 CYGARC_HAL_LPC2XXX_REG_VPBDIV, div);
184 //Set the two bits in VPBDIV which control peripheral clock division
185 //div must be 1,2 or 4
186 void lpc_set_vpbdiv(int div)
188 cyg_uint8 orig = lpc_get_vpbdiv();
190 // update VPBDIV register
191 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
192 CYGARC_HAL_LPC2XXX_REG_VPBDIV, (div % 4) | (orig & 0xFC));
194 lpc_pclk = lpc_cclk/div;
197 void hal_hardware_init(void)
199 lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED;
201 // Set up eCos/ROM interfaces
206 // -------------------------------------------------------------------------
207 // This routine is called to respond to a hardware interrupt (IRQ). It
208 // should interrogate the hardware and return the IRQ vector number.
209 int hal_IRQ_handler(void)
211 cyg_uint32 irq_num,irq_stat;
212 // Find out which interrupt caused the IRQ
213 // picks the lowest if there are more.
214 // FIXME:try to make use of the VIC for better latency.
215 // That will probably need changes to vectors.S and
216 // other int-related code
217 HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
218 CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT, irq_stat);
219 for (irq_num = 0; irq_num < 32; irq_num++)
220 if (irq_stat & (1<<irq_num)) break;
221 // No valid interrrupt source, treat as spurious interrupt
222 if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
223 irq_num = CYGNUM_HAL_INTERRUPT_NONE;
228 // -------------------------------------------------------------------------
232 void hal_interrupt_mask(int vector)
234 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
235 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
237 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
238 CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR, 1<<vector);
241 void hal_interrupt_unmask(int vector)
243 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
244 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
246 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
247 CYGARC_HAL_LPC2XXX_REG_VICINTENABLE, 1<<vector);
250 void hal_interrupt_acknowledge(int vector)
252 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE +
253 CYGARC_HAL_LPC2XXX_REG_VICVECTADDR, 0);
256 void hal_interrupt_configure(int vector, int level, int up)
260 // only external interrupts are configurable
261 CYG_ASSERT(vector <= CYGNUM_HAL_INTERRUPT_EINT3 &&
262 vector >= CYGNUM_HAL_INTERRUPT_EINT0 , "Invalid vector");
263 #if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
264 // Errata sheet says VPBDIV is corrupted when accessing EXTPOL or EXTMOD
265 // Must be written as 0 and at the end restored to original value
267 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
268 CYGARC_HAL_LPC2XXX_REG_VPBDIV, 0);
270 HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
271 CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
272 HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
273 CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
275 // map int vector to corresponding bit (0..3)
276 vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
285 // high/low or falling/rising
292 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
293 CYGARC_HAL_LPC2XXX_REG_EXTMODE, mode);
294 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
295 CYGARC_HAL_LPC2XXX_REG_EXTPOLAR, pol);
297 #if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
298 // we know this was the original value
299 lpc_set_vpbdiv(lpc_cclk/lpc_pclk);
303 void hal_interrupt_set_level(int vector, int level)
305 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
306 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
307 CYG_ASSERT(level >= 0 && level <= 15, "Invalid level");
311 // Use the watchdog to generate a reset
312 void hal_lpc_watchdog_reset(void)
314 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE +
315 CYGARC_HAL_LPC2XXX_REG_WDTC, 0xFF);
316 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE +
317 CYGARC_HAL_LPC2XXX_REG_WDMOD,
318 CYGARC_HAL_LPC2XXX_REG_WDMOD_WDEN |
319 CYGARC_HAL_LPC2XXX_REG_WDMOD_WDRESET);
321 // feed WD with the two magic values
322 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE +
323 CYGARC_HAL_LPC2XXX_REG_WDFEED,
324 CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC1);
325 HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_WD_BASE +
326 CYGARC_HAL_LPC2XXX_REG_WDFEED,
327 CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC2);
332 //--------------------------------------------------------------------------