packages/hal/arm/mx27/var/v2_0/include/hal_soc.h

   1 //==========================================================================
   2 //
   3 //              hal_soc.h
   4 //
   5 //              SoC chip definitions
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2002 Gary Thomas
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //========================================================================*/
  42
  43 #ifndef __HAL_SOC_H__
  44 #define __HAL_SOC_H__
  45
  46 #include <cyg/hal/mx27_pins.h>
  47
  48 #ifdef __ASSEMBLER__
  49 #define UL(a)            (a)
  50 #define REG8_VAL(a)      (a)
  51 #define REG16_VAL(a) (a)
  52 #define REG32_VAL(a) (a)
  53
  54 #define REG8_PTR(a)      (a)
  55 #define REG16_PTR(a) (a)
  56 #define REG32_PTR(a) (a)
  57
  58 #else /* __ASSEMBLER__ */
  59
  60 #define UL(a)            (a##UL)
  61
  62 extern char HAL_PLATFORM_EXTRA[20];
  63 #define REG8_VAL(a)                                             ((unsigned char)(a))
  64 #define REG16_VAL(a)                                    ((unsigned short)(a))
  65 #define REG32_VAL(a)                                    ((unsigned int)(a))
  66
  67 #define REG8_PTR(a)                                             ((volatile unsigned char *)(a))
  68 #define REG16_PTR(a)                                    ((volatile unsigned short *)(a))
  69 #define REG32_PTR(a)                                    ((volatile unsigned int *)(a))
  70 #define readb(a)                                                (*(volatile unsigned char *)(a))
  71 #define readw(a)                                                (*(volatile unsigned short *)(a))
  72 #define readl(a)                                                (*(volatile unsigned int *)(a))
  73 #define writeb(v,a)                                             (*(volatile unsigned char *)(a) = (v))
  74 #define writew(v,a)                                             (*(volatile unsigned short *)(a) = (v))
  75 #define writel(v,a)                                             (*(volatile unsigned int *)(a) = (v))
  76
  77 #endif /* __ASSEMBLER__ */
  78
  79 /*
  80  * Default Memory Layout Definitions
  81  */
  82
  83 #define SOC_AIPI1_BASE                                  UL(0x10000000)
  84 #define SOC_AIPI2_BASE                                  UL(0x10020000)
  85
  86 #define SOC_AIPI_PAR_OFF                                8
  87
  88 #define CSPI1_BASE_ADDR                                 (SOC_AIPI1_BASE + 0x0E000)
  89 #define CSPI2_BASE_ADDR                                 (SOC_AIPI1_BASE + 0x0F000)
  90 #define CSPI3_BASE_ADDR                                 (SOC_AIPI1_BASE + 0x17000)
  91
  92 #define SOC_CRM_BASE                                    UL(0x10027000)
  93 #define SOC_CRM_CSCR                                    (SOC_CRM_BASE + 0x0)
  94 #define SOC_CRM_MPCTL0                                  (SOC_CRM_BASE + 0x4)
  95 #define SOC_CRM_MPCTL1                                  (SOC_CRM_BASE + 0x8)
  96 #define SOC_CRM_SPCTL0                                  (SOC_CRM_BASE + 0xC)
  97 #define SOC_CRM_SPCTL1                                  (SOC_CRM_BASE + 0x10)
  98 #define SOC_CRM_OSC26MCTL                               (SOC_CRM_BASE + 0x14)
  99 #define SOC_CRM_PCDR0                                   (SOC_CRM_BASE + 0x18)
 100 #define SOC_CRM_PCDR1                                   (SOC_CRM_BASE + 0x1C)
 101 #define SOC_CRM_PCCR0                                   (SOC_CRM_BASE + 0x20)
 102 #define SOC_CRM_PCCR1                                   (SOC_CRM_BASE + 0x24)
 103 #define SOC_CRM_CCSR                                    (SOC_CRM_BASE + 0x28)
 104 #define SOC_CRM_PMCTL                                   (SOC_CRM_BASE + 0x2C)
 105 #define SOC_CRM_PMCOUNT                                 (SOC_CRM_BASE + 0x30)
 106 #define SOC_CRM_WKGDCTL                                 (SOC_CRM_BASE + 0x34)
 107
 108 #define CRM_CSCR_IPDIV_OFFSET                   8
 109 #define CRM_CSCR_BCLKDIV_OFFSET                 9
 110 #define CRM_CSCR_PRESC_OFFSET                   13
 111 #define CRM_CSCR_SSI1_SEL_OFFSET                22
 112 #define CRM_CSCR_SSI2_SEL_OFFSET                23
 113 #define CRM_CSCR_USB_DIV_OFFSET                 28
 114
 115 #define CRM_CSCR_ARM_OFFSET                             12
 116 #define CRM_CSCR_ARM_SRC                                (1<<15)
 117 #define CRM_CSCR_AHB_OFFSET                             8
 118
 119 #define FREQ_26MHZ                                              26000000
 120 #define FREQ_27MHZ                                              27000000
 121 #define FREQ_32768HZ                                    (32768 * 512 * 2)
 122 #define FREQ_32000HZ                                    (32000 * 512 * 2)
 123
 124 #if 0
 125 /* These should be defined in platform specific files */
 126 //#define CLOCK_266_133_66
 127 #define CLOCK_399_133_66
 128 //#define CLOCK_399_100_50
 129
 130 //#define PLL_REF_CLK                                   FREQ_32768HZ
 131 #define PLL_REF_CLK                                             FREQ_26MHZ
 132 //#define PLL_REF_CLK                                   FREQ_32000HZ
 133 #else
 134 #define PLL_REF_CLK             CYGHWR_HAL_ARM_SOC_PLL_REF_CLOCK
 135 #if (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399)
 136   #if (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 133)
 137         #define CLOCK_399_133_66
 138   #elif (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 100)
 139         #define CLOCK_399_100_50
 140   #else
 141         #error Invalid SYSTEM clock (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK) defined
 142   #endif
 143 #elif (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 266)
 144   #define CLOCK_266_133_66
 145 #else
 146   #error Invalid processor clock (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK) defined
 147 #endif
 148 #endif
 149
 150 //                                                                                                      PD                              MFD                             MFI                             MFN
 151 #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)              ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0))
 152
 153 #define SPLL_REF_CLK_kHz                                240000
 154
 155 #if (PLL_REF_CLK == FREQ_32768HZ)
 156         #define PLL_REF_CLK_32768HZ
 157         // SPCTL0  for 240 MHz
 158         #define CRM_SPCTL0_VAL                          CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
 159         #define CRM_SPCTL0_VAL_27MHZ            CRM_SPCTL0_VAL
 160         #define CRM_SPCTL0_VAL2                         CRM_PLL_PCTL_PARAM(4, 567, 14, 173)
 161         #define CRM_SPCTL0_VAL2_27MHZ           CRM_SPCTL0_VAL2
 162         #if defined (CLOCK_266_133_66)
 163                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500)
 164                 #define CRM_MPCTL0_VAL                  CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
 165                 #define CRM_MPCTL0_VAL_27MHZ    CRM_MPCTL0_VAL
 166                 #define CRM_CSCR_VAL                    0x33F00307
 167                 #define CRM_MPCTL0_VAL2                 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
 168                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_MPCTL0_VAL2
 169                 #define CRM_CSCR_VAL2                   0x33F00107
 170         #elif defined (CLOCK_399_133_66)
 171                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
 172                 #define CRM_MPCTL0_VAL                  CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
 173                 #define CRM_MPCTL0_VAL_27MHZ    CRM_MPCTL0_VAL
 174                 #define CRM_CSCR_VAL                    0x33F00507
 175                 #define CRM_MPCTL0_VAL2                 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
 176                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_MPCTL0_VAL2
 177                 #define CRM_CSCR_VAL2                   0x33F08107
 178         #elif defined (CLOCK_399_100_50)
 179                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
 180                 #define CRM_MPCTL0_VAL                  CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
 181                 #define CRM_MPCTL0_VAL_27MHZ    CRM_MPCTL0_VAL
 182                 #define CRM_CSCR_VAL                    0x33F00307
 183                 #define CRM_MPCTL0_VAL2                 CRM_PLL_PCTL_PARAM(1, 100, 11, 94)
 184                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_MPCTL0_VAL2
 185                 #define CRM_CSCR_VAL2                   0x33F00307
 186         #else
 187                 #error This clock is not supported !!!!
 188         #endif   // CLOCK_266_133_66
 189 #else // PLL_REF_CLK == FREQ_32768HZ
 190 #define PLL_VAL_239_999                                 CRM_PLL_PCTL_PARAM(2, 13, 9, 3)
 191 #define PLL_VAL_240                                             CRM_PLL_PCTL_PARAM(3, 13, 13, 11)
 192 #define PLL_VAL_265_999                                 CRM_PLL_PCTL_PARAM(2, 26, 10, 6)
 193 #define PLL_VAL_266                                             CRM_PLL_PCTL_PARAM(3, 26, 15, 9)
 194 #define PLL_VAL_399                                             CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
 195 #define PLL_VAL_399_ALT                                 CRM_PLL_PCTL_PARAM(2, 26, 15, 9)
 196 #define PLL_VAL_400                                             CRM_PLL_PCTL_PARAM(2, 13, 15, 5)
 197 #define PLL_VAL_600                                             CRM_PLL_PCTL_PARAM(1, 13, 11, 7)
 198 #define PLL_VAL_600_ALT                                 CRM_PLL_PCTL_PARAM(1, 52, 11, 28)
 199 #define PLL_VAL_598_5                                   CRM_PLL_PCTL_PARAM(1, 104, 11, 53)
 200
 201         // SPCTL0  for 240 MHz
 202         #define CRM_SPCTL0_VAL                          PLL_VAL_240
 203         #define CRM_SPCTL0_VAL_27MHZ            CRM_PLL_PCTL_PARAM(2, 9, 8, 8)
 204         #define CRM_SPCTL0_VAL2                         CRM_SPCTL0_VAL
 205         #define CRM_SPCTL0_VAL2_27MHZ           CRM_SPCTL0_VAL_27MHZ
 206
 207         #if defined (CLOCK_266_133_66)
 208                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500)
 209                 #define CRM_MPCTL0_VAL                  PLL_VAL_266 // 265.999
 210                 #define CRM_MPCTL0_VAL_27MHZ    CRM_PLL_PCTL_PARAM(2, 15, 9, 13)        // 266.4 MHz
 211                 #define CRM_CSCR_VAL                    0x33F30307
 212                 #define CRM_MPCTL0_VAL2                 PLL_VAL_399
 213                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_PLL_PCTL_PARAM(1, 5, 7, 2)          // 399.6 MHz
 214                 #define CRM_CSCR_VAL2                   0x33F30107
 215         #elif defined (CLOCK_399_133_66)
 216                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
 217                 #define CRM_MPCTL0_VAL                  PLL_VAL_399
 218                 #define CRM_MPCTL0_VAL_27MHZ    CRM_PLL_PCTL_PARAM(1, 5, 7, 2)          // 399.6 MHz
 219                 #define CRM_CSCR_VAL                    0x33F30507
 220                 #define CRM_MPCTL0_VAL2                 CRM_MPCTL0_VAL
 221                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_MPCTL0_VAL_27MHZ
 222                 #define CRM_CSCR_VAL2                   0x33F38107
 223         #elif defined (CLOCK_399_100_50)
 224                 #define MPLL_REF_CLK_kHz                (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
 225                 #define CRM_MPCTL0_VAL                  PLL_VAL_399
 226                 #define CRM_MPCTL0_VAL_27MHZ    CRM_PLL_PCTL_PARAM(1, 5, 7, 2)          // 399.6 MHz
 227                 #define CRM_CSCR_VAL                    0x33F30307
 228                 #define CRM_MPCTL0_VAL2                 PLL_VAL_399
 229                 #define CRM_MPCTL0_VAL2_27MHZ   CRM_MPCTL0_VAL_27MHZ
 230                 #define CRM_CSCR_VAL2                   0x33F38307
 231         #else
 232                 #error This clock is not supported !!!!
 233         #endif   // CLOCK_266_133_66
 234
 235 #endif  // PLL_REF_CLK == FREQ_26MHZ
 236
 237 // system control
 238 #define SOC_SYSCTRL_BASE                                UL(0x10027800)
 239 #define SOC_SYSCTRL_CID                                 (SOC_SYSCTRL_BASE + 0x00)
 240 #define SOC_SYSCTRL_FMCR                                (SOC_SYSCTRL_BASE + 0x14)
 241 #define FMCR_FMS                                                (1 << 5)
 242 #define FMCR_NF_16BIT                                   (1 << 4)
 243 #define FMCR_SLCDC_SEL                                  (1 << 2)
 244 #define FMCR_SDCS1_SEL                                  (1 << 1)
 245 #define FMCR_SDCS0_SEL                                  (1 << 0)
 246 #define SOC_SYSCTRL_GPCR                                (SOC_SYSCTRL_BASE + 0x18)
 247 #define SOC_SYSCTRL_WBCR                                (SOC_SYSCTRL_BASE + 0x1C)
 248 #define SOC_SYSCTRL_DSCR1                               (SOC_SYSCTRL_BASE + 0x20)
 249 #define SOC_SYSCTRL_DSCR2                               (SOC_SYSCTRL_BASE + 0x24)
 250 #define SOC_SYSCTRL_DSCR3                               (SOC_SYSCTRL_BASE + 0x28)
 251 #define SOC_SYSCTRL_DSCR4                               (SOC_SYSCTRL_BASE + 0x2C)
 252 #define SOC_SYSCTRL_DSCR5                               (SOC_SYSCTRL_BASE + 0x30)
 253 #define SOC_SYSCTRL_DSCR6                               (SOC_SYSCTRL_BASE + 0x34)
 254 #define SOC_SYSCTRL_DSCR7                               (SOC_SYSCTRL_BASE + 0x38)
 255 #define SOC_SYSCTRL_DSCR8                               (SOC_SYSCTRL_BASE + 0x3C)
 256 #define SOC_SYSCTRL_DSCR9                               (SOC_SYSCTRL_BASE + 0x40)
 257 #define SOC_SYSCTRL_DSCR10                              (SOC_SYSCTRL_BASE + 0x44)
 258 #define SOC_SYSCTRL_DSCR11                              (SOC_SYSCTRL_BASE + 0x48)
 259 #define SOC_SYSCTRL_DSCR12                              (SOC_SYSCTRL_BASE + 0x4C)
 260 #define SOC_SYSCTRL_DSCR13                              (SOC_SYSCTRL_BASE + 0x50)
 261 #define SOC_SYSCTRL_PSCR                                (SOC_SYSCTRL_BASE + 0x54)
 262 #define SOC_SYSCTRL_PCSR                                (SOC_SYSCTRL_BASE + 0x58)
 263 #define SOC_SYSCTRL_PMCR                                (SOC_SYSCTRL_BASE + 0x60)
 264 #define SOC_SYSCTRL_DCVR0                               (SOC_SYSCTRL_BASE + 0x64)
 265 #define SOC_SYSCTRL_DCVR1                               (SOC_SYSCTRL_BASE + 0x68)
 266 #define SOC_SYSCTRL_DCVR2                               (SOC_SYSCTRL_BASE + 0x6C)
 267 #define SOC_SYSCTRL_DCVR3                               (SOC_SYSCTRL_BASE + 0x70)
 268
 269 // Interrupt Controller Register Definitions.
 270 #define SOC_AITC_BASE                                   UL(0x10040000)
 271 #define SOC_AITC_INTCNTL                                (SOC_AITC_BASE + 0x00)
 272 #define SOC_AITC_NIMASK                                 (SOC_AITC_BASE + 0x04)
 273 #define SOC_AITC_INTENNUM                               (SOC_AITC_BASE + 0x08)
 274 #define SOC_AITC_INTDISNUM                              (SOC_AITC_BASE + 0x0C)
 275 #define SOC_AITC_INTENABLEH                             (SOC_AITC_BASE + 0x10)
 276 #define SOC_AITC_INTENABLEL                             (SOC_AITC_BASE + 0x14)
 277 #define SOC_AITC_INTTYPEH                               (SOC_AITC_BASE + 0x18)
 278 #define SOC_AITC_INTTYPEL                               (SOC_AITC_BASE + 0x1C)
 279 #define SOC_AITC_NIPRIORITY7                    (SOC_AITC_BASE + 0x20)
 280 #define SOC_AITC_NIPRIORITY6                    (SOC_AITC_BASE + 0x24)
 281 #define SOC_AITC_NIPRIORITY5                    (SOC_AITC_BASE + 0x28)
 282 #define SOC_AITC_NIPRIORITY4                    (SOC_AITC_BASE + 0x2C)
 283 #define SOC_AITC_NIPRIORITY3                    (SOC_AITC_BASE + 0x30)
 284 #define SOC_AITC_NIPRIORITY2                    (SOC_AITC_BASE + 0x34)
 285 #define SOC_AITC_NIPRIORITY1                    (SOC_AITC_BASE + 0x38)
 286 #define SOC_AITC_NIPRIORITY0                    (SOC_AITC_BASE + 0x3C)
 287
 288 #define UART_WIDTH_32
 289
 290 // UART Base Addresses
 291 #define SOC_UART1_BASE                                  UL(0x1000A000)
 292 #define SOC_UART2_BASE                                  UL(0x1000B000)
 293 #define SOC_UART3_BASE                                  UL(0x1000C000)
 294 #define SOC_UART4_BASE                                  UL(0x1000D000)
 295 #define SOC_UART5_BASE                                  UL(0x1001B000)
 296 #define SOC_UART6_BASE                                  UL(0x1001C000)
 297
 298 #define SOC_MAX_BASE                                    UL(0x1003F000)
 299 // Slave port base offset
 300 #define MAX_SLAVE_PORT0_OFFSET                  0x0
 301 #define MAX_SLAVE_PORT1_OFFSET                  0x100
 302 #define MAX_SLAVE_PORT2_OFFSET                  0x200
 303 // Register offset for slave port
 304 #define MAX_SLAVE_MPR_OFFSET                    0x0                             /* Master Priority register */
 305 #define MAX_SLAVE_AMPR_OFFSET                   0x4                             /* Alternate Master Priority register */
 306 #define MAX_SLAVE_SGPCR_OFFSET                  0x10    /* Slave General Purpose Control register */
 307 #define MAX_SLAVE_ASGPCR_OFFSET                 0x14    /* Alternate Slave General Purpose control register */
 308 // Master port base offset
 309 #define MAX_MASTER_PORT0_OFFSET                 0x800
 310 #define MAX_MASTER_PORT1_OFFSET                 0x900
 311 #define MAX_MASTER_PORT2_OFFSET                 0xA00
 312 #define MAX_MASTER_PORT3_OFFSET                 0xB00
 313 #define MAX_MASTER_PORT4_OFFSET                 0xC00
 314 #define MAX_MASTER_PORT5_OFFSET                 0xD00
 315 // Register offset for master port
 316 #define MAX_MASTER_MGPCR_OFFSET                 0x0                             /* Master General Purpose Control Register */
 317 /*
 318  * MX27 GPIO Register Definitions
 319  */
 320 #define SOC_GPIOA_BASE                                  UL(0x10015000)
 321 #define SOC_GPIOB_BASE                                  UL(0x10015100)
 322 #define SOC_GPIOC_BASE                                  UL(0x10015200)
 323 #define SOC_GPIOD_BASE                                  UL(0x10015300)
 324 #define SOC_GPIOE_BASE                                  UL(0x10015400)
 325 #define SOC_GPIOF_BASE                                  UL(0x10015500)
 326 #define SOC_GPIO_PMASK                                  UL(0x10015600)
 327 #define GPIO_DDIR                                               0x0                             /* Data direction reg */
 328 #define GPIO_OCR1                                               0x4                             /* Output config reg 1 */
 329 #define GPIO_OCR2                                               0x8                             /* Output config reg 2 */
 330 #define GPIO_ICONFA1                                    0xC                             /* Input config reg A1 */
 331 #define GPIO_ICONFA2                                    0x10                    /* Input config reg A2 */
 332 #define GPIO_ICONFB1                                    0x14                    /* Input config reg B1 */
 333 #define GPIO_ICONFB2                                    0x18                    /* Input config reg B2 */
 334 #define GPIO_DR                                                 0x1C                    /* Data reg */
 335 #define GPIO_GIUS                                               0x20                    /* GPIO in use reg */
 336 #define GPIO_SSR                                                0x24                    /* Sample status reg */
 337 #define GPIO_ICR1                                               0x28                    /* Int config reg 1 */
 338 #define GPIO_ICR2                                               0x2C                    /* Int config reg 2 */
 339 #define GPIO_IMR                                                0x30                    /* Int mask reg */
 340 #define GPIO_ISR                                                0x34                    /* Int status reg */
 341 #define GPIO_GPR                                                0x38                    /* Gen purpose reg */
 342 #define GPIO_SWR                                                0x3C                    /* Software reset reg */
 343 #define GPIO_PUEN                                               0x40                    /* Pull-up enable reg */
 344
 345 #define GPIO_OCR_A                                              0                               /* External input a_IN */
 346 #define GPIO_OCR_B                                              1                               /* External input b_IN */
 347 #define GPIO_OCR_C                                              2                               /* External input c_IN */
 348 #define GPIO_OCR_DR                                             3                               /* Data register */
 349 #define GPIO_ICONF_In                                   0                               /* GPIO-in */
 350 #define GPIO_ICONF_Isr                                  1                               /* Interrupt status register */
 351 #define GPIO_ICONF_0                                    2                               /* 0 */
 352 #define GPIO_ICONF_1                                    3                               /* 1 */
 353 #define GPIO_ICR_PosEdge                                0                               /* Positive edge */
 354 #define GPIO_ICR_NegEdge                                1                               /* Negative edge */
 355 #define GPIO_ICR_PosLvl                                 2                               /* Positive level */
 356 #define GPIO_ICR_NegLvl                                 3                               /* Negative level */
 357 #define GPIO_SWR_SWR                                    1                               /* Software reset */
 358
 359 /*
 360  * GPT Timer defines
 361  */
 362 #define HAL_DELAY_TIMER                                 SOC_GPT2_BASE   // use timer2 for hal_delay_us()
 363
 364 #define SOC_GPT1_BASE                                   UL(0x10003000)
 365 #define SOC_GPT2_BASE                                   UL(0x10004000)
 366 #define SOC_GPT3_BASE                                   UL(0x10005000)
 367 #define SOC_GPT4_BASE                                   UL(0x10019000)
 368 #define SOC_GPT5_BASE                                   UL(0x1001A000)
 369 #define SOC_GPT6_BASE                                   UL(0x1001F000)
 370 #define GPT_TCTL_OFFSET                                 0x0
 371 #define GPT_TPRER_OFFSET                                0x4
 372 #define GPT_TCMP_OFFSET                                 0x8
 373 #define GPT_TCR_OFFSET                                  0xC
 374 #define GPT_TCN_OFFSET                                  0x10
 375 #define GPT_TSTAT_OFFSET                                0x14
 376 #define MX_STARTUP_DELAY                                (1000000 / 10)  // 0.1s delay to get around the ethernet reset failure problem
 377
 378 #define TIMER_PRESCALER                                 3
 379 #define SOC_SI_ID_REG                                   UL(0x10027800)
 380 #define SOC_SILICONID_Rev1_0                    0x0
 381 #define SOC_SILICONID_Rev2_0                    0x1
 382 #define SOC_SILICONID_Rev2_1                    0x2
 383 #define CHIP_REV_1_x                                    1
 384 #define CHIP_REV_2_x                                    2
 385 #define CHIP_REV_3_0                                    3
 386 #define CHIP_REV_3_1                                    4
 387 #define CHIP_REV_unknown                                0x100
 388
 389 #define SOC_WDOG_BASE                                   UL(0x10002000)
 390 #define WDOG_BASE_ADDR                                  SOC_WDOG_BASE
 391
 392 #define NFC_BASE                                                UL(0xD8000000)
 393 #define SOC_ESDCTL_BASE                                 UL(0xD8001000)
 394 #define SOC_EIM_BASE                                    UL(0xD8002000)
 395 #define SOC_M3IF_BASE                                   UL(0xD8003000)
 396 #define SOC_PCMCIA_BASE                                 UL(0xD8004000)
 397
 398 #define SOC_CS0_CTL_BASE                                SOC_EIM_BASE
 399 #define SOC_CS1_CTL_BASE                                (SOC_EIM_BASE + 0x10)
 400 #define SOC_CS2_CTL_BASE                                (SOC_EIM_BASE + 0x20)
 401 #define SOC_CS3_CTL_BASE                                (SOC_EIM_BASE + 0x30)
 402 #define SOC_CS4_CTL_BASE                                (SOC_EIM_BASE + 0x40)
 403 #define SOC_CS5_CTL_BASE                                (SOC_EIM_BASE + 0x50)
 404
 405 /* WEIM */
 406 #define CSCRU_OFFSET                                    0x00
 407 #define CSCRL_OFFSET                                    0x04
 408 #define CSCRA_OFFSET                                    0x08
 409 #define CSWCR_OFFSET                                    0x60
 410
 411 // Memories
 412 #define SOC_CSD0_BASE                                   UL(0xA0000000)
 413 #define SOC_CSD1_BASE                                   UL(0xB0000000)
 414 #define SOC_CS0_BASE                                    UL(0xC0000000)
 415 #define CS0_BASE_ADDR                                   SOC_CS0_BASE
 416 #define SOC_CS1_BASE                                    UL(0xC8000000)
 417 #define SOC_CS2_BASE                                    UL(0xD0000000)
 418 #define SOC_CS3_BASE                                    UL(0xD2000000)
 419 #define SOC_CS4_BASE                                    UL(0xD4000000)
 420 #define SOC_CS5_BASE                                    UL(0xD6000000)
 421 #define NAND_REG_BASE                                   (NFC_BASE + 0xE00)
 422
 423 #define SOC_IIM_BASE                                    UL(0x10028000)
 424 #define SOC_FEC_MAC_BASE                                UL(0x10028C04)
 425 #define SOC_FEC_MAC_BASE2                               UL(0x10028814)
 426 #define SOC_FEC_BASE                                    UL(0x1002B000)
 427 #define IIM_BASE_ADDR                                   SOC_IIM_BASE
 428 /* IIM */
 429 #define CHIP_REV_1_0                                    0x0                                             /* PASS 1.0 */
 430 #define CHIP_REV_2_0                                    0x1                                             /* PASS 2.0 */
 431
 432 #define IIM_STAT_OFF                                    0x00
 433 #define IIM_STAT_BUSY                                   (1 << 7)
 434 #define IIM_STAT_PRGD                                   (1 << 1)
 435 #define IIM_STAT_SNSD                                   (1 << 0)
 436 #define IIM_STATM_OFF                                   0x04
 437 #define IIM_ERR_OFF                                             0x08
 438 #define IIM_ERR_PRGE                                    (1 << 7)
 439 #define IIM_ERR_WPE                                             (1 << 6)
 440 #define IIM_ERR_OPE                                             (1 << 5)
 441 #define IIM_ERR_RPE                                             (1 << 4)
 442 #define IIM_ERR_WLRE                                    (1 << 3)
 443 #define IIM_ERR_SNSE                                    (1 << 2)
 444 #define IIM_ERR_PARITYE                                 (1 << 1)
 445 #define IIM_EMASK_OFF                                   0x0C
 446 #define IIM_FCTL_OFF                                    0x10
 447 #define IIM_UA_OFF                                              0x14
 448 #define IIM_LA_OFF                                              0x18
 449 #define IIM_SDAT_OFF                                    0x1C
 450 #define IIM_PREV_OFF                                    0x20
 451 #define IIM_SREV_OFF                                    0x24
 452 #define IIM_PREG_P_OFF                                  0x28
 453 #define IIM_SCS0_OFF                                    0x2C
 454 #define IIM_SCS1_P_OFF                                  0x30
 455 #define IIM_SCS2_OFF                                    0x34
 456 #define IIM_SCS3_P_OFF                                  0x38
 457
 458 #define ESDCTL_ESDCTL0                                  0x00
 459 #define ESDCTL_ESDCFG0                                  0x04
 460 #define ESDCTL_ESDCTL1                                  0x08
 461 #define ESDCTL_ESDCFG1                                  0x0C
 462 #define ESDCTL_ESDMISC                                  0x10
 463 #define ESDCTL_ESDCDLY1                                 0x20
 464 #define ESDCTL_ESDCDLY2                                 0x24
 465 #define ESDCTL_ESDCDLY3                                 0x28
 466 #define ESDCTL_ESDCDLY4                                 0x2c
 467 #define ESDCTL_ESDCDLY5                                 0x30
 468
 469 #define NFC_BUFSIZE_REG_OFF                             (0 + 0x00)
 470 #define RAM_BUFFER_ADDRESS_REG_OFF              (0 + 0x04)
 471 #define NAND_FLASH_ADD_REG_OFF                  (0 + 0x06)
 472 #define NAND_FLASH_CMD_REG_OFF                  (0 + 0x08)
 473 #define NFC_CONFIGURATION_REG_OFF               (0 + 0x0A)
 474 #define ECC_STATUS_RESULT_REG_OFF               (0 + 0x0C)
 475 #define ECC_RSLT_MAIN_AREA_REG_OFF              (0 + 0x0E)
 476 #define ECC_RSLT_SPARE_AREA_REG_OFF             (0 + 0x10)
 477 #define NF_WR_PROT_REG_OFF                              (0 + 0x12)
 478 #define UNLOCK_START_BLK_ADD_REG_OFF    (0 + 0x14)
 479 #define UNLOCK_END_BLK_ADD_REG_OFF              (0 + 0x16)
 480 #define NAND_FLASH_WR_PR_ST_REG_OFF             (0 + 0x18)
 481 #define NAND_FLASH_CONFIG1_REG_OFF              (0 + 0x1A)
 482 #define NAND_FLASH_CONFIG2_REG_OFF              (0 + 0x1C)
 483 #define RAM_BUFFER_ADDRESS_RBA_3                0x3
 484 #define NFC_BUFSIZE_1KB                                 0x0
 485 #define NFC_BUFSIZE_2KB                                 0x1
 486 #define NFC_CONFIGURATION_UNLOCKED              0x2
 487 #define ECC_STATUS_RESULT_NO_ERR                0x0
 488 #define ECC_STATUS_RESULT_1BIT_ERR              0x1
 489 #define ECC_STATUS_RESULT_2BIT_ERR              0x2
 490 #define NF_WR_PROT_UNLOCK                               0x4
 491 #define NAND_FLASH_CONFIG1_FORCE_CE             (1 << 7)
 492 #define NAND_FLASH_CONFIG1_RST                  (1 << 6)
 493 #define NAND_FLASH_CONFIG1_BIG                  (1 << 5)
 494 #define NAND_FLASH_CONFIG1_INT_MSK              (1 << 4)
 495 #define NAND_FLASH_CONFIG1_ECC_EN               (1 << 3)
 496 #define NAND_FLASH_CONFIG1_SP_EN                (1 << 2)
 497 #define NAND_FLASH_CONFIG2_INT_DONE             (1 << 15)
 498 #define NAND_FLASH_CONFIG2_FDO_PAGE             (0 << 3)
 499 #define NAND_FLASH_CONFIG2_FDO_ID               (2 << 3)
 500 #define NAND_FLASH_CONFIG2_FDO_STATUS   (4 << 3)
 501 #define NAND_FLASH_CONFIG2_FDI_EN               (1 << 2)
 502 #define NAND_FLASH_CONFIG2_FADD_EN              (1 << 1)
 503 #define NAND_FLASH_CONFIG2_FCMD_EN              (1 << 0)
 504 #define FDO_PAGE_SPARE_VAL                              0x8
 505
 506 #define MXC_NAND_BASE_DUMMY                             UL(0xE0000000)
 507 #define NOR_FLASH_BOOT                                  0
 508 #define NAND_FLASH_BOOT                                 0x10
 509 #define SDRAM_NON_FLASH_BOOT                    0x20
 510 #define MXCBOOT_FLAG_REG                                SOC_AITC_NIPRIORITY7
 511
 512 #define MXCFIS_NOTHING                                  0x00000000
 513 #define MXCFIS_NAND                                             0x10000000
 514 #define MXCFIS_NOR                                              0x20000000
 515 #define MXCFIS_FLAG_REG                                 SOC_AITC_NIPRIORITY6
 516 #ifndef MXCFLASH_SELECT_NAND
 517 #define IS_BOOTING_FROM_NAND()                  0
 518 #else
 519 #define IS_BOOTING_FROM_NAND()                  (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
 520 #endif
 521 #ifndef MXCFLASH_SELECT_NOR
 522 #define IS_BOOTING_FROM_NOR()                   0
 523 #else
 524 #define IS_BOOTING_FROM_NOR()                   (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
 525 #endif
 526 #ifndef IS_BOOTING_FROM_SDRAM
 527 #define IS_BOOTING_FROM_SDRAM()                 (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
 528 #endif
 529
 530 #ifndef MXCFLASH_SELECT_NAND
 531 #define IS_FIS_FROM_NAND()                              0
 532 #else
 533 #ifndef MXCFLASH_SELECT_NOR
 534 #define IS_FIS_FROM_NAND()                              1
 535 #else
 536 #define IS_FIS_FROM_NAND()                              (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
 537 #endif
 538 #endif
 539
 540 #ifndef MXCFLASH_SELECT_NOR
 541 #define IS_FIS_FROM_NOR()                               0
 542 #else
 543 #define IS_FIS_FROM_NOR()                               (!IS_FIS_FROM_NAND())
 544 #endif
 545
 546 #define MXC_ASSERT_NOR_BOOT()                   writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
 547 #define MXC_ASSERT_NAND_BOOT()                  writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
 548
 549 #define SERIAL_DOWNLOAD_MAGIC                   0x000000AA
 550 #define SERIAL_DOWNLOAD_MAGIC_REG               SOC_AITC_NIPRIORITY3
 551 #define SERIAL_DOWNLOAD_SRC_REG                 SOC_AITC_NIPRIORITY2
 552 #define SERIAL_DOWNLOAD_TGT_REG                 SOC_AITC_NIPRIORITY1
 553 #define SERIAL_DOWNLOAD_SZ_REG                  SOC_AITC_NIPRIORITY0
 554
 555 #if !defined(__ASSEMBLER__)
 556 void cyg_hal_plf_serial_init(void);
 557 void cyg_hal_plf_serial_stop(void);
 558 void hal_delay_us(unsigned int usecs);
 559 #define HAL_DELAY_US(n)                                 hal_delay_us(n)
 560
 561 enum plls {
 562                 MCU_PLL = SOC_CRM_MPCTL0,
 563                 SER_PLL = SOC_CRM_SPCTL0,
 564 };
 565
 566 enum main_clocks {
 567                 CPU_CLK,
 568                 AHB_CLK,
 569                 IPG_CLK,
 570                 NFC_CLK,
 571                 USB_CLK,
 572 };
 573
 574 enum peri_clocks {
 575                 PER_CLK1,
 576                 PER_CLK2,
 577                 PER_CLK3,
 578                 PER_CLK4,
 579                 H264_BAUD,
 580                 MSHC_BAUD,
 581                 SSI1_BAUD,
 582                 SSI2_BAUD,
 583                 SPI1_CLK = CSPI1_BASE_ADDR,
 584                 SPI2_CLK = CSPI2_BASE_ADDR,
 585 };
 586
 587 unsigned int pll_clock(enum plls pll);
 588
 589 unsigned int get_main_clock(enum main_clocks clk);
 590
 591 unsigned int get_peri_clock(enum peri_clocks clk);
 592 #define GPIO_PORT_NUM                   6
 593 #define GPIO_NUM_PIN                    32
 594 #define MXC_MAX_GPIO_LINES              (GPIO_NUM_PIN * GPIO_PORT_NUM)
 595
 596 #define IOMUX_TO_GPIO(pin)              ((((unsigned int)pin >> MUX_IO_P) * GPIO_NUM_PIN) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) -1)))
 597 #define IOMUX_TO_IRQ(pin)               (MXC_GPIO_BASE + IOMUX_TO_GPIO(pin))
 598 #define GPIO_TO_PORT(n)                 (n / GPIO_NUM_PIN)
 599 #define GPIO_TO_INDEX(n)                (n % GPIO_NUM_PIN)
 600
 601 typedef enum {
 602                 GPIO_MUX_PRIMARY,
 603                 GPIO_MUX_ALT,
 604                 GPIO_MUX_GPIO,
 605                 GPIO_MUX_INPUT1,
 606                 GPIO_MUX_INPUT2,
 607                 GPIO_MUX_OUTPUT1,
 608                 GPIO_MUX_OUTPUT2,
 609                 GPIO_MUX_OUTPUT3,
 610 } gpio_mux_mode_t;
 611
 612 int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
 613 void clock_spi_enable(unsigned int spi_clk);
 614
 615 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
 616
 617 #endif //#if !defined(__ASSEMBLER__)
 618
 619 #define HAL_MMU_OFF()                                                                                                   \
 620 CYG_MACRO_START                                                                                                                 \
 621         asm volatile (                                                                                                          \
 622                 "1: "                                                                                                                   \
 623                 "mrc p15, 0, r15, c7, c14, 3;"  /*test clean and inval*/                \
 624                 "bne 1b;"                                                                                                               \
 625                 "mov r0, #0;"                                                                                                   \
 626                 "mcr p15,0,r0,c7,c10,4;"   /* Data Write Barrier */                             \
 627                 "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */                                \
 628                 "mrc p15,0,r0,c1,c0,0;" /* read c1 */                                                   \
 629                 "bic r0,r0,#0x7;" /* disable DCache and MMU */                                  \
 630                 "bic r0,r0,#0x1000;" /* disable ICache */                                               \
 631                 "mcr p15,0,r0,c1,c0,0;" /*      */                                                                      \
 632                 "nop;" /* flush i+d-TLBs */                                                                             \
 633                 "nop;" /* flush i+d-TLBs */                                                                             \
 634                 "nop;" /* flush i+d-TLBs */                                                                             \
 635                 :                                                                                                                               \
 636                 :                                                                                                                               \
 637                 : "r0","memory" /* clobber list */);                                                    \
 638 CYG_MACRO_END
 639
 640 #endif /* __HAL_SOC_H__ */