1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //===========================================================================*/
42 #include <pkgconf/hal.h>
44 #include <cyg/infra/cyg_type.h> // base types
45 #include <cyg/infra/cyg_trac.h> // tracing macros
46 #include <cyg/infra/cyg_ass.h> // assertion macros
48 #include <cyg/hal/hal_arch.h> // basic machine info
49 #include <cyg/hal/hal_intr.h> // interrupt macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_diag.h>
52 #include <cyg/hal/hal_if.h> // Calling-if API
53 #include <cyg/hal/drv_api.h> // driver API
54 #include <cyg/hal/hal_misc.h> // Helper functions
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/karo_tx37.h> // Platform specifics
58 extern void cyg_hal_plf_serial_init(void);
60 void cyg_hal_plf_comms_init(void)
62 static int initialized = 0;
68 cyg_hal_plf_serial_init();
71 //-----------------------------------------------------------------------------
72 // Based on 3.6864 MHz xtal
73 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
74 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
75 #define CYG_DEV_SERIAL_BAUD_LSB 0x18
77 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
78 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
79 #define CYG_DEV_SERIAL_BAUD_LSB 0x0C
81 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
82 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
83 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
85 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
86 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
87 #define CYG_DEV_SERIAL_BAUD_LSB 0x04
89 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
90 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
91 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
94 #ifndef CYG_DEV_SERIAL_BAUD_MSB
95 #error Missing/incorrect serial baud rate defined - CDL error?
98 //-----------------------------------------------------------------------------
99 // Define the serial registers. The board is equipped with a 16552
102 #if defined (EXT_UART_x16)
103 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
104 #define HAL_READ_UINT_UART HAL_READ_UINT16
105 typedef cyg_uint16 uart_width;
106 #elif defined (EXT_UART_x32)
107 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
108 #define HAL_READ_UINT_UART HAL_READ_UINT32
109 typedef cyg_uint32 uart_width;
111 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
112 #define HAL_READ_UINT_UART HAL_READ_UINT8
113 typedef cyg_uint8 uart_width;
116 #define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
117 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
118 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
119 #define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
120 #define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
121 #define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
122 #define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
123 #define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
124 #define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
125 #define CYG_DEV_SERIAL_MCR 0x04
126 #define CYG_DEV_SERIAL_MCR_A 0x04
127 #define CYG_DEV_SERIAL_MCR_B 0x04
128 #define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
129 #define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
130 #define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
132 // The interrupt enable register bits.
133 #define SIO_IER_ERDAI 0x01 // enable received data available irq
134 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
135 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
136 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
138 // The interrupt identification register bits.
139 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
140 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
144 // The line status register bits.
145 #define SIO_LSR_DR 0x01 // data ready
146 #define SIO_LSR_OE 0x02 // overrun error
147 #define SIO_LSR_PE 0x04 // parity error
148 #define SIO_LSR_FE 0x08 // framing error
149 #define SIO_LSR_BI 0x10 // break interrupt
150 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
151 #define SIO_LSR_TEMT 0x40 // transmitter register empty
152 #define SIO_LSR_ERR 0x80 // any error condition
154 // The modem status register bits.
155 #define SIO_MSR_DCTS 0x01 // delta clear to send
156 #define SIO_MSR_DDSR 0x02 // delta data set ready
157 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
158 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
159 #define SIO_MSR_CTS 0x10 // clear to send
160 #define SIO_MSR_DSR 0x20 // data set ready
161 #define SIO_MSR_RI 0x40 // ring indicator
162 #define SIO_MSR_DCD 0x80 // data carrier detect
164 // The line control register bits.
165 #define SIO_LCR_WLS0 0x01 // word length select bit 0
166 #define SIO_LCR_WLS1 0x02 // word length select bit 1
167 #define SIO_LCR_STB 0x04 // number of stop bits
168 #define SIO_LCR_PEN 0x08 // parity enable
169 #define SIO_LCR_EPS 0x10 // even parity select
170 #define SIO_LCR_SP 0x20 // stick parity
171 #define SIO_LCR_SB 0x40 // set break
172 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
174 // The FIFO control register
175 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
176 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
177 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
179 //-----------------------------------------------------------------------------
182 //#define x_debug_uart_log_buf
183 #ifdef x_debug_uart_log_buf
184 #define x_DIAG_BUFSIZE 2048
185 static char __x_log_buf[x_DIAG_BUFSIZE];
186 static int x_diag_bp = 0;
190 //=============================================================================
191 // Compatibility with older stubs
192 //=============================================================================
194 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
196 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
201 #ifdef CYGSEM_HAL_ROM_MONITOR
202 #define CYG_HAL_STARTUP_ROM
203 #define CYG_HAL_STARTUP_ROMRAM
204 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
207 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
208 #define HAL_DIAG_USES_HARDWARE
209 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
210 #define HAL_DIAG_USES_HARDWARE
211 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
212 #define HAL_DIAG_USES_HARDWARE
215 static channel_data_t channel = {
216 (uart_width*) _BASE, 0, 0
219 #ifdef HAL_DIAG_USES_HARDWARE
221 void hal_diag_init(void)
224 char *msg = "\n\rARM eCos\n\r";
229 init_duart_channel(&channel);
231 while (*msg) hal_diag_write_char(*msg++);
235 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
236 #define DIAG_BUFSIZE 32
238 #define DIAG_BUFSIZE 2048
240 static char diag_buffer[DIAG_BUFSIZE];
241 static int diag_bp = 0;
244 void hal_diag_write_char(char c)
250 cyg_hal_plf_duart_putc(&channel, c)
253 diag_buffer[diag_bp++] = c;
254 if (diag_bp == DIAG_BUFSIZE) {
261 void hal_diag_read_char(char *c)
263 *c = cyg_hal_plf_duart_getc(&channel);
266 #else // HAL_DIAG relies on GDB
268 // Initialize diag port - assume GDB channel is already set up
269 void hal_diag_init(void)
271 if (0) init_duart_channel(&channel); // avoid warning
274 // Actually send character down the wire
275 static void hal_diag_write_char_serial(char c)
277 cyg_hal_plf_duart_putc(&channel, c);
280 static bool hal_diag_read_serial(char *c)
282 long timeout = 1000000000; // A long time...
284 while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
285 if (0 == --timeout) return false;
290 void hal_diag_read_char(char *c)
292 while (!hal_diag_read_serial(c)) ;
295 void hal_diag_write_char(char c)
297 static char line[100];
300 // No need to send CRs
301 if (c == '\r') return;
305 if (c == '\n' || pos == sizeof(line)) {
306 CYG_INTERRUPT_STATE old;
308 // Disable interrupts. This prevents GDB trying to interrupt us
309 // while we are in the middle of sending a packet. The serial
310 // receive interrupt will be seen when we re-enable interrupts
313 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
314 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
316 HAL_DISABLE_INTERRUPTS(old);
320 static char hex[] = "0123456789ABCDEF";
325 hal_diag_write_char_serial('$');
326 hal_diag_write_char_serial('O');
328 for (i = 0; i < pos; i++) {
330 char h = hex[(ch>>4)&0xF];
331 char l = hex[ch&0xF];
332 hal_diag_write_char_serial(h);
333 hal_diag_write_char_serial(l);
337 hal_diag_write_char_serial('#');
338 hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
339 hal_diag_write_char_serial(hex[csum&0xF]);
341 // Wait for the ACK character '+' from GDB here and handle
342 // receiving a ^C instead. This is the reason for this clause
344 if (!hal_diag_read_serial(&c1))
345 continue; // No response - try sending packet again
348 break; // a good acknowledge
350 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
351 cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
353 // Ctrl-C: breakpoint.
354 cyg_hal_gdb_interrupt (__builtin_return_address(0));
358 // otherwise, loop round again
363 // And re-enable interrupts
364 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
365 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
367 HAL_RESTORE_INTERRUPTS(old);
376 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
378 /*---------------------------------------------------------------------------*/