packages/hal/arm/xscale/pxa2x0/v2_0/include/hal_pxa2x0.h

   1 //==========================================================================
   2 //
   3 //      hal_pxa2x0.h
   4 //
   5 //      HAL misc board support definitions for PXA250/210
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2003 Gary Thomas
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //==========================================================================
  42 //#####DESCRIPTIONBEGIN####
  43 //
  44 // Author(s):    <knud.woehler@microplex.de>
  45 // Date:         2003-01-06
  46 //
  47 //####DESCRIPTIONEND####
  48 //
  49 //==========================================================================
  50 #ifndef CYGONCE_HAL_ARM_PXA2X0_H
  51 #define CYGONCE_HAL_ARM_PXA2X0_H
  52
  53 #include <pkgconf/system.h>
  54 #include <cyg/hal/hal_xscale.h>
  55
  56 #ifdef __ASSEMBLER__
  57 #define PXA2X0_REGISTER(a)      (a)
  58 #else
  59 #define PXA2X0_REGISTER(a)      ((volatile unsigned long *)(a))
  60 #endif
  61
  62 // Memory layout
  63 #define PXA2X0_CS0_BASE                         (0x00000000)
  64 #define PXA2X0_CS1_BASE                         (0x04000000)
  65 #define PXA2X0_CS2_BASE                         (0x08000000)
  66 #define PXA2X0_CS3_BASE                         (0x0c000000)
  67 #define PXA2X0_CS4_BASE                         (0x10000000)
  68 #define PXA2X0_CS5_BASE                         (0x14000000)
  69
  70 #define PXA2X0_PCMCIA0_BASE                     (0x20000000)
  71 #define PXA2X0_PCMCIA1_BASE                     (0x30000000)
  72
  73 #define PXA2X0_PERIPHERALS_BASE         (0x40000000)
  74 #define PXA2X0_LCD_BASE                         (0x44000000)
  75 #define PXA2X0_MEMORY_CTL_BASE          (0x48000000)
  76
  77 #define PXA2X0_RAM_BANK0_BASE           (0xA0000000)
  78 #define PXA2X0_RAM_BANK1_BASE           (0xA4000000)
  79 #define PXA2X0_RAM_BANK2_BASE           (0xA8000000)
  80 #define PXA2X0_RAM_BANK3_BASE           (0xAc000000)
  81
  82 #define PXA2X0_CACHE_FLUSH_BASE         (0xc0000000)
  83
  84 #define DCACHE_FLUSH_AREA                       0xc0000000
  85
  86 // DMA Controller
  87 #define PXA2X0_DMA_CTL_BASE                     ( PXA2X0_PERIPHERALS_BASE + 0x0000000 )
  88 #define PXA2X0_DCSR0                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0000 )
  89 #define PXA2X0_DCSR1                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0004 )
  90 #define PXA2X0_DCSR2                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0008 )
  91 #define PXA2X0_DCSR3                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x000c )
  92 #define PXA2X0_DCSR4                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0010 )
  93 #define PXA2X0_DCSR5                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0014 )
  94 #define PXA2X0_DCSR6                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0018 )
  95 #define PXA2X0_DCSR7                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x001c )
  96 #define PXA2X0_DCSR8                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0020 )
  97 #define PXA2X0_DCSR9                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0024 )
  98 #define PXA2X0_DCSR10                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0028 )
  99 #define PXA2X0_DCSR11                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x002c )
 100 #define PXA2X0_DCSR12                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0030 )
 101 #define PXA2X0_DCSR13                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0034 )
 102 #define PXA2X0_DCSR14                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0038 )
 103 #define PXA2X0_DCSR15                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x003c )
 104 #define PXA2X0_DINT                                     PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x00f0 )
 105 #define PXA2X0_DRCMR0                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0100 )
 106 #define PXA2X0_DRCMR1                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0104 )
 107 #define PXA2X0_DRCMR2                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0108 )
 108 #define PXA2X0_DRCMR3                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x010c )
 109 #define PXA2X0_DRCMR4                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0110 )
 110 #define PXA2X0_DRCMR5                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0114 )
 111 #define PXA2X0_DRCMR6                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0118 )
 112 #define PXA2X0_DRCMR7                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x011c )
 113 #define PXA2X0_DRCMR8                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0120 )
 114 #define PXA2X0_DRCMR9                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0124 )
 115 #define PXA2X0_DRCMR10                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0128 )
 116 #define PXA2X0_DRCMR11                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x012c )
 117 #define PXA2X0_DRCMR12                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0130 )
 118 #define PXA2X0_DRCMR13                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0134 )
 119 #define PXA2X0_DRCMR14                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0138 )
 120 #define PXA2X0_DRCMR15                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x013c )
 121 #define PXA2X0_DRCMR16                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0140 )
 122 #define PXA2X0_DRCMR17                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0144 )
 123 #define PXA2X0_DRCMR18                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0148 )
 124 #define PXA2X0_DRCMR19                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x014c )
 125 #define PXA2X0_DRCMR20                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0150 )
 126 #define PXA2X0_DRCMR21                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0154 )
 127 #define PXA2X0_DRCMR22                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0158 )
 128 #define PXA2X0_DRCMR23                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x015c )
 129 #define PXA2X0_DRCMR24                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0160 )
 130 #define PXA2X0_DRCMR25                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0164 )
 131 #define PXA2X0_DRCMR26                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0168 )
 132 #define PXA2X0_DRCMR27                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x016c )
 133 #define PXA2X0_DRCMR28                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0170 )
 134 #define PXA2X0_DRCMR29                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0174 )
 135 #define PXA2X0_DRCMR30                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0178 )
 136 #define PXA2X0_DRCMR31                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x017c )
 137 #define PXA2X0_DRCMR32                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0180 )
 138 #define PXA2X0_DRCMR33                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0184 )
 139 #define PXA2X0_DRCMR34                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0188 )
 140 #define PXA2X0_DRCMR35                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x018c )
 141 #define PXA2X0_DRCMR36                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0190 )
 142 #define PXA2X0_DRCMR37                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0194 )
 143 #define PXA2X0_DRCMR38                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0198 )
 144 #define PXA2X0_DRCMR39                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x019c )
 145 #define PXA2X0_DDADR0                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0200 )
 146 #define PXA2X0_DSADR0                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0204 )
 147 #define PXA2X0_DTADR0                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0208 )
 148 #define PXA2X0_DCMD0                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x020c )
 149 #define PXA2X0_DDADR1                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0210 )
 150 #define PXA2X0_DSADR1                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0214 )
 151 #define PXA2X0_DTADR1                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0218 )
 152 #define PXA2X0_DCMD1                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x021c )
 153 #define PXA2X0_DDADR2                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0220 )
 154 #define PXA2X0_DSADR2                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0224 )
 155 #define PXA2X0_DTADR2                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0228 )
 156 #define PXA2X0_DCMD2                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x022c )
 157 #define PXA2X0_DDADR3                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0230 )
 158 #define PXA2X0_DSADR3                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0234 )
 159 #define PXA2X0_DTADR3                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0238 )
 160 #define PXA2X0_DCMD3                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x023c )
 161 #define PXA2X0_DDADR4                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0240 )
 162 #define PXA2X0_DSADR4                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0244 )
 163 #define PXA2X0_DTADR4                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0248 )
 164 #define PXA2X0_DCMD4                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x024c )
 165 #define PXA2X0_DDADR5                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0250 )
 166 #define PXA2X0_DSADR5                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0254 )
 167 #define PXA2X0_DTADR5                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0258 )
 168 #define PXA2X0_DCMD5                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x025c )
 169 #define PXA2X0_DDADR6                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0260 )
 170 #define PXA2X0_DSADR6                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0264 )
 171 #define PXA2X0_DTADR6                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0268 )
 172 #define PXA2X0_DCMD6                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x026c )
 173 #define PXA2X0_DDADR7                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0270 )
 174 #define PXA2X0_DSADR7                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0274 )
 175 #define PXA2X0_DTADR7                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0278 )
 176 #define PXA2X0_DCMD7                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x027c )
 177 #define PXA2X0_DDADR8                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0280 )
 178 #define PXA2X0_DSADR8                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0284 )
 179 #define PXA2X0_DTADR8                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0288 )
 180 #define PXA2X0_DCMD8                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x028c )
 181 #define PXA2X0_DDADR9                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0290 )
 182 #define PXA2X0_DSADR9                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0294 )
 183 #define PXA2X0_DTADR9                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0298 )
 184 #define PXA2X0_DCMD9                            PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x029c )
 185 #define PXA2X0_DDADR10                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a0 )
 186 #define PXA2X0_DSADR10                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a4 )
 187 #define PXA2X0_DTADR10                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a8 )
 188 #define PXA2X0_DCMD10                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ac )
 189 #define PXA2X0_DDADR11                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b0 )
 190 #define PXA2X0_DSADR11                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b4 )
 191 #define PXA2X0_DTADR11                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b8 )
 192 #define PXA2X0_DCMD11                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02bc )
 193 #define PXA2X0_DDADR12                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c0 )
 194 #define PXA2X0_DSADR12                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c4 )
 195 #define PXA2X0_DTADR12                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c8 )
 196 #define PXA2X0_DCMD12                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02cc )
 197 #define PXA2X0_DDADR13                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d0 )
 198 #define PXA2X0_DSADR13                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d4 )
 199 #define PXA2X0_DTADR13                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d8 )
 200 #define PXA2X0_DCMD13                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02dc )
 201 #define PXA2X0_DDADR14                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e0 )
 202 #define PXA2X0_DSADR14                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e4 )
 203 #define PXA2X0_DTADR14                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e8 )
 204 #define PXA2X0_DCMD14                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ec )
 205 #define PXA2X0_DDADR15                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f0 )
 206 #define PXA2X0_DSADR15                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f4 )
 207 #define PXA2X0_DTADR15                          PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f8 )
 208 #define PXA2X0_DCMD15                           PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02fc )
 209
 210 // Full Function UART
 211 #define PXA2X0_FFUART_BASE                      ( PXA2X0_PERIPHERALS_BASE + 0x0100000 )
 212 #define PXA2X0_FFRBR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
 213 #define PXA2X0_FFTHR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
 214 #define PXA2X0_FFIER                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 )
 215 #define PXA2X0_FFIIR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
 216 #define PXA2X0_FFFCR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
 217 #define PXA2X0_FFLCR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x000c )
 218 #define PXA2X0_FFMCR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0010 )
 219 #define PXA2X0_FFLSR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0014 )
 220 #define PXA2X0_FFMSR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0018 )
 221 #define PXA2X0_FFSPR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x001c )
 222 #define PXA2X0_FFISR                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0020 )
 223 #define PXA2X0_FFDLL                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
 224 #define PXA2X0_FFDLH                            PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 )
 225
 226 // Bluetooth UART
 227 #define PXA2X0_BTUART_BASE                      ( PXA2X0_PERIPHERALS_BASE + 0x0200000 )
 228 #define PXA2X0_BTRBR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
 229 #define PXA2X0_BTTHR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
 230 #define PXA2X0_BTIER                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 )
 231 #define PXA2X0_BTIIR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 )
 232 #define PXA2X0_BTFCR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0008 )
 233 #define PXA2X0_BTLCR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x000c )
 234 #define PXA2X0_BTMCR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0010 )
 235 #define PXA2X0_BTLSR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0014 )
 236 #define PXA2X0_BTMSR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0018 )
 237 #define PXA2X0_BTSPR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x001c )
 238 #define PXA2X0_BTISR                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0020 )
 239 #define PXA2X0_BTDLL                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0000 )
 240 #define PXA2X0_BTDLH                            PXA2X0_REGISTER( PXA2X0_BTUART_BASE+0x0004 )
 241
 242 // I2C
 243 #define PXA2X0_I2C_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x0300000 )
 244 #define PXA2X0_IBMR                                     PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1680 )
 245 #define PXA2X0_IDBR                                     PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1688 )
 246 #define PXA2X0_ICR                                      PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1690 )
 247 #define PXA2X0_ISR                                      PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x1698 )
 248 #define PXA2X0_ISAR                                     PXA2X0_REGISTER( PXA2X0_I2C_BASE+0x16a0 )
 249
 250
 251 // I2S
 252 #define PXA2X0_I2S_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x0400000 )
 253 #define PXA2X0_SACR0                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0000 )
 254 #define PXA2X0_SACR1                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0004 )
 255 #define PXA2X0_SASR0                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x000c )
 256 #define PXA2X0_SAIMR                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0014 )
 257 #define PXA2X0_SAICR                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0018 )
 258 #define PXA2X0_SADIV                            PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0060 )
 259 #define PXA2X0_SADR                                     PXA2X0_REGISTER( PXA2X0_I2S_BASE+0x0080 )
 260
 261 // AC97
 262 #define PXA2X0_AC97_BASE                        ( PXA2X0_PERIPHERALS_BASE + 0x0500000 )
 263 #define PXA2X0_POCR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0000 )
 264 #define PXA2X0_PICR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0004 )
 265 #define PXA2X0_MCCR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0008 )
 266 #define PXA2X0_GCR                                      PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x000c )
 267 #define PXA2X0_POSR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0010 )
 268 #define PXA2X0_PISR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0014 )
 269 #define PXA2X0_MCSR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0018 )
 270 #define PXA2X0_GSR                                      PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x001c )
 271 #define PXA2X0_CAR                                      PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0020 )
 272 #define PXA2X0_PCDR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0040 )
 273 #define PXA2X0_MCDR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0060 )
 274 #define PXA2X0_MOCR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0100 )
 275 #define PXA2X0_MICR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0108 )
 276 #define PXA2X0_MOSR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0110 )
 277 #define PXA2X0_MISR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0118 )
 278 #define PXA2X0_MODR                                     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0140 )
 279 #define PXA2X0_AC97_PRIM_AUDIO_BASE     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0200 )
 280 #define PXA2X0_AC97_SEC_AUDIO_BASE      PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0300 )
 281 #define PXA2X0_AC97_PRIM_MODEM_BASE     PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0400 )
 282 #define PXA2X0_AC97_SEC_MODEM_BASE      PXA2X0_REGISTER( PXA2X0_AC97_BASE+0x0500 )
 283
 284 // UDC
 285 #define PXA2X0_UDC_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x0600000 )
 286 #define PXA2X0_UDCCR                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0000 )
 287 #define PXA2X0_UDCCS0                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0010 )
 288 #define PXA2X0_UDCCS1                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0014 )
 289 #define PXA2X0_UDCCS2                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0018 )
 290 #define PXA2X0_UDCCS3                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x001c )
 291 #define PXA2X0_UDCCS4                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0020 )
 292 #define PXA2X0_UDCCS5                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0024 )
 293 #define PXA2X0_UDCCS6                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0028 )
 294 #define PXA2X0_UDCCS7                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x002c )
 295 #define PXA2X0_UDCCS8                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0030 )
 296 #define PXA2X0_UDCCS9                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0034 )
 297 #define PXA2X0_UDCCS10                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0038 )
 298 #define PXA2X0_UDCCS11                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x003c )
 299 #define PXA2X0_UDCCS12                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0040 )
 300 #define PXA2X0_UDCCS13                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0044 )
 301 #define PXA2X0_UDCCS14                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0048 )
 302 #define PXA2X0_UDCCS15                          PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x004c )
 303 #define PXA2X0_UFNRH                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0060 )
 304 #define PXA2X0_UFNRL                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0064 )
 305 #define PXA2X0_UBCR2                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0068 )
 306 #define PXA2X0_UBCR4                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x006c )
 307 #define PXA2X0_UBCR7                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0070 )
 308 #define PXA2X0_UBCR9                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0074 )
 309 #define PXA2X0_UBCR12                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0078 )
 310 #define PXA2X0_UBCR14                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x007c )
 311 #define PXA2X0_UDDR0                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0080 )
 312 #define PXA2X0_UDDR1                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0100 )
 313 #define PXA2X0_UDDR2                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0180 )
 314 #define PXA2X0_UDDR3                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0200 )
 315 #define PXA2X0_UDDR4                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0400 )
 316 #define PXA2X0_UDDR5                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00a0 )
 317 #define PXA2X0_UDDR6                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0600 )
 318 #define PXA2X0_UDDR7                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0680 )
 319 #define PXA2X0_UDDR8                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0700 )
 320 #define PXA2X0_UDDR9                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0900 )
 321 #define PXA2X0_UDDR10                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00c0 )
 322 #define PXA2X0_UDDR11                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b00 )
 323 #define PXA2X0_UDDR12                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0b80 )
 324 #define PXA2X0_UDDR13                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0c00 )
 325 #define PXA2X0_UDDR14                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0e00 )
 326 #define PXA2X0_UDDR15                           PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x00e0 )
 327 #define PXA2X0_UICR0                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0050 )
 328 #define PXA2X0_UICR1                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0054 )
 329 #define PXA2X0_USIR0                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x0058 )
 330 #define PXA2X0_USIR1                            PXA2X0_REGISTER( PXA2X0_UDC_BASE+0x005c )
 331
 332 // Standard UART
 333 #define PXA2X0_STUART_BASE                      ( PXA2X0_PERIPHERALS_BASE + 0x0700000 )
 334 #define PXA2X0_STRBR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
 335 #define PXA2X0_STTHR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
 336 #define PXA2X0_STIER                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 )
 337 #define PXA2X0_STIIR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 )
 338 #define PXA2X0_STFCR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0008 )
 339 #define PXA2X0_STLCR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x000c )
 340 #define PXA2X0_STMCR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0010 )
 341 #define PXA2X0_STLSR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0014 )
 342 #define PXA2X0_STMSR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0018 )
 343 #define PXA2X0_STSPR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x001c )
 344 #define PXA2X0_STISR                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0020 )
 345 #define PXA2X0_STDLL                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0000 )
 346 #define PXA2X0_STDLH                            PXA2X0_REGISTER( PXA2X0_STUART_BASE+0x0004 )
 347
 348 // ICP
 349 #define PXA2X0_ICP_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x0800000 )
 350 #define PXA2X0_ICCR0                            PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0000 )
 351 #define PXA2X0_ICCR1                            PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0004 )
 352 #define PXA2X0_ICCR2                            PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0008 )
 353 #define PXA2X0_ICDR                                     PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x000c )
 354 #define PXA2X0_ICSR0                            PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0014 )
 355 #define PXA2X0_ICSR1                            PXA2X0_REGISTER( PXA2X0_ICP_BASE+0x0018 )
 356
 357 // RTC
 358 #define PXA2X0_RTC_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x0900000 )
 359 #define PXA2X0_RCNR                                     PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0000 )
 360 #define PXA2X0_RTAR                                     PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0004 )
 361 #define PXA2X0_RTSR                                     PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x0008 )
 362 #define PXA2X0_RTTR                                     PXA2X0_REGISTER( PXA2X0_RTC_BASE+0x000c )
 363
 364 // OS Timer
 365 #define PXA2X0_OSTIMER_BASE                     ( PXA2X0_PERIPHERALS_BASE + 0x0a00000 )
 366 #define PXA2X0_OSMR0                            PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0000 )
 367 #define PXA2X0_OSMR1                            PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0004 )
 368 #define PXA2X0_OSMR2                            PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0008 )
 369 #define PXA2X0_OSMR3                            PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x000c )
 370 #define PXA2X0_OSCR                                     PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0010 )
 371 #define PXA2X0_OSSR                                     PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0014 )
 372 #define PXA2X0_OWER                                     PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x0018 )
 373 #define PXA2X0_OIER                                     PXA2X0_REGISTER( PXA2X0_OSTIMER_BASE+0x001c )
 374
 375 #define PXA2X0_OSSR_TIMER0                      (0x1 << 0)
 376 #define PXA2X0_OSSR_TIMER1                      (0x1 << 1)
 377 #define PXA2X0_OSSR_TIMER2                      (0x1 << 2)
 378 #define PXA2X0_OSSR_TIMER3                      (0x1 << 3)
 379
 380 #define PXA2X0_OIER_TIMER0                      (0x1 << 0)
 381 #define PXA2X0_OIER_TIMER1                      (0x1 << 1)
 382 #define PXA2X0_OIER_TIMER2                      (0x1 << 2)
 383 #define PXA2X0_OIER_TIMER3                      (0x1 << 3)
 384
 385 #define PXA2X0_OWER_WME                         (0x1 << 0)
 386
 387 // PWM 0
 388 #define PXA2X0_PWM0_BASE                        ( PXA2X0_PERIPHERALS_BASE + 0x0b00000 )
 389 #define PXA2X0_PWM_CTRL0                        PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0000 )
 390 #define PXA2X0_PWM_PWDUTY0                      PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0004 )
 391 #define PXA2X0_PWM_PERVAL0                      PXA2X0_REGISTER( PXA2X0_PWM0_BASE+0x0008 )
 392
 393 // PWM 1
 394 #define PXA2X0_PWM1_BASE                        ( PXA2X0_PERIPHERALS_BASE + 0x0c00000 )
 395 #define PXA2X0_PWM_CTRL1                        PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0000 )
 396 #define PXA2X0_PWM_PWDUTY1                      PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0004 )
 397 #define PXA2X0_PWM_PERVAL1                      PXA2X0_REGISTER( PXA2X0_PWM1_BASE+0x0008 )
 398
 399 // Interrupt Control
 400 #define PXA2X0_IC_BASE                          ( PXA2X0_PERIPHERALS_BASE + 0x0d00000 )
 401 #define PXA2X0_ICIP                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0000 )
 402 #define PXA2X0_ICMR                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0004 )
 403 #define PXA2X0_ICLR                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0008 )
 404 #define PXA2X0_ICFP                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x000c )
 405 #define PXA2X0_ICPR                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0010 )
 406 #define PXA2X0_ICCR                                     PXA2X0_REGISTER( PXA2X0_IC_BASE+0x0014 )
 407 #define PXA2X0_ICMR2                                    PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a0 )
 408 #define PXA2X0_ICLR2                                    PXA2X0_REGISTER( PXA2X0_IC_BASE+0x00a4 )
 409
 410 // GPIO
 411 #define PXA2X0_GPIO_BASE                        ( PXA2X0_PERIPHERALS_BASE + 0x0e00000 )
 412 #define PXA2X0_GPLR0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0000 )
 413 #define PXA2X0_GPLR1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0004 )
 414 #define PXA2X0_GPLR2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0008 )
 415 #define PXA2X0_GPDR0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x000c )
 416 #define PXA2X0_GPDR1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0010 )
 417 #define PXA2X0_GPDR2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0014 )
 418 #define PXA2X0_GPSR0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0018 )
 419 #define PXA2X0_GPSR1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x001c )
 420 #define PXA2X0_GPSR2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0020 )
 421 #define PXA2X0_GPCR0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0024 )
 422 #define PXA2X0_GPCR1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0028 )
 423 #define PXA2X0_GPCR2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x002c )
 424 #define PXA2X0_GRER0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0030 )
 425 #define PXA2X0_GRER1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0034 )
 426 #define PXA2X0_GRER2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0038 )
 427 #define PXA2X0_GFER0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x003c )
 428 #define PXA2X0_GFER1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0040 )
 429 #define PXA2X0_GFER2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0044 )
 430 #define PXA2X0_GEDR0                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0048 )
 431 #define PXA2X0_GEDR1                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x004c )
 432 #define PXA2X0_GEDR2                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0050 )
 433 #define PXA2X0_GAFR0_L                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0054 )
 434 #define PXA2X0_GAFR0_U                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0058 )
 435 #define PXA2X0_GAFR1_L                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x005c )
 436 #define PXA2X0_GAFR1_U                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 )
 437 #define PXA2X0_GAFR2_L                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 )
 438 #define PXA2X0_GAFR2_U                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 )
 439 #define PXA2X0_GAFR3_L                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x006c )
 440 #define PXA2X0_GAFR3_U                          PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0070 )
 441 #define PXA2X0_GPLR3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0100 )
 442 #define PXA2X0_GPDR3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x010c )
 443 #define PXA2X0_GPSR3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0118 )
 444 #define PXA2X0_GPCR3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0124 )
 445 #define PXA2X0_GRER3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0130 )
 446 #define PXA2X0_GFER3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x013c )
 447 #define PXA2X0_GEDR3                            PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0148 )
 448
 449 #define PXA2X0_GPIO_NORM 0x00
 450 #define PXA2X0_GPIO_AF1  0x01
 451 #define PXA2X0_GPIO_AF2  0x02
 452 #define PXA2X0_GPIO_AF3  0x03
 453 #define PXA2X0_GPIO_IN      0
 454 #define PXA2X0_GPIO_OUT     1
 455
 456
 457 // Power Manager and Reset Control
 458 #define PXA2X0_PM_BASE                          ( PXA2X0_PERIPHERALS_BASE + 0x0f00000 )
 459 #define PXA2X0_PMCR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0000 )
 460 #define PXA2X0_PSSR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0004 )
 461 #define PXA2X0_PSPR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0008 )
 462 #define PXA2X0_PWER                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x000c )
 463 #define PXA2X0_PRER                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0010 )
 464 #define PXA2X0_PFER                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0014 )
 465 #define PXA2X0_PEDR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0018 )
 466 #define PXA2X0_PCFR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x001c )
 467 #define PXA2X0_PGSR0                            PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0020 )
 468 #define PXA2X0_PGSR1                            PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0024 )
 469 #define PXA2X0_PGSR2                            PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0028 )
 470 #define PXA2X0_RCSR                                     PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0030 )
 471
 472 // SSP
 473 #define PXA2X0_SSP_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x1000000 )
 474 #define PXA2X0_SSCR0                            PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0000 )
 475 #define PXA2X0_SSCR1                            PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0004 )
 476 #define PXA2X0_SSSR                                     PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0008 )
 477 #define PXA2X0_SSITR                            PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x000c )
 478 #define PXA2X0_SSDR                                     PXA2X0_REGISTER( PXA2X0_SSP_BASE+0x0010 )
 479
 480 // MMC Controller
 481 #define PXA2X0_MMC_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x1100000 )
 482 #define PXA2X0_MMC_STRPCL                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0000 )
 483 #define PXA2X0_MMC_STAT                         PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0004 )
 484 #define PXA2X0_MMC_CLKRT                        PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0008 )
 485 #define PXA2X0_MMC_SPI                          PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x000c )
 486 #define PXA2X0_MMC_CMDAT                        PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0010 )
 487 #define PXA2X0_MMC_RESTO                        PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0014 )
 488 #define PXA2X0_MMC_RDTO                         PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0018 )
 489 #define PXA2X0_MMC_BLKLEN                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x001c )
 490 #define PXA2X0_MMC_NOB                          PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0020 )
 491 #define PXA2X0_MMC_PRTBUF                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0024 )
 492 #define PXA2X0_MMC_I_MASK                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0028 )
 493 #define PXA2X0_MMC_I_REG                        PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x002c )
 494 #define PXA2X0_MMC_CMD                          PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0030 )
 495 #define PXA2X0_MMC_ARGH                         PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0034 )
 496 #define PXA2X0_MMC_ARGL                         PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0038 )
 497 #define PXA2X0_MMC_RES                          PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x003c )
 498 #define PXA2X0_MMC_RXFIFO                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0040 )
 499 #define PXA2X0_MMC_TXFIFO                       PXA2X0_REGISTER( PXA2X0_MMC_BASE+0x0044 )
 500
 501 // Clocks Manager
 502 #define PXA2X0_CLK_BASE                         ( PXA2X0_PERIPHERALS_BASE + 0x1300000 )
 503 #define PXA2X0_CCCR                                     PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0000 )
 504 #define PXA2X0_CKEN                                     PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0004 )
 505 #define PXA2X0_OSCC                                     PXA2X0_REGISTER( PXA2X0_CLK_BASE+0x0008 )
 506
 507 // PXA25x CCCR bits
 508 #ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X
 509 // Crystal Frequency to Memory Frequency multiplier
 510 #  define PXA2X0_CCCR_L09       (0x1f)
 511 #  define PXA2X0_CCCR_L27       (0x01)
 512 #  define PXA2X0_CCCR_L32       (0x02)
 513 #  define PXA2X0_CCCR_L36       (0x03)
 514 #  define PXA2X0_CCCR_L40       (0x04)
 515 #  define PXA2X0_CCCR_L45       (0x05)
 516 // Memory frequency to to run mode frequency multiplier
 517 #  define PXA2X0_CCCR_M1        (0x1 << 5)
 518 #  define PXA2X0_CCCR_M2        (0x2 << 5)
 519 #  define PXA2X0_CCCR_M4        (0x3 << 5)
 520 // Run mode frequency to turbo mode frequency multiplier
 521 #  define PXA2X0_CCCR_N10       (0x2 << 7)      // N=1.0
 522 #  define PXA2X0_CCCR_N15       (0x3 << 7)      // N=1.5
 523 #  define PXA2X0_CCCR_N20       (0x4 << 7)      // N=2.0
 524 #  define PXA2X0_CCCR_N25       (0x5 << 7)      // N=2.5
 525 #  define PXA2X0_CCCR_N30       (0x6 << 7)      // N=3.0
 526 #endif
 527
 528 // PXA27x CCCR bits
 529 #ifdef CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X
 530 // Run-mode-to-oscillator ratio
 531 #  define PXA27X_CCCR_L8           (0x08)
 532 #  define PXA27X_CCCR_L16          (0x10)
 533 // Turbo-mode-to-run-mode ratio
 534 #  define PXA27X_CCCR_N1           (0x02 << 7)
 535 #  define PXA27X_CCCR_N1_5         (0x03 << 7)
 536 #  define PXA27X_CCCR_N2           (0x04 << 7)
 537 #  define PXA27X_CCCR_N2_5         (0x05 << 7)
 538 #  define PXA27X_CCCR_N3           (0x06 << 7)
 539
 540 #  define PXA27X_CCCR_A            (0x02000000)
 541 #  define PXA27X_CCCR_PLL_EARLY_EN (0x04000000)
 542 #  define PXA27X_CCCR_LCD_26       (0x08000000)
 543 #  define PXA27X_CCCR_PPDIS        (0x40000000)
 544 #  define PXA27X_CCCR_CPDIS        (0x80000000)
 545 #endif
 546
 547 // LCD Controller
 548 #define PXA2X0_LCCR0                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0000 )
 549 #define PXA2X0_LCCR1                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0004 )
 550 #define PXA2X0_LCCR2                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0008 )
 551 #define PXA2X0_LCCR3                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x000c )
 552 #define PXA2X0_FDADR0                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0200 )
 553 #define PXA2X0_FSADR0                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0204 )
 554 #define PXA2X0_FIDR0                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0208 )
 555 #define PXA2X0_LDCMD0                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x020c )
 556 #define PXA2X0_FDADR1                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0210 )
 557 #define PXA2X0_FSADR1                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0214 )
 558 #define PXA2X0_FIDR1                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0218 )
 559 #define PXA2X0_LDCMD1                           PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x021c )
 560 #define PXA2X0_FBR0                                     PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0020 )
 561 #define PXA2X0_FBR1                                     PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0024 )
 562 #define PXA2X0_LCSR                                     PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0038 )
 563 #define PXA2X0_LIIDR                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x003c )
 564 #define PXA2X0_TRGBR                            PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0040 )
 565 #define PXA2X0_TCR                                      PXA2X0_REGISTER( PXA2X0_LCD_BASE+0x0044 )
 566
 567 // Memory Controller
 568 #define PXA2X0_MDCNFG                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0000 )
 569 #define PXA2X0_MDREFR                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0004 )
 570 #define PXA2X0_MSC0                                     PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0008 )
 571 #define PXA2X0_MSC1                                     PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x000c )
 572 #define PXA2X0_MSC2                                     PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0010 )
 573 #define PXA2X0_MECR                                     PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0014 )
 574 #define PXA2X0_SXCNFG                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x001c )
 575 #define PXA2X0_SXMRS                            PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0024 )
 576 #define PXA2X0_MCMEM0                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0028 )
 577 #define PXA2X0_MCMEM1                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x002c )
 578 #define PXA2X0_MCATT0                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0030 )
 579 #define PXA2X0_MCATT1                           PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0034 )
 580 #define PXA2X0_MCIO0                            PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0038 )
 581 #define PXA2X0_MCIO1                            PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x003c )
 582 #define PXA2X0_MDMRS                            PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0040 )
 583 #define PXA2X0_BOOT_DEF                         PXA2X0_REGISTER( PXA2X0_MEMORY_CTL_BASE+0x0044 )
 584
 585 // UART definitions
 586 //      Register offsets
 587 #define PXA2X0_UART_RBR                         ( 0x0000 )      // Receive Buffer Register
 588 #define PXA2X0_UART_THR                         ( 0x0000 )      // Transmit Hold Register
 589 #define PXA2X0_UART_IER                         ( 0x0004 )      // Interrupt Enable Register
 590 #define PXA2X0_UART_IIR                         ( 0x0008 )      // Interrupt ID Register
 591 #define PXA2X0_UART_FCR                         ( 0x0008 )
 592 #define PXA2X0_UART_LCR                         ( 0x000c )
 593 #define PXA2X0_UART_MCR                         ( 0x0010 )
 594 #define PXA2X0_UART_LSR                         ( 0x0014 )
 595 #define PXA2X0_UART_MSR                         ( 0x0018 )
 596 #define PXA2X0_UART_SPR                         ( 0x001c )
 597 #define PXA2X0_UART_ISR                         ( 0x0020 )
 598 #define PXA2X0_UART_DLL                         ( 0x0000 )
 599 #define PXA2X0_UART_DLH                         ( 0x0004 )
 600
 601
 602 // The interrupt enable register bits.
 603 #define PXA2X0_UART_IER_RAVIE   0x01            // enable received data available irq
 604 #define PXA2X0_UART_IER_TIE             0x02            // enable transmit data request interrupt
 605 #define PXA2X0_UART_IER_RLSE    0x04            // enable receiver line status irq
 606 #define PXA2X0_UART_IER_MIE             0x08            // enable modem status interrupt
 607 #define PXA2X0_UART_IER_RTOIE   0x10            // enable Rx timeout interrupt
 608 #define PXA2X0_UART_IER_NRZE    0x20            // enable NRZ coding
 609 #define PXA2X0_UART_IER_UUE             0x40            // enable the UART unit
 610 #define PXA2X0_UART_IER_DMAE    0x80            // enable DMA requests
 611
 612 // The interrupt identification register bits.
 613 #define PXA2X0_UART_IIR_IP              0x01            // 0 if interrupt pending
 614 #define PXA2X0_UART_Tx                  0x02
 615 #define PXA2X0_UART_Rx                  0x04
 616 #define PXA2X0_UART_IIR_ID_MASK 0xff            // mask for interrupt ID bits
 617
 618 // The line status register bits.
 619 #define PXA2X0_UART_LSR_DR      0x01                    // data ready
 620 #define PXA2X0_UART_LSR_OE      0x02                    // overrun error
 621 #define PXA2X0_UART_LSR_PE      0x04                    // parity error
 622 #define PXA2X0_UART_LSR_FE      0x08                    // framing error
 623 #define PXA2X0_UART_LSR_BI      0x10                    // break interrupt
 624 #define PXA2X0_UART_LSR_THRE    0x20                    // transmitter holding register empty
 625 #define PXA2X0_UART_LSR_TEMT    0x40                    // transmitter holding and Tx shift registers empty
 626 #define PXA2X0_UART_LSR_ERR     0x80                    // any error condition (FIFOE)
 627
 628 // The modem status register bits.
 629 #define PXA2X0_UART_MSR_DCTS    0x01                    // delta clear to send
 630 #define PXA2X0_UART_MSR_DDSR    0x02                    // delta data set ready
 631 #define PXA2X0_UART_MSR_TERI    0x04                    // trailing edge ring indicator
 632 #define PXA2X0_UART_MSR_DDCD    0x08                    // delta data carrier detect
 633 #define PXA2X0_UART_MSR_CTS             0x10                    // clear to send
 634 #define PXA2X0_UART_MSR_DSR             0x20                    // data set ready
 635 #define PXA2X0_UART_MSR_RI              0x40                    // ring indicator
 636 #define PXA2X0_UART_MSR_DCD             0x80                    // data carrier detect
 637
 638 // The line control register bits.
 639 #define PXA2X0_UART_LCR_WLS0    0x01                    // word length select bit 0
 640 #define PXA2X0_UART_LCR_WLS1    0x02                    // word length select bit 1
 641 #define PXA2X0_UART_LCR_STB             0x04                    // number of stop bits
 642 #define PXA2X0_UART_LCR_PEN             0x08                    // parity enable
 643 #define PXA2X0_UART_LCR_EPS             0x10                    // even parity select
 644 #define PXA2X0_UART_LCR_SP              0x20                    // stick parity
 645 #define PXA2X0_UART_LCR_SB              0x40                    // set break
 646 #define PXA2X0_UART_LCR_DLAB    0x80                    // divisor latch access bit
 647
 648 // The FIFO control register
 649 #define PXA2X0_UART_FCR_FCR0    0x01                    // enable xmit and rcvr fifos
 650 #define PXA2X0_UART_FCR_FCR1    0x02                    // clear RCVR FIFO
 651 #define PXA2X0_UART_FCR_FCR2    0x04                    // clear XMIT FIFO
 652 #define PXA2X0_UART_FCR_ITL0    0x40                    // Interrupt trigger level (ITL) bit 0
 653 #define PXA2X0_UART_FCR_ITL1    0x80                    // Interrupt trigger level (ITL) bit 1
 654 #define PXA2X0_UART_FCR_ITL_1BYTE   0x00                // i byte triggers interrupt
 655
 656 #define PXA2X0_UART_BAUD_RATE_DIVISOR(x)         ((14745600/(16*(x))))
 657
 658 #endif // CYGONCE_HAL_ARM_PXA2X0_H
 659 // EOF hal_pxa2x0.h
 660