1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //#####ECOSGPLCOPYRIGHTBEGIN####
10 //## -------------------------------------------
11 //## This file is part of eCos, the Embedded Configurable Operating System.
12 //## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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25 //## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //## or inline functions from this file, or you compile this file and link it
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35 //## this file might be covered by the GNU General Public License.
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39 //## -------------------------------------------
40 //#####ECOSGPLCOPYRIGHTEND####
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: Define Interrupt support
47 // Description: The interrupt details for the INPHINITY are defined here.
49 // #include <cyg/hal/hal_platform_ints.h>
53 //####DESCRIPTIONEND####
55 //==========================================================================
61 #define CYGNUM_HAL_INTERRUPT_GPIO0 8
62 #define CYGNUM_HAL_INTERRUPT_GPIO1 9
63 #define CYGNUM_HAL_INTERRUPT_GPIO 10
64 #define CYGNUM_HAL_INTERRUPT_USB 11
65 #define CYGNUM_HAL_INTERRUPT_PMU 12
66 #define CYGNUM_HAL_INTERRUPT_I2S 13
67 #define CYGNUM_HAL_INTERRUPT_AC97 14
69 #define CYGNUM_HAL_INTERRUPT_LCD 17
70 #define CYGNUM_HAL_INTERRUPT_I2C 18
71 #define CYGNUM_HAL_INTERRUPT_ICP 19
72 #define CYGNUM_HAL_INTERRUPT_STUART 20
73 #define CYGNUM_HAL_INTERRUPT_BTUART 21
74 #define CYGNUM_HAL_INTERRUPT_FFUART 22
75 #define CYGNUM_HAL_INTERRUPT_MMC 23
76 #define CYGNUM_HAL_INTERRUPT_SSP 24
77 #define CYGNUM_HAL_INTERRUPT_DMA 25
78 #define CYGNUM_HAL_INTERRUPT_TIMER0 26
79 #define CYGNUM_HAL_INTERRUPT_TIMER1 27
80 #define CYGNUM_HAL_INTERRUPT_TIMER2 28
81 #define CYGNUM_HAL_INTERRUPT_TIMER3 29
82 #define CYGNUM_HAL_INTERRUPT_HZ 30
83 #define CYGNUM_HAL_INTERRUPT_ALARM 31
88 #define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2)
89 #define CYGNUM_HAL_INTERRUPT_GPIO3 (32+3)
90 #define CYGNUM_HAL_INTERRUPT_GPIO4 (32+4)
91 #define CYGNUM_HAL_INTERRUPT_GPIO5 (32+5)
92 #define CYGNUM_HAL_INTERRUPT_GPIO6 (32+6)
93 #define CYGNUM_HAL_INTERRUPT_GPIO7 (32+7)
94 #define CYGNUM_HAL_INTERRUPT_GPIO8 (32+8)
95 #define CYGNUM_HAL_INTERRUPT_GPIO9 (32+9)
96 #define CYGNUM_HAL_INTERRUPT_GPIO10 (32+10)
97 #define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
98 #define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
99 #define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
100 #define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
101 #define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
102 #define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
103 #define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
104 #define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
105 #define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
106 #define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
107 #define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
108 #define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
109 #define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
110 #define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
111 #define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
112 #define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
113 #define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
114 #define CYGNUM_HAL_INTERRUPT_GPIO28 (32+28)
115 #define CYGNUM_HAL_INTERRUPT_GPIO29 (32+29)
116 #define CYGNUM_HAL_INTERRUPT_GPIO30 (32+30)
117 #define CYGNUM_HAL_INTERRUPT_GPIO31 (32+31)
119 #define CYGNUM_HAL_INTERRUPT_GPIO32 (64+0)
120 #define CYGNUM_HAL_INTERRUPT_GPIO33 (64+1)
121 #define CYGNUM_HAL_INTERRUPT_GPIO34 (64+2)
122 #define CYGNUM_HAL_INTERRUPT_GPIO35 (64+3)
123 #define CYGNUM_HAL_INTERRUPT_GPIO36 (64+4)
124 #define CYGNUM_HAL_INTERRUPT_GPIO37 (64+5)
125 #define CYGNUM_HAL_INTERRUPT_GPIO38 (64+6)
126 #define CYGNUM_HAL_INTERRUPT_GPIO39 (64+7)
127 #define CYGNUM_HAL_INTERRUPT_GPIO40 (64+8)
128 #define CYGNUM_HAL_INTERRUPT_GPIO41 (64+9)
129 #define CYGNUM_HAL_INTERRUPT_GPIO42 (64+10)
130 #define CYGNUM_HAL_INTERRUPT_GPIO43 (64+11)
131 #define CYGNUM_HAL_INTERRUPT_GPIO44 (64+12)
132 #define CYGNUM_HAL_INTERRUPT_GPIO45 (64+13)
133 #define CYGNUM_HAL_INTERRUPT_GPIO46 (64+14)
134 #define CYGNUM_HAL_INTERRUPT_GPIO47 (64+15)
135 #define CYGNUM_HAL_INTERRUPT_GPIO48 (64+16)
136 #define CYGNUM_HAL_INTERRUPT_GPIO49 (64+17)
137 #define CYGNUM_HAL_INTERRUPT_GPIO50 (64+18)
138 #define CYGNUM_HAL_INTERRUPT_GPIO51 (64+19)
139 #define CYGNUM_HAL_INTERRUPT_GPIO52 (64+20)
140 #define CYGNUM_HAL_INTERRUPT_GPIO53 (64+21)
141 #define CYGNUM_HAL_INTERRUPT_GPIO54 (64+22)
142 #define CYGNUM_HAL_INTERRUPT_GPIO55 (64+23)
143 #define CYGNUM_HAL_INTERRUPT_GPIO56 (64+24)
144 #define CYGNUM_HAL_INTERRUPT_GPIO57 (64+25)
145 #define CYGNUM_HAL_INTERRUPT_GPIO58 (64+26)
146 #define CYGNUM_HAL_INTERRUPT_GPIO59 (64+27)
147 #define CYGNUM_HAL_INTERRUPT_GPIO60 (64+28)
148 #define CYGNUM_HAL_INTERRUPT_GPIO61 (64+29)
149 #define CYGNUM_HAL_INTERRUPT_GPIO62 (64+30)
150 #define CYGNUM_HAL_INTERRUPT_GPIO63 (64+31)
152 #define CYGNUM_HAL_INTERRUPT_GPIO64 (96+0)
153 #define CYGNUM_HAL_INTERRUPT_GPIO65 (96+1)
154 #define CYGNUM_HAL_INTERRUPT_GPIO66 (96+2)
155 #define CYGNUM_HAL_INTERRUPT_GPIO67 (96+3)
156 #define CYGNUM_HAL_INTERRUPT_GPIO68 (96+4)
157 #define CYGNUM_HAL_INTERRUPT_GPIO69 (96+5)
158 #define CYGNUM_HAL_INTERRUPT_GPIO70 (96+6)
159 #define CYGNUM_HAL_INTERRUPT_GPIO71 (96+7)
160 #define CYGNUM_HAL_INTERRUPT_GPIO72 (96+8)
161 #define CYGNUM_HAL_INTERRUPT_GPIO73 (96+9)
162 #define CYGNUM_HAL_INTERRUPT_GPIO74 (96+10)
163 #define CYGNUM_HAL_INTERRUPT_GPIO75 (96+11)
164 #define CYGNUM_HAL_INTERRUPT_GPIO76 (96+12)
165 #define CYGNUM_HAL_INTERRUPT_GPIO77 (96+13)
166 #define CYGNUM_HAL_INTERRUPT_GPIO78 (96+14)
167 #define CYGNUM_HAL_INTERRUPT_GPIO79 (96+15)
168 #define CYGNUM_HAL_INTERRUPT_GPIO80 (96+16)
169 #define CYGNUM_HAL_INTERRUPT_GPIO81 (96+17)
170 #define CYGNUM_HAL_INTERRUPT_GPIO82 (96+18)
171 #define CYGNUM_HAL_INTERRUPT_GPIO83 (96+19)
172 #define CYGNUM_HAL_INTERRUPT_GPIO84 (96+20)
174 externC void cyg_hal_xscale_soft_reset(CYG_ADDRESS);
176 #define HAL_PLATFORM_RESET() cyg_hal_xscale_soft_reset(HAL_PLATFORM_RESET_ENTRY)
177 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
179 // *** remainder are reserved ****
180 #define CYGNUM_HAL_INT_
182 #define CYGNUM_HAL_ISR_MIN 0
183 #define CYGNUM_HAL_ISR_MAX 48
185 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
187 // The vector used by the Real time clock
188 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
189 //#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL
191 extern void hal_delay_us(cyg_uint32 usecs);
193 #define HAL_DELAY_US(n) hal_delay_us(n);
195 #endif // CYGONCE_HAL_PLATFORM_INTS_H