17 #include <cyg/hal/hal_triton270.h> // Platform specific hardware definitions
32 .equ GPIO_DIR_INPUT, 0
33 .equ GPIO_DIR_OUTPUT, 1
46 /*GPIO 0 */ .byte 0, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
47 /*GPIO 1 */ .byte 1, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
48 /*GPIO 2 */ .byte 2, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
49 /*GPIO 3 */ .byte 3, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
50 /*GPIO 4 */ .byte 4, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
51 /*GPIO 5 */ .byte 5, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
52 /*GPIO 6 */ .byte 6, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
53 /*GPIO 7 */ .byte 7, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
54 /*GPIO 8 */ .byte 8, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
55 /*GPIO 9 */ .byte 9, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
56 /*GPIO 10 */ .byte 10, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /* ETN Reset */
57 /*GPIO 11 */ .byte 11, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
58 /*GPIO 12 */ .byte 12, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
59 /*GPIO 13 */ .byte 13, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
60 /*GPIO 14 */ .byte 14, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0 /* Backlight enable */
61 /*GPIO 15 */ .byte 15, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF1 /* PCE1# */
62 /*GPIO 16 */ .byte 16, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
63 /*GPIO 17 */ .byte 17, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
64 /*GPIO 18 */ .byte 18, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* RDY pin */
65 /*GPIO 19 */ .byte 19, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
66 /*GPIO 20 */ .byte 20, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
67 /*GPIO 21 */ .byte 21, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /* USB pull up */
68 /*GPIO 22 */ .byte 22, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
69 /*GPIO 23 */ .byte 23, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
70 /*GPIO 24 */ .byte 24, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
71 /*GPIO 25 */ .byte 25, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
72 /*GPIO 26 */ .byte 26, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
73 /*GPIO 27 */ .byte 27, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
74 /*GPIO 28 */ .byte 28, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* AC97_BITCLK */
75 /*GPIO 29 */ .byte 29, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* AC97_SDATA_IN0 */
76 /*GPIO 30 */ .byte 30, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* AC97_SDATA_OUT */
77 /*GPIO 31 */ .byte 31, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* AC97_SYNC */
80 /*GPIO 32 */ .byte 32, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* MMCLK */
81 /*GPIO 33 */ .byte 33, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* CS5# -> CSETN# */
82 /*GPIO 34 */ .byte 34, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* FFRxD */
83 /*GPIO 35 */ .byte 35, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* FFCTS */
84 /*GPIO 36 */ .byte 36, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* FFDCD */
85 /*GPIO 37 */ .byte 37, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* FFDSR */
86 /*GPIO 38 */ .byte 38, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* FFRI */
87 /*GPIO 39 */ .byte 39, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* FFTxD */
88 /*GPIO 40 */ .byte 40, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* FFDTR */
89 /*GPIO 41 */ .byte 41, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* FFRTS */
90 /*GPIO 42 */ .byte 42, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* BTRxD */
91 /*GPIO 43 */ .byte 43, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* BTTxD */
92 /*GPIO 44 */ .byte 44, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* BTCTS */
93 /*GPIO 45 */ .byte 45, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* BTRTS */
94 /*GPIO 46 */ .byte 46, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* STDRxD */
95 /*GPIO 47 */ .byte 47, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF1 /* STDTxD */
96 /*GPIO 48 */ .byte 48, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* POE# */
97 /*GPIO 49 */ .byte 49, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* PWE# */
98 /*GPIO 50 */ .byte 50, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* PIOR# */
99 /*GPIO 51 */ .byte 51, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* PIOW# */
100 /*GPIO 52 */ .byte 52, GPIO_DIR_INPUT, GPIO_REDGE | GPIO_LOW, GPIO_AF0 /* ETNINT */
101 /*GPIO 53 */ .byte 53, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /* MMC-Card CD# */
102 /*GPIO 54 */ .byte 54, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /* MMC-Card WP# */
103 /*GPIO 55 */ .byte 55, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* PREG# */
104 /*GPIO 56 */ .byte 56, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* PWAIT */
105 /*GPIO 57 */ .byte 57, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* IOS16 */
106 /*GPIO 58 */ .byte 58, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD0 */
107 /*GPIO 59 */ .byte 59, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD1 */
108 /*GPIO 60 */ .byte 60, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD2 */
109 /*GPIO 61 */ .byte 61, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD3 */
110 /*GPIO 62 */ .byte 62, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD4 */
111 /*GPIO 63 */ .byte 63, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD5 */
114 /*GPIO 64 */ .byte 64, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD6 */
115 /*GPIO 65 */ .byte 65, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD7 */
116 /*GPIO 66 */ .byte 66, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD8 */
117 /*GPIO 67 */ .byte 67, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD9 */
118 /*GPIO 68 */ .byte 68, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD10 */
119 /*GPIO 69 */ .byte 69, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD11 */
120 /*GPIO 70 */ .byte 70, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD12 */
121 /*GPIO 71 */ .byte 71, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD13 */
122 /*GPIO 72 */ .byte 72, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD14 */
123 /*GPIO 73 */ .byte 73, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD15 */
124 /*GPIO 74 */ .byte 74, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* FCLK */
125 /*GPIO 75 */ .byte 75, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LCLK */
126 /*GPIO 76 */ .byte 76, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* PCLK */
127 /*GPIO 77 */ .byte 77, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LCD_DEN */
128 /*GPIO 78 */ .byte 78, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF1 /* PCE2# */
129 /*GPIO 79 */ .byte 79, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* PSKTSEL */
130 /*GPIO 80 */ .byte 80, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /* Display enable or CS*/
131 /*GPIO 81 */ .byte 81, GPIO_DIR_INPUT, GPIO_REDGE | GPIO_LOW, GPIO_AF0 /*CF IRQ */
132 /*GPIO 82 */ .byte 82, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0 /*CF Card Detect# */
133 /*GPIO 83 */ .byte 83, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF0 /*CF RESET */
134 /*GPIO 84 */ .byte 84, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0 /*CF BVD2# */
135 /*GPIO 85 */ .byte 85, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0 /*CF BVD1# */
136 /*GPIO 86 */ .byte 86, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD16 */
137 /*GPIO 87 */ .byte 87, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* LDD17 */
138 /*GPIO 88 */ .byte 88, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* USBHPWR1 USB Host power Status*/
139 /*GPIO 89 */ .byte 89, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_HIGH, GPIO_AF2 /* USBHPEN1 USB Host power Enable (set to off) */
140 /*GPIO 90 */ .byte 90, GPIO_DIR_INPUT, GPIO_REDGE | GPIO_LOW, GPIO_AF0 /* UCB1400 IRQ */
141 /*GPIO 91 */ .byte 91, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
142 /*GPIO 92 */ .byte 92, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* MMDAT0 */
143 /*GPIO 93 */ .byte 93, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
144 /*GPIO 94 */ .byte 94, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
145 /*GPIO 95 */ .byte 95, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
149 /*GPIO 96 */ .byte 96, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
150 /*GPIO 97 */ .byte 97, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
151 /*GPIO 98 */ .byte 98, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
152 /*GPIO 99 */ .byte 99, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
153 /*GPIO 100 */ .byte 100, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
154 /*GPIO 101 */ .byte 101, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
155 /*GPIO 102 */ .byte 102, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
156 /*GPIO 103 */ .byte 103, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
157 /*GPIO 104 */ .byte 104, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
158 /*GPIO 105 */ .byte 105, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
159 /*GPIO 106 */ .byte 106, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
160 /*GPIO 107 */ .byte 107, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
161 /*GPIO 108 */ .byte 108, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
162 /*GPIO 109 */ .byte 109, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* MMDAT1 */
163 /*GPIO 110 */ .byte 110, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* MMDAT2 */
164 /*GPIO 111 */ .byte 111, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* MMDAT3 */
165 /*GPIO 112 */ .byte 112, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF1 /* MMCMD */
166 /*GPIO 113 */ .byte 113, GPIO_DIR_OUTPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF2 /* AC97_RESET# */
167 /*GPIO 114 */ .byte 114, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
168 /*GPIO 115 */ .byte 115, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
169 /*GPIO 116 */ .byte 116, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
170 /*GPIO 117 */ .byte 117, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
171 /*GPIO 118 */ .byte 118, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
172 /*GPIO 119 */ .byte 119, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
173 /*GPIO 120 */ .byte 120, GPIO_DIR_INPUT, GPIO_NOEDGE | GPIO_LOW, GPIO_AF0
174 /*GPIO 121 */ .byte 121, 0, 0, 0
175 /*GPIO 122 */ .byte 122, 0, 0, 0
176 /*GPIO 123 */ .byte 123, 0, 0, 0
177 /*GPIO 124 */ .byte 124, 0, 0, 0
178 /*GPIO 125 */ .byte 125, 0, 0, 0
179 /*GPIO 126 */ .byte 126, 0, 0, 0
180 /*GPIO 127 */ .byte 127, 0, 0, 0
206 // must set the GPIOs up before any chip selects will work
210 //GPCRa = 0xffffffff put a 0 on any of the GPIOs (0=unchanged, 1=drive 0)
230 // *************************************************************************************
231 // extract value for Output Set Register GPSRa from table
232 // *************************************************************************************
233 ldr r0, =pin_state_table
234 mov r1, #1 // mask register
235 mov r2, #0 // this is the register where the value is composed
238 ldr r3, [r0], #4 // load table entry, increase pointer
239 ands r3, r3, #0x00010000
240 beq _exGPSRa1 // ZERO flag is set
241 orr r2, r2, r1 // OR mask bit to value
243 mov r1, r1, ASL #1 // shift mask bit
251 // *************************************************************************************
252 // extract value for Output Set Register GPSRb from table
253 // *************************************************************************************
254 ldr r0, =pin_state_table
255 add r0, r0, #128 // use second third of table
256 mov r1, #1 // mask register
257 mov r2, #0 // this is the register where the value is composed
260 ldr r3, [r0], #4 // load table entry, increase pointer
261 ands r3, r3, #0x00010000
262 beq _exGPSRb1 // ZERO flag is set
263 orr r2, r2, r1 // OR mask bit to value
265 mov r1, r1, ASL #1 // shift mask bit
274 // *************************************************************************************
275 // extract value for Output Set Register GPSRc from table
276 // *************************************************************************************
277 ldr r0, =pin_state_table
278 add r0, r0, #256 // use last third of table
279 mov r1, #1 // mask register
280 mov r2, #0 // this is the register where the value is composed
283 ldr r3, [r0], #4 // load table entry, increase pointer
284 ands r3, r3, #0x00010000
285 beq _exGPSRc1 // ZERO flag is set
286 orr r2, r2, r1 // OR mask bit to value
288 mov r1, r1, ASL #1 // shift mask bit
298 // *************************************************************************************
299 // extract value for Output Set Register GPSRd from table
300 // *************************************************************************************
301 ldr r0, =pin_state_table
302 add r0, r0, #384 // use last quarter of table
303 mov r1, #1 // mask register
304 mov r2, #0 // this is the register where the value is composed
307 ldr r3, [r0], #4 // load table entry, increase pointer
308 ands r3, r3, #0x00010000
309 beq _exGPSRd1 // ZERO flag is set
310 orr r2, r2, r1 // OR mask bit to value
312 mov r1, r1, ASL #1 // shift mask bit
327 // *************************************************************************************
328 // extract value for Direction Register GPDRa from table
329 // *************************************************************************************
330 ldr r0, =pin_state_table
331 mov r1, #1 // mask register
332 mov r2, #0 // this is the register where the value is composed
335 ldr r3, [r0], #4 // load table entry, increase pointer
336 ands r3, r3, #0x00000100
337 beq _exGPDRa1 // ZERO flag is set
338 orr r2, r2, r1 // OR mask bit to value
340 mov r1, r1, ASL #1 // shift mask bit
346 bic r2, r2, r5 // reserved bits
358 // *************************************************************************************
359 // extract value for Direction Register GPDRb from table
360 // *************************************************************************************
361 ldr r0, =pin_state_table
362 add r0, r0, #128 // use second quarter of table
363 mov r1, #1 // mask register
364 mov r2, #0 // this is the register where the value is composed
367 ldr r3, [r0], #4 // load table entry, increase pointer
368 ands r3, r3, #0x00000100
369 beq _exGPDRb1 // ZERO flag is set
370 orr r2, r2, r1 // OR mask bit to value
372 mov r1, r1, ASL #1 // shift mask bit
381 // *************************************************************************************
382 // extract value for Direction Register GPDRc from table
383 // *************************************************************************************
384 ldr r0, =pin_state_table
385 add r0, r0, #256 // use third quarter of table
386 mov r1, #1 // mask register
387 mov r2, #0 // this is the register where the value is composed
390 ldr r3, [r0], #4 // load table entry, increase pointer
391 ands r3, r3, #0x00000100
392 beq _exGPDRc1 // ZERO flag is set
393 orr r2, r2, r1 // OR mask bit to value
395 mov r1, r1, ASL #1 // shift mask bit
405 // *************************************************************************************
406 // extract value for Direction Register GPDRd from table
407 // *************************************************************************************
408 ldr r0, =pin_state_table
409 add r0, r0, #384 // use last quarter of table
410 mov r1, #1 // mask register
411 mov r2, #0 // this is the register where the value is composed
414 ldr r3, [r0], #4 // load table entry, increase pointer
415 ands r3, r3, #0x00000100
416 beq _exGPDRd1 // ZERO flag is set
417 orr r2, r2, r1 // OR mask bit to value
419 mov r1, r1, ASL #1 // shift mask bit
438 // *************************************************************************************
439 // extract value for Alternate Function Register GAFR0a from table
440 // *************************************************************************************
441 ldr r0, =pin_state_table
442 mov r1, #1 // mask register
443 mov r2, #0 // this is the register where the value is composed
446 ldr r3, [r0], #4 // load table entry, increase pointer
447 ands r4, r3, #0x01000000
448 beq _exGAFR0a1 // ZERO flag is set
449 orr r2, r2, r1 // OR mask bit to value
451 mov r1, r1, ASL #1 // shift mask bit
452 ands r4, r3, #0x02000000
453 beq _exGAFR0a2 // ZERO flag is set
454 orr r2, r2, r1 // OR mask bit to value
456 mov r1, r1, ASL #1 // shift mask bit
464 // *************************************************************************************
465 // extract value for Alternate Function Register GAFR1a from table
466 // *************************************************************************************
467 ldr r0, =pin_state_table
469 mov r1, #1 // mask register
470 mov r2, #0 // this is the register where the value is composed
473 ldr r3, [r0], #4 // load table entry, increase pointer
474 ands r4, r3, #0x01000000
475 beq _exGAFR1a1 // ZERO flag is set
476 orr r2, r2, r1 // OR mask bit to value
478 mov r1, r1, ASL #1 // shift mask bit
479 ands r4, r3, #0x02000000
480 beq _exGAFR1a2 // ZERO flag is set
481 orr r2, r2, r1 // OR mask bit to value
483 mov r1, r1, ASL #1 // shift mask bit
494 // *************************************************************************************
495 // extract value for Alternate Function Register GAFR0b from table
496 // *************************************************************************************
497 ldr r0, =pin_state_table
499 mov r1, #1 // mask register
500 mov r2, #0 // this is the register where the value is composed
503 ldr r3, [r0], #4 // load table entry, increase pointer
504 ands r4, r3, #0x01000000
505 beq _exGAFR0b1 // ZERO flag is set
506 orr r2, r2, r1 // OR mask bit to value
508 mov r1, r1, ASL #1 // shift mask bit
509 ands r4, r3, #0x02000000
510 beq _exGAFR0b2 // ZERO flag is set
511 orr r2, r2, r1 // OR mask bit to value
513 mov r1, r1, ASL #1 // shift mask bit
521 // *************************************************************************************
522 // extract value for Alternate Function Register GAFR1b from table
523 // *************************************************************************************
524 ldr r0, =pin_state_table
526 mov r1, #1 // mask register
527 mov r2, #0 // this is the register where the value is composed
530 ldr r3, [r0], #4 // load table entry, increase pointer
531 ands r4, r3, #0x01000000
532 beq _exGAFR1b1 // ZERO flag is set
533 orr r2, r2, r1 // OR mask bit to value
535 mov r1, r1, ASL #1 // shift mask bit
536 ands r4, r3, #0x02000000
537 beq _exGAFR1b2 // ZERO flag is set
538 orr r2, r2, r1 // OR mask bit to value
540 mov r1, r1, ASL #1 // shift mask bit
550 // *************************************************************************************
551 // extract value for Alternate Function Register GAFR0c from table
552 // *************************************************************************************
553 ldr r0, =pin_state_table
555 mov r1, #1 // mask register
556 mov r2, #0 // this is the register where the value is composed
559 ldr r3, [r0], #4 // load table entry, increase pointer
560 ands r4, r3, #0x01000000
561 beq _exGAFR0c1 // ZERO flag is set
562 orr r2, r2, r1 // OR mask bit to value
564 mov r1, r1, ASL #1 // shift mask bit
565 ands r4, r3, #0x02000000
566 beq _exGAFR0c2 // ZERO flag is set
567 orr r2, r2, r1 // OR mask bit to value
569 mov r1, r1, ASL #1 // shift mask bit
577 // *************************************************************************************
578 // extract value for Alternate Function Register GAFR1c from table
579 // *************************************************************************************
580 ldr r0, =pin_state_table
582 mov r1, #1 // mask register
583 mov r2, #0 // this is the register where the value is composed
586 ldr r3, [r0], #4 // load table entry, increase pointer
587 ands r4, r3, #0x01000000
588 beq _exGAFR1c1 // ZERO flag is set
589 orr r2, r2, r1 // OR mask bit to value
591 mov r1, r1, ASL #1 // shift mask bit
592 ands r4, r3, #0x02000000
593 beq _exGAFR1c2 // ZERO flag is set
594 orr r2, r2, r1 // OR mask bit to value
596 mov r1, r1, ASL #1 // shift mask bit
608 // *************************************************************************************
609 // extract value for Alternate Function Register GAFR0d from table
610 // *************************************************************************************
611 ldr r0, =pin_state_table
613 mov r1, #1 // mask register
614 mov r2, #0 // this is the register where the value is composed
617 ldr r3, [r0], #4 // load table entry, increase pointer
618 ands r4, r3, #0x01000000
619 beq _exGAFR0d1 // ZERO flag is set
620 orr r2, r2, r1 // OR mask bit to value
622 mov r1, r1, ASL #1 // shift mask bit
623 ands r4, r3, #0x02000000
624 beq _exGAFR0d2 // ZERO flag is set
625 orr r2, r2, r1 // OR mask bit to value
627 mov r1, r1, ASL #1 // shift mask bit
635 // *************************************************************************************
636 // extract value for Alternate Function Register GAFR1d from table
637 // *************************************************************************************
638 ldr r0, =pin_state_table
640 mov r1, #1 // mask register
641 mov r2, #0 // this is the register where the value is composed
644 ldr r3, [r0], #4 // load table entry, increase pointer
645 ands r4, r3, #0x01000000
646 beq _exGAFR1d1 // ZERO flag is set
647 orr r2, r2, r1 // OR mask bit to value
649 mov r1, r1, ASL #1 // shift mask bit
650 ands r4, r3, #0x02000000
651 beq _exGAFR1d2 // ZERO flag is set
652 orr r2, r2, r1 // OR mask bit to value
654 mov r1, r1, ASL #1 // shift mask bit
686 // *************************************************************************************
687 // extract value for Rising Edge Register GRERa from table
688 // *************************************************************************************
689 ldr r0, =pin_state_table
690 mov r1, #1 // mask register
691 mov r2, #0 // this is the register where the value is composed
694 ldr r3, [r0], #4 // load table entry, increase pointer
695 ands r3, r3, #0x00800000
696 beq _exGRERa1 // ZERO flag is set
697 orr r2, r2, r1 // OR mask bit to value
699 mov r1, r1, ASL #1 // shift mask bit
707 // *************************************************************************************
708 // extract value for Rising Edge Register GRERb from table
709 // *************************************************************************************
710 ldr r0, =pin_state_table
711 add r0, r0, #128 // use second third of table
712 mov r1, #1 // mask register
713 mov r2, #0 // this is the register where the value is composed
716 ldr r3, [r0], #4 // load table entry, increase pointer
717 ands r3, r3, #0x00800000
718 beq _exGRERb1 // ZERO flag is set
719 orr r2, r2, r1 // OR mask bit to value
721 mov r1, r1, ASL #1 // shift mask bit
731 // *************************************************************************************
732 // extract value for Rising Edge Register GRERc from table
733 // *************************************************************************************
734 ldr r0, =pin_state_table
735 add r0, r0, #256 // use last third of table
736 mov r1, #1 // mask register
737 mov r2, #0 // this is the register where the value is composed
740 ldr r3, [r0], #4 // load table entry, increase pointer
741 ands r3, r3, #0x00800000
742 beq _exGRERc1 // ZERO flag is set
743 orr r2, r2, r1 // OR mask bit to value
745 mov r1, r1, ASL #1 // shift mask bit
753 // *************************************************************************************
754 // extract value for Rising Edge Register GRERd from table
755 // *************************************************************************************
756 ldr r0, =pin_state_table
757 add r0, r0, #384 // use last third of table
758 mov r1, #1 // mask register
759 mov r2, #0 // this is the register where the value is composed
762 ldr r3, [r0], #4 // load table entry, increase pointer
763 ands r3, r3, #0x00800000
764 beq _exGRERd1 // ZERO flag is set
765 orr r2, r2, r1 // OR mask bit to value
767 mov r1, r1, ASL #1 // shift mask bit
779 // *************************************************************************************
780 // extract value for Falling Edge Register GFERa from table
781 // *************************************************************************************
782 ldr r0, =pin_state_table
783 mov r1, #1 // mask register
784 mov r2, #0 // this is the register where the value is composed
787 ldr r3, [r0], #4 // load table entry, increase pointer
788 ands r3, r3, #0x00400000
789 beq _exGFERa1 // ZERO flag is set
790 orr r2, r2, r1 // OR mask bit to value
792 mov r1, r1, ASL #1 // shift mask bit
800 // *************************************************************************************
801 // extract value for Falling Edge Register GFERb from table
802 // *************************************************************************************
803 ldr r0, =pin_state_table
804 add r0, r0, #128 // use second third of table
805 mov r1, #1 // mask register
806 mov r2, #0 // this is the register where the value is composed
809 ldr r3, [r0], #4 // load table entry, increase pointer
810 ands r3, r3, #0x00400000
811 beq _exGFERb1 // ZERO flag is set
812 orr r2, r2, r1 // OR mask bit to value
814 mov r1, r1, ASL #1 // shift mask bit
823 // *************************************************************************************
824 // extract value for Falling Edge Register GFERc from table
825 // *************************************************************************************
826 ldr r0, =pin_state_table
827 add r0, r0, #256 // use last third of table
828 mov r1, #1 // mask register
829 mov r2, #0 // this is the register where the value is composed
832 ldr r3, [r0], #4 // load table entry, increase pointer
833 ands r3, r3, #0x00400000
834 beq _exGFERc1 // ZERO flag is set
835 orr r2, r2, r1 // OR mask bit to value
837 mov r1, r1, ASL #1 // shift mask bit
845 // *************************************************************************************
846 // extract value for Falling Edge Register GFERd from table
847 // *************************************************************************************
848 ldr r0, =pin_state_table
849 add r0, r0, #384 // use last quarter of table
850 mov r1, #1 // mask register
851 mov r2, #0 // this is the register where the value is composed
854 ldr r3, [r0], #4 // load table entry, increase pointer
855 ands r3, r3, #0x00400000
856 beq _exGFERd1 // ZERO flag is set
857 orr r2, r2, r1 // OR mask bit to value
859 mov r1, r1, ASL #1 // shift mask bit
871 mov r15, r14 // return
878 // --------------------------------------------------------------------------
879 // end of hal_initio.S