+
+/* SDRAM configuration */
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define PWDT 1 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define FP 0 /* 0: not full page 1: full page */
+#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
+#define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
+#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
+ (BL << 7) | (PRCT << 0))
+
+/* SDRAM timing definitions */
+#define SDRAM_CLK 133
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - 16
+ .set \name, \clks - \offs
+ .else
+ .set \name, 0
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_64M
+/* MT46H16M32LF-75 */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+/* tRC is actually max(tRC,tRFC,tXSR) */
+NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H32M32LF-6 or -75 */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
+ (tRCD << 4) | (tRC << 0))
+