packages/devs/flash/arm/mxc/v2_0/src/mxc_nfc.c

   1 //==========================================================================
   2 //
   3 //              mxc_nfc.c
   4 //
   5 //              Flash programming to support NAND flash on Freescale MXC platforms
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    Kevin Zhang <k.zhang@freescale.com>
  44 // Contributors: Kevin Zhang <k.zhang@freescale.com>
  45 // Date:                 2006-01-23 Initial version
  46 // Date:                 2007-12-20 Update to support 4K page and bbt management.
  47 // Purpose:
  48 // Description:
  49 //       -- Add bad block management according to Linux NAND MTD implementation.
  50 //              Reference linux/drivers/mtd/nand/nand_bbt.c by Thomas Gleixner
  51 //              Summary:
  52 //                 1. Last 4 blocks are reserved for one main BBT and one
  53 //                        mirror BBT (2 spare ones just in case a block turns bad.)
  54 //                 2. The main BBT block's spare area starts with "Bbt0" followed
  55 //                        by a version number starting from 1.
  56 //                 3. The mirror BBT block's spare area starts with "1tbB" followed
  57 //                        by a version number also starting from 1.
  58 //                 4. The actual main area, starting from first page in the BBT block,
  59 //                        is used to indicate if a block is bad or not through 2bit/block:
  60 //                              * The table uses 2 bits per block
  61 //                              * 11b:  block is good
  62 //                              * 00b:  block is factory marked bad
  63 //                              * 01b:  block is marked bad due to wear
  64 //                              * 10b:  block is marked reserved (for BBT)
  65 //              Redboot operations: During boot, it searches for the marker for
  66 //                                                      either main BBT or mirror BBT based on the marker:
  67 //                 case 1: Neither table is found:
  68 //                                 Do the bad block scan of the whole flash with ECC off. Use
  69 //                                 manufactor marked BI field to decide if a block is bad and
  70 //                                 then build the BBT in RAM. Then write this table to both
  71 //                                 main BBT block and mirror BBT block.
  72 //                 case 2: Only one table is found:
  73 //                                 Load the BBT from the flash and stored in the RAM.
  74 //                                 Then build the 2nd BBT in the flash.
  75 //                 case 3: If both tables found, load the one with higher version in the
  76 //                                 RAM and then update the block with older BBT info with the
  77 //                                 newer one. If same version, just then read out the table in
  78 //                                 RAM.
  79 //
  80 //####DESCRIPTIONEND####
  81 //
  82 //==========================================================================
  83
  84 #include <pkgconf/hal.h>
  85 #include <cyg/hal/hal_arch.h>
  86 #include <cyg/hal/hal_cache.h>
  87 #include <cyg/hal/hal_misc.h>
  88 #include <cyg/io/nand_bbt.h>
  89 #include <redboot.h>
  90 #include <stdlib.h>
  91
  92 #include CYGHWR_MEMORY_LAYOUT_H
  93
  94 #include <cyg/hal/hal_io.h>
  95 #define  _FLASH_PRIVATE_
  96 #include <cyg/io/flash.h>
  97
  98 #ifdef CYGHWR_FLASH_NAND_BBT_HEADER
  99 #include CYGHWR_FLASH_NAND_BBT_HEADER
 100 #endif
 101
 102 #include <cyg/io/imx_nfc.h>
 103
 104 #define ECC_FORCE_ON    1
 105 #define ECC_FORCE_OFF   2
 106
 107 typedef u64 flash_addr_t;
 108
 109 enum blk_bad_type
 110 {
 111         BLK_GOOD = 0,
 112         BLK_BAD_RUNTIME = 1,
 113         BLK_RESERVED = 2,
 114         BLK_BAD_FACTORY = 3,
 115 };
 116
 117 #define diag_printf1(fmt...) CYG_MACRO_START                                            \
 118                 if (g_nfc_debug_level >= NFC_DEBUG_MIN) diag_printf(fmt);       \
 119 CYG_MACRO_END
 120
 121 #define MXC_UNLOCK_BLK_END              0xFFFF
 122
 123 extern unsigned int hal_timer_count(void);
 124 static int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len);
 125 static int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose);
 126
 127 static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force);
 128 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
 129                                                           u32 num_of_nand_chips);
 130 static int nfc_erase_blk(u32 ra);
 131 static void print_page(u32 addr, bool spare_only);
 132 static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off);
 133 static int mxc_nfc_scan(bool lowlevel);
 134 static void read_nflash_id(u32 *id, u32 cs_line);
 135 static int nfc_program_blk(u32 ra, u8 *buf, u32 len);
 136
 137 static void print_pkt_16(u16 *pkt, u32 len);
 138
 139 // globals
 140 static int g_ecc_enable = true;
 141 static int g_spare_only_read_ok = true;
 142 static int g_nfc_debug_level = NFC_DEBUG_DEF;
 143 static bool g_nfc_debug_measure = false;
 144 static bool g_is_2k_page = false;
 145 static unsigned int g_block_offset;
 146 static bool g_is_4k_page = false;
 147 static unsigned int g_nfc_version = MXC_NFC_V1; // default to version 1.0
 148 static int      num_of_nand_chips = 1;
 149 static int num_of_nand_chips_for_nandsize = 1;
 150 static int scale_block_cnt = 1;
 151
 152 #define nfc_printf(level, args...) CYG_MACRO_START      \
 153                 if (g_nfc_debug_level >= level)                         \
 154                         diag_printf(args);                                              \
 155 CYG_MACRO_END
 156
 157 #if defined(NFC_V2_0) || defined(NFC_V2_1)
 158 #include <cyg/io/mxc_nfc_v2.h>
 159 #elif defined(NFC_V3_0)
 160 #include <cyg/io/mxc_nfc_v3.h>
 161 #else
 162 #include <cyg/io/mxc_nfc.h>
 163 #endif
 164
 165 #ifndef NAND_LAUNCH_REG
 166 #define NAND_LAUNCH_REG                         0xDEADEEEE
 167 #define NAND_CONFIGURATION1_REG         0xDEADEEEE
 168 #define NFC_FLASH_CONFIG2_REG           0xDEADEEEE
 169 #define NFC_FLASH_CONFIG2_ECC_EN        0xDEADEEEE
 170 #define write_nfc_ip_reg(a, b)
 171 #endif
 172
 173 #ifndef MXCFLASH_SELECT_MULTI
 174 void flash_query(void *data)
 175 #else
 176 void nandflash_query(void *data)
 177 #endif
 178 {
 179         u32 id[2];
 180
 181         nfc_printf(NFC_DEBUG_MIN, "%s@%d data=%p\n", __FUNCTION__, __LINE__, data);
 182
 183         read_nflash_id(&id[0], 0);
 184         nfc_printf(NFC_DEBUG_MIN, "%s(ID=0x%02x: 0x%02x, 0x%02x, 0x%02x)\n", __FUNCTION__,
 185                            id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
 186         if (data != NULL) {
 187                 nfc_printf(NFC_DEBUG_MAX, "%s@%d copy flash ID from %p to %p\n",
 188                                 __FUNCTION__, __LINE__, &id[0], data);
 189                 memcpy(data, id, sizeof(id));
 190         }
 191         nfc_printf(NFC_DEBUG_MAX, "%s@%d %p\n", __FUNCTION__, __LINE__,
 192                         __builtin_return_address(0));
 193 }
 194
 195 #ifndef MXCFLASH_SELECT_MULTI
 196 int flash_program_buf(void *addr, void *data, int len)
 197 #else
 198 int nandflash_program_buf(void *addr, void *data, int len)
 199 #endif
 200 {
 201         nfc_printf(NFC_DEBUG_MAX, "%s(addr=%p, data=%p, len=0x%08x)\n",
 202                            __FUNCTION__, addr, data, len);
 203         return nfc_program_region((u32)addr, data, len);
 204 }
 205
 206 #ifndef MXCFLASH_SELECT_MULTI
 207 int flash_erase_block(void *block, unsigned int size)
 208 #else
 209 int nandflash_erase_block(void *block, unsigned int size)
 210 #endif
 211 {
 212         nfc_printf(NFC_DEBUG_MAX, "%s(block=%p, size=0x%08x)\n",
 213                            __FUNCTION__, block, size);
 214         return nfc_erase_region((u32)block, size, 1, 0);
 215 }
 216
 217 #ifndef MXCFLASH_SELECT_MULTI
 218 bool flash_code_overlaps(void *start, void *end)
 219 #else
 220 bool nandflash_code_overlaps(void *start, void *end)
 221 #endif
 222 {
 223         extern unsigned char _stext[], _etext[];
 224
 225         return ((((unsigned long)&_stext >= (unsigned long)start) &&
 226                          ((unsigned long)&_stext < (unsigned long)end)) ||
 227                         (((unsigned long)&_etext >= (unsigned long)start) &&
 228                          ((unsigned long)&_etext < (unsigned long)end)));
 229 }
 230
 231 #ifndef MXCFLASH_SELECT_MULTI
 232 int flash_hwr_map_error(int e)
 233 #else
 234 int nandflash_hwr_map_error(int e)
 235 #endif
 236 {
 237         return e;
 238 }
 239
 240 #ifndef MXCFLASH_SELECT_MULTI
 241 int flash_lock_block(void *block)
 242 #else
 243 int nandflash_lock_block(void *block)
 244 #endif
 245 {
 246         // Not supported yet
 247         return 0;
 248 }
 249
 250 #ifndef MXCFLASH_SELECT_MULTI
 251 int flash_unlock_block(void *block, int block_size, int blocks)
 252 #else
 253 int nandflash_unlock_block(void *block, int block_size, int blocks)
 254 #endif
 255 {
 256         // Not supported yet
 257         return 0;
 258 }
 259
 260 //----------------------------------------------------------------------------
 261 // Now that device properties are defined, include magic for defining
 262 // accessor type and constants.
 263 #include <cyg/io/flash_dev.h>
 264
 265 // Information about supported devices
 266 typedef struct flash_dev_info {
 267         cyg_uint16       device_id;
 268         cyg_uint16       device_id2;
 269         cyg_uint16       device_id3;
 270         cyg_uint16       device_id4;
 271         cyg_uint16       page_size;
 272         cyg_uint16       spare_size;
 273         cyg_uint32       pages_per_block;
 274         cyg_uint32       block_size;
 275         cyg_int32        block_count;
 276         cyg_uint32       device_size;
 277         cyg_uint32       port_size;             // x8 or x16 IO
 278         cyg_uint32       type;                  // SLC vs MLC
 279         cyg_uint32       options;
 280         cyg_uint32       fis_start_addr;
 281         cyg_uint32       bi_off;
 282         cyg_uint32       bbt_blk_max_nr;
 283         cyg_uint8        vendor_info[96];
 284         cyg_uint32       col_cycle;                // number of column address cycles
 285         cyg_uint32       row_cycle;                // number of row address cycles
 286         cyg_uint32       max_bad_blk;
 287 } flash_dev_info_t;
 288
 289 static const flash_dev_info_t *flash_dev_info;
 290 static const flash_dev_info_t supported_devices[] = {
 291 #include <cyg/io/mxc_nand_parts.inl>
 292 };
 293 #define NUM_DEVICES NUM_ELEMS(supported_devices)
 294
 295 #define COL_CYCLE                                       flash_dev_info->col_cycle
 296 #define ROW_CYCLE                                       flash_dev_info->row_cycle
 297 #define NF_PG_SZ                                        ((flash_dev_info->page_size) * num_of_nand_chips)
 298 #define NF_SPARE_SZ                                     ((flash_dev_info->spare_size) * num_of_nand_chips)
 299 #define NF_PG_PER_BLK                           flash_dev_info->pages_per_block
 300 #define NF_DEV_SZ                                       ((flash_dev_info->device_size) * num_of_nand_chips_for_nandsize)
 301 #define NF_BLK_SZ                                       ((flash_dev_info->block_size) * num_of_nand_chips)
 302 #define NF_BLK_CNT                                      ((flash_dev_info->block_count) / scale_block_cnt)
 303 #define NF_VEND_INFO                            flash_dev_info->vendor_info
 304 #define NF_OPTIONS                                      flash_dev_info->options
 305 #define NF_BBT_MAX_NR                           flash_dev_info->bbt_blk_max_nr
 306 #define NF_OPTIONS                                      flash_dev_info->options
 307 #define NF_BI_OFF                                       flash_dev_info->bi_off
 308
 309 #define MXC_NAND_ADDR_MASK                              (NF_DEV_SZ - 1)
 310 #define BLOCK_TO_OFFSET(blk)                    ((blk) * NF_PG_PER_BLK * NF_PG_SZ)
 311 #define BLOCK_TO_PAGE(blk)                              ((blk) * NF_PG_PER_BLK)
 312 #define BLOCK_PAGE_TO_OFFSET(blk, pge)  (((blk) * NF_PG_PER_BLK + (pge)) * NF_PG_SZ)
 313 #define OFFSET_TO_BLOCK(offset)                 ((u32)((offset) / (NF_PG_SZ * NF_PG_PER_BLK)))
 314 #define OFFSET_TO_PAGE(offset)                  ((u32)((offset) / NF_PG_SZ) % NF_PG_PER_BLK)
 315
 316 static u8 *g_bbt, *g_page_buf;
 317 static u32 g_bbt_sz;
 318 static bool mxcnfc_init_ok = false;
 319 static bool mxc_nfc_scan_done;
 320
 321 // this callback allows the platform specific function to be called right
 322 // after flash_dev_query()
 323 nfc_setup_func_t *nfc_setup = NULL;
 324
 325 // this callback allows the platform specific iomux setup
 326 nfc_iomuxsetup_func_t *nfc_iomux_setup = NULL;
 327
 328 static flash_addr_t flash_region_start;
 329 static flash_addr_t flash_region_end;
 330 static int flash_enable;
 331
 332 /* This assumes reading the flash with monotonically increasing flash addresses */
 333 static flash_addr_t nfc_l_to_p(flash_addr_t addr)
 334 {
 335         if (g_block_offset == 0) {
 336                 return addr & MXC_NAND_ADDR_MASK;
 337         } else {
 338                 flash_addr_t ra;
 339                 u32 block = (addr & MXC_NAND_ADDR_MASK) / NF_BLK_SZ;
 340                 u32 offset = addr % NF_BLK_SZ;
 341
 342                 ra = (block + g_block_offset) * NF_BLK_SZ + offset;
 343                 if (offset == 0) {
 344                         nfc_printf(NFC_DEBUG_MIN,
 345                                            "Remapping block %u at addr 0x%08llx to block %u at addr 0x%08llx\n",
 346                                            block, (u64)addr, block + g_block_offset, (u64)ra);
 347                 }
 348                 return ra;
 349         }
 350 }
 351
 352 static int flash_addr_valid(flash_addr_t addr)
 353 {
 354         if (!flash_enable) {
 355                 nfc_printf(NFC_DEBUG_MIN, "No flash area enabled\n");
 356                 return 1;
 357         }
 358         if (addr < flash_region_start || addr >= flash_region_end) {
 359                 diag_printf("Flash address 0x%08llx is outside valid region 0x%08llx..0x%08llx\n",
 360                                         (u64)addr, (u64)flash_region_start, (u64)flash_region_end);
 361                 return 0;
 362         }
 363         return 1;
 364 }
 365
 366 /* FIXME: we should pass flash_addr_t as arguments */
 367 void mxc_flash_enable(void *start, void *end)
 368 {
 369         flash_addr_t s = (unsigned long)start & MXC_NAND_ADDR_MASK;
 370         flash_addr_t e = ((unsigned long)end - 1) & MXC_NAND_ADDR_MASK;
 371
 372         if (flash_enable++ == 0) {
 373                 flash_region_start = s;
 374                 flash_region_end = e;
 375                 diag_printf1("Enabling flash region 0x%08llx..0x%08llx\n",
 376                                          (u64)s, (u64)e);
 377                 g_block_offset = 0;
 378         } else {
 379                 if (s < flash_region_start ||
 380                         e > flash_region_end) {
 381                         diag_printf("** WARNING: Enable 0x%08llx..0x%08llx outside enabled flash region 0x%08llx..0x%08llx\n",
 382                                                 (u64)s, (u64)e, (u64)flash_region_start, (u64)flash_region_end);
 383                 }
 384         }
 385 }
 386
 387 void mxc_flash_disable(void *start, void *end)
 388 {
 389         flash_addr_t s = (unsigned long)start & MXC_NAND_ADDR_MASK;
 390         flash_addr_t e = ((unsigned long)end - 1) & MXC_NAND_ADDR_MASK;
 391
 392         if (flash_enable) {
 393                 if (--flash_enable == 0) {
 394                         diag_printf1("Disabling flash region 0x%08llx..0x%08llx\n",
 395                                                  (u64)s, (u64)e);
 396                         if (s != flash_region_start ||
 397                                 e != flash_region_end) {
 398                                 diag_printf("** Error: Disable 0x%08llx..0x%08llx not equal to enabled flash region 0x%08llx..0x%08llx\n",
 399                                                 (u64)s, (u64)e, (u64)flash_region_start, (u64)flash_region_end);
 400                         }
 401                 }
 402         } else {
 403                 diag_printf("** Error: unbalanced call to flash_disable()\n");
 404         }
 405 }
 406
 407 int
 408 #ifndef MXCFLASH_SELECT_MULTI
 409 flash_hwr_init(void)
 410 #else
 411 nandflash_hwr_init(void)
 412 #endif
 413 {
 414         u32 id[2];
 415         int i;
 416
 417         nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
 418
 419         if (nfc_iomux_setup)
 420                 nfc_iomux_setup();
 421
 422         NFC_SET_NFC_ACTIVE_CS(0);
 423         NFC_CMD_INPUT(FLASH_Reset);
 424
 425         // Look through table for device data
 426         nfc_printf(NFC_DEBUG_MAX, "%s@%d %p\n", __FUNCTION__, __LINE__, &id[0]);
 427         flash_dev_query(&id[0]);
 428         nfc_printf(NFC_DEBUG_MAX, "%s@%d\n", __FUNCTION__, __LINE__);
 429
 430         flash_dev_info = supported_devices;
 431         for (i = 0; i < NUM_DEVICES; i++) {
 432                 if ((flash_dev_info->device_id == (id[0] & 0xffff)) &&
 433                         (flash_dev_info->device_id2 == 0xFFFF ||
 434                          flash_dev_info->device_id2 == (id[0] >> 16)))
 435                         break;
 436                 flash_dev_info++;
 437         }
 438         nfc_printf(NFC_DEBUG_MAX, "%s@%d\n", __FUNCTION__, __LINE__);
 439
 440         // Did we find the device? If not, return error.
 441         if (NUM_DEVICES == i) {
 442                 diag_printf("Unrecognized NAND part: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
 443                                         id[0] & 0xff, (id[0] >> 8) & 0xff, (id[0] >> 16) & 0xff, id[0] >> 24);
 444                 return FLASH_ERR_DRV_WRONG_PART;
 445         }
 446
 447         mxcnfc_init_ok = true;
 448
 449         if (NF_PG_SZ == 2048) {
 450                 g_is_2k_page = true;
 451                 g_spare_only_read_ok = false;
 452         }
 453         if (NF_PG_SZ == 4096) {
 454                 g_is_4k_page = true;
 455                 g_spare_only_read_ok = false;
 456         }
 457
 458         nfc_printf(NFC_DEBUG_MED, "%s(): %d out of NUM_DEVICES=%d, id=0x%02x\n",
 459                            __FUNCTION__, i, NUM_DEVICES, flash_dev_info->device_id);
 460
 461         if (nfc_setup) {
 462                 nfc_printf(NFC_DEBUG_MAX, "%s@%d\n", __FUNCTION__, __LINE__);
 463                 g_nfc_version = nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
 464                                                                   flash_dev_info->type, num_of_nand_chips);
 465         }
 466         nfc_printf(NFC_DEBUG_MAX, "%s@%d\n", __FUNCTION__, __LINE__);
 467         diag_printf1("NFC version: %02x\n", g_nfc_version);
 468         if (g_nfc_version >= MXC_NFC_V3) {
 469                 for (i = 2; i <= NUM_OF_CS_LINES; i++) {
 470                         u32 id_tmp[2];
 471                         read_nflash_id(&id_tmp[0], i - 1);
 472                         if (id[0] != id_tmp[0]) {
 473                                 break;
 474                         }
 475                         /* Support interleave with 1, 2, 4, 8 chips */
 476                         if (i == (num_of_nand_chips * 2)) {
 477                                 num_of_nand_chips = i;
 478                         }
 479                         NFC_CMD_INPUT(FLASH_Reset);
 480                 }
 481
 482                 if (nfc_setup && (num_of_nand_chips > 1)) {
 483                         nfc_setup(NF_PG_SZ / num_of_nand_chips, flash_dev_info->port_size,
 484                                                    flash_dev_info->type, num_of_nand_chips);
 485                 }
 486         }
 487
 488         NFC_ARCH_INIT();
 489
 490         g_bbt_sz = NF_BLK_CNT / 4;
 491         g_bbt = malloc(g_bbt_sz); // two bit for each block
 492         if (g_bbt == NULL) {
 493                 diag_printf("%s(): failed to allocate %d byte for bbt\n", __FUNCTION__, g_bbt_sz);
 494                 return FLASH_ERR_PROTOCOL;
 495         }
 496
 497         g_page_buf = malloc(NF_PG_SZ); // for programming less than one page size buffer
 498         if (g_page_buf == NULL) {
 499                 diag_printf("%s(): failed to allocate %d byte page buffer\n", __FUNCTION__,
 500                                         NF_PG_SZ);
 501                 return FLASH_ERR_PROTOCOL;
 502         }
 503         memset(g_bbt, 0, g_bbt_sz);
 504
 505         /* For now cap off the Device size to 2GB */
 506         i = 1;
 507         while ((i <= num_of_nand_chips) && ((NF_DEV_SZ * i) < 0x80000000)) {
 508                 num_of_nand_chips_for_nandsize = i;
 509                 i *= 2;
 510         }
 511
 512         scale_block_cnt = num_of_nand_chips / num_of_nand_chips_for_nandsize;
 513         // Hard wired for now
 514         flash_info.block_size = NF_BLK_SZ;
 515         flash_info.blocks = NF_BLK_CNT - CYGNUM_FLASH_NAND_BBT_BLOCKS;
 516         flash_info.start = (void *)MXC_NAND_BASE_DUMMY;
 517         flash_info.end = (void *)(MXC_NAND_BASE_DUMMY + NF_DEV_SZ -
 518                                                           CYGNUM_FLASH_NAND_BBT_BLOCKS * NF_BLK_SZ);
 519
 520         mxc_nfc_scan(false); // look for table
 521
 522         diag_printf1("%s(): block_size=0x%08x, blocks=0x%08x, start=%p, end=%p\n",
 523                                  __FUNCTION__, flash_info.block_size, flash_info.blocks,
 524                                  flash_info.start, flash_info.end);
 525
 526         return FLASH_ERR_OK;
 527 }
 528
 529 // used by redboot/current/src/flash.c
 530 int mxc_nand_fis_start(void)
 531 {
 532         return flash_dev_info->fis_start_addr * num_of_nand_chips;
 533 }
 534
 535 static inline u8 get_byte(cyg_uint16 *buf, int offs)
 536 {
 537         cyg_uint16 word = buf[offs >> 1];
 538         if (offs & 1) {
 539                 return word >> 8;
 540         }
 541         return word & 0xff;
 542 }
 543
 544 static inline void store_byte(cyg_uint16 *buf, int offs, u8 val)
 545 {
 546         cyg_uint16 word = buf[offs >> 1];
 547
 548         if (offs & 1) {
 549                 word = (word & 0x00ff) | ((u16)val << 8);
 550         } else {
 551                 word = (word & 0xff00) | val;
 552         }
 553         buf[offs >> 1] = word;
 554 }
 555
 556 static inline bool nfc_verify_addr(unsigned long dst, unsigned long len)
 557 {
 558         if (dst < NAND_MAIN_BUF0 || dst + len >= NAND_SPAR_BUF3 + NFC_SPARE_BUF_SZ) {
 559                 diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, dst);
 560                 return false;
 561         }
 562         return true;
 563 }
 564
 565 static void nfc_buf_read(void *dst, unsigned long src, u32 len)
 566 {
 567         u16 *s = (u16 *)(src & ~1);
 568         u8 *bp = dst;
 569
 570         if (len == 0) {
 571                 return;
 572         }
 573         if (src + len < src) {
 574                 diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
 575                                         src, src + len);
 576         }
 577         if ((unsigned long)dst + len < (unsigned long)dst) {
 578                 diag_printf("%s: Bad address range 0x%08lx .. 0x%08lx\n", __FUNCTION__,
 579                                         (unsigned long)dst, (unsigned long)dst + len);
 580         }
 581         if (src < NAND_MAIN_BUF0 || src + len >= NAND_SPAR_BUF3 + NF_PG_SZ) {
 582                 diag_printf("%s: Bad NFC Buffer address 0x%08lx\n", __FUNCTION__, src);
 583                 return;
 584         }
 585         if ((unsigned long)dst >= NAND_MAIN_BUF0 &&
 586                 (unsigned long)dst < NAND_SPAR_BUF3 + NF_PG_SZ) {
 587                 diag_printf("%s: Bad memory address 0x%08lx\n", __FUNCTION__,
 588                                         (unsigned long)dst);
 589                 return;
 590         }
 591         if (src & 1) {
 592                 *bp++ = get_byte(s, 1);
 593                 s++;
 594                 len--;
 595         }
 596         if ((unsigned long)bp & 1) {
 597                 while (len > 1) {
 598                         u16 word = *s++;
 599                         *bp++ = word & 0xff;
 600                         *bp++ = word >> 8;
 601                         len -= 2;
 602                 }
 603         } else {
 604                 u16 *wp = (u16 *)bp;
 605
 606                 while (len > 1) {
 607                         *wp++ = *s++;
 608                         len -= 2;
 609                 }
 610                 bp = (u8*)wp;
 611         }
 612         if (len != 0) {
 613                 u16 word = *s;
 614                 *bp = word & 0xff;
 615         }
 616 }
 617
 618 static void nfc_buf_write(unsigned long dst, void *src, u32 len)
 619 {
 620         u8 *bp = src;
 621         u16 *d = (u16 *)(dst & ~1);
 622
 623         if (len == 0) {
 624                 return;
 625         }
 626         if (!nfc_verify_addr(dst, len)) {
 627                 return;
 628         }
 629         diag_printf1("Copying %u byte from %p..%p to flash buffer %08lx..%08lx\n",
 630                                 len, bp, bp + len - 1, dst, dst + len - 1);
 631         if (dst & 1) {
 632                 store_byte(d, 1, *bp);
 633                 d++;
 634                 bp++;
 635                 len--;
 636         }
 637         if ((unsigned long)bp & 1) {
 638                 while (len > 1) {
 639                         u16 word;
 640                         word = *bp++;
 641                         word |= (u16)(*bp++) << 8;
 642                         *d++ = word;
 643                         len -= 2;
 644                 }
 645         } else {
 646                 u16 *wp = (u16 *)bp;
 647                 while (len > 1) {
 648                         *d++ = *wp++;
 649                         len -= 2;
 650                 }
 651                 bp = (u8 *)wp;
 652         }
 653         if (len != 0) {
 654                 store_byte(d, 1, *bp);
 655         }
 656 }
 657
 658 #ifndef NFC_V3_0
 659 /*!
 660  * Starts the address input cycles for different operations as defined in ops.
 661  *
 662  * @param ops                   operations as defined in enum nfc_addr_ops
 663  * @param pg_no                 page number offset from 0
 664  * @param pg_off                byte offset within the page
 665  * @param is_erase              don't care for earlier NFC
 666  * @param cs_line                don't care for earlier NFC
 667  */
 668 static void start_nfc_addr_ops(u32 ops, u32 pg_no, u32 pg_off, u32 is_erase,
 669                                    u32 cs_line, u32 num_of_chips)
 670 {
 671         int i;
 672
 673         switch (ops) {
 674         case FLASH_Read_ID:
 675                 /* Only supports one NAND chip (CS0) */
 676                 if (cs_line != 0)
 677                         return;
 678                 NFC_ADDR_INPUT(0);
 679                 return;
 680         case FLASH_Read_Mode1:
 681         case FLASH_Program:
 682                 for (i = 0; i < COL_CYCLE; i++, pg_off >>= 8) {
 683                         NFC_ADDR_INPUT(pg_off & 0xFF);
 684                 }
 685                 // don't break on purpose
 686         case FLASH_Block_Erase:
 687                 for (i = 0; i < ROW_CYCLE; i++, pg_no >>= 8) {
 688                         NFC_ADDR_INPUT(pg_no & 0xFF);
 689                 }
 690                 break;
 691         default:
 692                 diag_printf("!!!!!! %s(): wrong ops: %d !!!!!\n", __FUNCTION__, ops);
 693                 return;
 694         }
 695 }
 696 #endif                                  // #ifndef NFC_V3_0
 697
 698 static void read_nflash_id(u32 *id, u32 cs_line)
 699 {
 700         volatile u32 *ptr = (volatile u32*)NAND_MAIN_BUF0;
 701
 702         nfc_printf(NFC_DEBUG_MIN, "%s: read flash id from chip %d @ %p\n",
 703                            __FUNCTION__, cs_line, ptr);
 704
 705         NFC_PRESET(MXC_UNLOCK_BLK_END);
 706         NFC_SET_NFC_ACTIVE_CS(cs_line);
 707         NFC_CMD_INPUT(FLASH_Read_ID);
 708
 709         start_nfc_addr_ops(FLASH_Read_ID, 0, 0, 0, cs_line, num_of_nand_chips);
 710         NFC_DATA_OUTPUT(RAM_BUF_0, FDO_FLASH_ID, g_ecc_enable);
 711
 712         *id++ = *ptr++;
 713         *id++ = *ptr++;
 714 }
 715
 716 static void mark_blk_bad(unsigned int block, unsigned char *buf,
 717                                                  enum blk_bad_type bad_type)
 718 {
 719         unsigned int off = block >> 2;                  // byte offset - each byte can hold status for 4 blocks
 720         unsigned int sft = (block & 3) << 1;    // bit shift 0, 2, 4, 6
 721         unsigned char val = buf[off];
 722
 723         if (block > NF_BLK_CNT) {
 724                 diag_printf("%s: Block number %u out of range: 0..%u\n", __FUNCTION__,
 725                                         block, NF_BLK_CNT - 1);
 726                 return;
 727         }
 728         val = (val & ~(3 << sft)) | (bad_type << sft);
 729         buf[off] = val;
 730 }
 731
 732 /*!
 733  * Checks to see if a block is bad. If buf is not NULL, it indicates a valid
 734  * BBT in the RAM. In this case, it assumes to have 2-bit to represent each
 735  * block for good or bad
 736  *                              * 11b:  block is good
 737  *                              * 00b:  block is factory marked bad
 738  *                              * 01b:  block is marked bad due to wear
 739  *                              * 10b:  block is marked reserved (for BBT)
 740  * If buf is NULL, then it indicates a low level scan based on the certain
 741  * offset value in certain pages and certain offset to be non-0xFF. In this
 742  * case, the HW ECC will be turned off.
 743  *
 744  * @param block         0-based block number
 745  * @param buf           BBT buffer. Could be NULL (see above explanation)
 746  *
 747  * @return                      1 if bad block; 0 otherwise
 748  */
 749 static int nfc_is_badblock(u32 block, u8 *buf)
 750 {
 751         u32 off;           // byte offset
 752         u32 sft;           // bit shift 0, 2, 4, 6
 753         flash_addr_t addr;
 754         u16 temp, i;
 755         int res;
 756         u32 pg_no;
 757
 758         if (buf) {
 759                 // use BBT
 760                 off = block >> 2;               // byte offset
 761                 sft = (block & 3) << 1;  // bit shift 0, 2, 4, 6
 762                 res = (buf[off] >> sft) & 0x3;
 763                 if (res) {
 764                         addr = BLOCK_TO_OFFSET(block);
 765                         diag_printf1("Block %u at 0x%08llx is marked %s (%d) in BBT@%p[%02x] mask %02x\n",
 766                                                  block, (u64)addr, res == BLK_RESERVED ? "reserved" :
 767                                                  res == BLK_BAD_FACTORY ? "factory bad" : "runtime bad",
 768                                                  res, buf, off, 3 << sft);
 769                 }
 770                 return res;
 771         }
 772
 773         // need to do low level scan with ECC off
 774         if (NF_OPTIONS & NAND_BBT_SCANLSTPAGE) {
 775                 if (g_is_4k_page || g_is_2k_page) {
 776                         addr = (block + 1) * NF_BLK_SZ - NF_PG_SZ;
 777                         pg_no = addr / NF_PG_SZ;
 778                         for (i = 0; i < num_of_nand_chips; i++) {
 779                                 // we don't do partial page read here. No ecc either
 780                                 nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips);
 781                                 temp = readw((u32)NAND_MAIN_BUF0 + NF_BI_OFF);
 782                                 if ((temp & 0xFF) != 0xFF) {
 783                                         return BLK_BAD_FACTORY;
 784                                 }
 785                         }
 786                 } else {
 787                         diag_printf("only 2K/4K page is supported\n");
 788                         // die here -- need to fix the SW
 789                         while (1);
 790                 }
 791                 return 0;
 792         }
 793         addr = block * NF_BLK_SZ;
 794         pg_no = addr / NF_PG_SZ;
 795         for (i = 0; i < num_of_nand_chips; i++) {
 796                 nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
 797                 if (g_is_2k_page || g_is_4k_page) {
 798                         temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
 799                 } else {
 800                         temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
 801                 }
 802                 if ((temp & 0xFF) != 0xFF) {
 803                         return BLK_BAD_FACTORY;
 804                 }
 805         }
 806         if (NF_OPTIONS & NAND_BBT_SCAN2NDPAGE) {
 807                 addr += NF_PG_SZ;
 808                 pg_no++;
 809                 for (i = 0; i < num_of_nand_chips; i++) {
 810                         nfc_read_pg_random(pg_no, 0, ECC_FORCE_OFF, i, num_of_nand_chips); // no ecc
 811                         if (g_is_2k_page || g_is_4k_page) {
 812                                 temp = readw(NAND_MAIN_BUF0 + NF_BI_OFF);
 813                         } else {
 814                                 temp = readw(NAND_SPAR_BUF0 + 4) >> 8; // BI is at 5th byte in spare area
 815                         }
 816                         if ((temp & 0xFF) != 0xFF) {
 817                                 return BLK_BAD_FACTORY;
 818                         }
 819                 }
 820         }
 821         return 0;
 822 }
 823
 824 static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
 825 {
 826         int i;
 827         u16 *p = (u16 *)buf;
 828         u16 fill = pattern;
 829
 830         fill = (fill << 8) | pattern;
 831         for (i = 0; i < size >> 1; i++) {
 832                 p[i] = fill;
 833         }
 834 }
 835
 836 #ifdef CYGHWR_FLASH_NAND_BBT_HEADER
 837 /*
 838  * check_short_pattern - [GENERIC] check if a pattern is in the buffer
 839  * @buf:        the buffer to search
 840  * @td:         search pattern descriptor
 841  *
 842  * Check for a pattern at the given place. Used to search bad block
 843  * tables and good / bad block identifiers.
 844 */
 845 static int check_short_pattern(void *buf, struct nand_bbt_descr *td)
 846 {
 847         int i;
 848
 849         for (i = 0; i < td->len; i++) {
 850                 if (get_byte(buf, td->offs + i) != td->pattern[i]) {
 851                         return -1;
 852                 }
 853         }
 854         return 0;
 855 }
 856
 857 static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force);
 858 /*
 859  * Program g_bbt into the NAND block with offset at g_main_bbt_addr.
 860  * This assumes that the g_bbt has been built already.
 861  *
 862  * If g_main_bbt_addr is 0, search for a free block from the bottom 4 blocks (but make
 863  * sure not re-using the mirror block). If g_mirror_bbt_page is 0, do the same thing.
 864  * Otherwise, just use g_main_bbt_addr, g_mirror_bbt_page numbers to prgram the
 865  * g_bbt into those two blocks.
 866  * todo: need to do the version to see which one is newer.
 867  *
 868  * @return      0 if successful; -1 otherwise.
 869  */
 870 static int mxc_nfc_write_bbt_page(struct nand_bbt_descr *td)
 871 {
 872         int ret;
 873         u32 block = td->pages / NF_PG_PER_BLK;
 874         flash_addr_t addr = td->pages * NF_PG_SZ;
 875
 876         ret = nfc_erase_blk(addr);
 877         if (ret != 0) {
 878                 diag_printf("Failed to erase bbt block %u\n", block);
 879                 return ret;
 880         }
 881         ret = nfc_write_page(td->pages, 0, 0);
 882         if (ret != 0) {
 883                 diag_printf("Failed to write bbt block %u\n", block);
 884                 return ret;
 885         }
 886         mark_blk_bad(block, g_bbt, BLK_RESERVED);
 887         return 0;
 888 }
 889
 890 static int mxc_nfc_write_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 891 {
 892         int ret = -1;
 893         int block;
 894         int pg_offs = 0;
 895         int page = 0;
 896         u16 *buf = (u16 *)NAND_MAIN_BUF0;
 897
 898         for (block = NF_BLK_CNT - 1; block >= NF_BLK_CNT - td->maxblocks - 1; block--) {
 899                 int pg = block * NF_PG_PER_BLK;
 900
 901                 if ((nfc_is_badblock(block, g_bbt) & 1) == 0) {
 902                         if (md != NULL && md->pages == pg) {
 903                                 continue;
 904                         }
 905                         td->pages = pg;
 906                         break;
 907                 }
 908         }
 909         if (td->pages < 0) {
 910                 return -1;
 911         }
 912         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
 913         mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
 914         diag_printf1("%s: Updating bbt %c%c%c%c version %d\n", __FUNCTION__,
 915                                  td->pattern[0], td->pattern[1], td->pattern[2], td->pattern[3], td->version);
 916         nfc_buf_write(NAND_SPAR_BUF0 + td->offs, td->pattern, td->len);
 917         store_byte((u16 *)NAND_SPAR_BUF0, td->veroffs, td->version);
 918
 919         for (block = 0, pg_offs = 0; block < NF_BLK_CNT; pg_offs++) {
 920                 u16 tmp = 0xffff;
 921                 int i;
 922
 923                 if (pg_offs << 1 >= NF_PG_SZ) {
 924                         ret = mxc_nfc_write_bbt_page(td);
 925                         if (ret != 0) {
 926                                 return ret;
 927                         }
 928                         page++;
 929                         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
 930                         mxc_nfc_buf_clear(NAND_MAIN_BUF0, 0xff, NF_PG_SZ);
 931                         pg_offs = 0;
 932                 }
 933                 for (i = 0; i < 16 && block < NF_BLK_CNT; i += 2, block++) {
 934                         u8 code = nfc_is_badblock(block, g_bbt);
 935                         if ((code & 1) != 0) {
 936                                 tmp &= ~(code << i);
 937                                 diag_printf1("%s: bad block %u pattern[%p] 0x%04x mask 0x%04x\n", __FUNCTION__,
 938                                                          block, &buf[pg_offs], tmp, 0x03 << i);
 939                         }
 940                 }
 941                 buf[pg_offs] = tmp;
 942         }
 943         if (pg_offs > 0) {
 944                 diag_printf1("%s: Writing final bbt block %d page %d\n", __FUNCTION__,
 945                                          td->pages / NF_PG_PER_BLK, page);
 946                 ret = mxc_nfc_write_bbt_page(td);
 947         }
 948         return ret;
 949 }
 950
 951 static int mxc_nfc_update_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 952 {
 953         int ret;
 954
 955         if (td == NULL) {
 956                 return -1;
 957         }
 958         if (td->pages < 0 && (md == NULL || md->pages == -1)) {
 959                 td->version = 1;
 960         } else {
 961                 if (md != NULL && md->pages >= 0) {
 962                         if (md->version >= td->version) {
 963                                 td->version = ++md->version;
 964                         } else {
 965                                 md->version = ++td->version;
 966                         }
 967                 } else {
 968                         td->version++;
 969                 }
 970         }
 971         ret = mxc_nfc_write_bbt(td, md);
 972         if (ret) {
 973                 diag_printf("** Error: Failed to update main BBT\n");
 974         }
 975         if (md) {
 976                 ret = mxc_nfc_write_bbt(md, td);
 977                 if (ret) {
 978                         diag_printf("** Error: Failed to update mirror BBT\n");
 979                 }
 980         }
 981         return ret;
 982 }
 983
 984 static int program_bbt_to_flash(void)
 985 {
 986         return mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr);
 987 }
 988 #else
 989 static int program_bbt_to_flash(void)
 990 {
 991         return 0;
 992 }
 993 #endif
 994
 995 /*!
 996  * Unconditionally erase a block without checking the BI field.
 997  * Note that there is NO error checking for passed-in ra.
 998  *
 999  * @param ra            starting address in the raw address space (offset)
1000  *                                      Must be block-aligned
1001  * @return                      0 if successful; -1 otherwise
1002  */
1003 static int nfc_erase_blk(u32 ra)
1004 {
1005         u16 flash_status, i;
1006         u32 pg_no, pg_off;
1007
1008         if (g_nfc_version >= MXC_NFC_V3) {
1009                 // combine the two commands for erase
1010                 nfc_reg_write((FLASH_Start_Erase << 8) | FLASH_Block_Erase, NAND_CMD_REG);
1011                 pg_no = ra / NF_PG_SZ;
1012                 pg_off = ra % NF_PG_SZ;
1013                 for (i = 0; i < num_of_nand_chips; i++) {
1014                         start_nfc_addr_ops(FLASH_Block_Erase, pg_no, pg_off, 1, i, num_of_nand_chips);
1015                         // start auto-erase
1016                         nfc_reg_write(NAND_LAUNCH_AUTO_ERASE, NAND_LAUNCH_REG);
1017                         wait_op_done();
1018                         pg_off = 0;
1019                 }
1020                 flash_status = NFC_STATUS_READ();
1021                 // check I/O bit 0 to see if it is 0 for success
1022                 if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
1023                         return -1;
1024                 }
1025         } else {
1026                 NFC_CMD_INPUT(FLASH_Block_Erase);
1027                 start_nfc_addr_ops(FLASH_Block_Erase, ra / NF_PG_SZ, ra % NF_PG_SZ,
1028                                                    1, 0, num_of_nand_chips);
1029                 NFC_CMD_INPUT(FLASH_Start_Erase);
1030
1031                 flash_status = NFC_STATUS_READ();
1032
1033                 // check I/O bit 0 to see if it is 0 for success
1034                 if ((flash_status & 0x1) != 0) {
1035                         return -1;
1036                 }
1037         }
1038         return 0;
1039 }
1040
1041 /*!
1042  * Program a block of data in the flash. This function doesn't do
1043  * bad block checking. But if program fails, it return error.
1044  * Note: If "len" is less than a block it will program up to a page's
1045  *               boundary. If not within a page boundary, then it fills the
1046  *               rest of the page with 0xFF.
1047  *
1048  * @param ra            destination raw flash address
1049  * @param buf           source address in the RAM
1050  * @param len           len to be programmed
1051  *
1052  * @return                      0 if successful; -1 otherwise
1053  */
1054 static int nfc_program_blk(u32 ra, u8 *buf, u32 len)
1055 {
1056         u32 temp = num_of_nand_chips;
1057
1058         /* Needed when romupdate is called */
1059         if (ra == 0)
1060                 num_of_nand_chips = 1;
1061
1062         for (; len >= NF_PG_SZ; len -= NF_PG_SZ) {
1063                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, buf, 0) != 0) {
1064                         return -1;
1065                 }
1066                 ra += NF_PG_SZ;
1067                 buf += NF_PG_SZ;
1068         }
1069         if (len != 0) {
1070                 diag_printf1("Clearing flash buffer from %p..%p\n", g_page_buf + len - 1,
1071                                         g_page_buf + NF_PG_SZ - 1);
1072                 memset(g_page_buf + len, 0xFF, NF_PG_SZ - len);
1073                 diag_printf1("Copying partial page from %p..%p to %p..%p\n",
1074                                         buf, buf + len - 1, g_page_buf, g_page_buf + len);
1075                 memcpy(g_page_buf, buf, len);
1076                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, g_page_buf, 0) != 0) {
1077                         num_of_nand_chips = temp;
1078                         return -1;
1079                 }
1080         }
1081         num_of_nand_chips = temp;
1082         return 0;
1083 }
1084
1085 /*!
1086  * Erase a range of NAND flash good blocks only.
1087  * It skips bad blocks and update the BBT once it sees new bad block due to erase.
1088  * @param addr                  raw NAND flash address. it has to be block size aligned
1089  * @param len                   number of bytes
1090  * @param skip_bad              if 1, don't erase bad block; otherwise, always erase
1091  * @param verbose               use true to print more messages
1092  *
1093  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1094  */
1095 static int nfc_erase_region(flash_addr_t addr, u32 len, bool skip_bad, bool verbose)
1096 {
1097         u32 sz, blk, update = 0, j = 0;
1098
1099         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx len=0x%08x\n",
1100                            __FUNCTION__, (u64)addr, len);
1101
1102         if ((addr % NF_BLK_SZ) != 0) {
1103                 diag_printf("Error: flash address 0x%08llx not block aligned\n", addr);
1104                 return FLASH_ERR_INVALID;
1105         }
1106         if ((len % NF_BLK_SZ) != 0 || len == 0) {
1107                 diag_printf("Error: invalid length %u (must be > 0 and block aligned)\n", len);
1108                 return FLASH_ERR_INVALID;
1109         }
1110         addr &= MXC_NAND_ADDR_MASK;
1111         // now addr has to be block aligned
1112         for (sz = 0; sz < len; addr += NF_BLK_SZ, j++, sz += NF_BLK_SZ) {
1113                 if (!flash_addr_valid(addr)) {
1114                         return 0;
1115                 }
1116                 blk = OFFSET_TO_BLOCK(addr);
1117                 if (skip_bad && nfc_is_badblock(blk, g_bbt)) {
1118                         diag_printf("\nSkipping bad block %u at addr 0x%08llx\n",
1119                                                 blk, (u64)addr);
1120                         continue;
1121                 }
1122                 if (nfc_erase_blk(addr) != 0) {
1123                         diag_printf("\n** Error: Failed to erase block %u at addr 0x%08llx\n",
1124                                                 blk, (u64)addr);
1125                         mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
1126                         // we don't need to update the table immediately here since even
1127                         // with power loss now, we should see the same erase error again.
1128                         update++;
1129                         continue;
1130                 }
1131                 if (verbose) {
1132                         if ((j % 0x20) == 0)
1133                                 diag_printf("\n%s 0x%08llx: ", skip_bad ? "Erase" : "FORCE erase", (u64)addr);
1134                         diag_printf(".");
1135                 }
1136         }
1137         if (update) {
1138                 if (program_bbt_to_flash() != 0) {
1139                         diag_printf("\nError: Failed to update bad block table\n");
1140                         return FLASH_ERR_PROGRAM;
1141                 }
1142                 diag_printf("\nnew bad blocks=%d\n", update);
1143         }
1144         return FLASH_ERR_OK;
1145 }
1146
1147 /*!
1148  * Program a range of NAND flash in blocks only.
1149  * It skips bad blocks and update the BBT once it sees new bad block due to program.
1150  * @param addr                  raw NAND flash address. it has to be block size aligned
1151  * @param len                   number of bytes
1152  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1153  */
1154 static int nfc_program_region(flash_addr_t addr, u8 *buf, u32 len)
1155 {
1156         u32 sz, blk, update = 0, partial_block_size;
1157
1158         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx, len=0x%08x\n",
1159                            __FUNCTION__, (u64)addr, len);
1160
1161         if ((addr % (NF_PG_SZ / num_of_nand_chips)) != 0) {
1162                 diag_printf("Error: flash address 0x%08llx not page aligned\n", (u64)addr);
1163                 return FLASH_ERR_INVALID;
1164         }
1165         if (len == 0) {
1166                 diag_printf("Error: invalid length\n");
1167                 return FLASH_ERR_INVALID;
1168         }
1169
1170         partial_block_size = NF_BLK_SZ - (addr % NF_BLK_SZ);
1171
1172         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
1173         addr = nfc_l_to_p(addr);
1174         while (1) {
1175                 if (!flash_addr_valid(addr)) {
1176                         diag_printf("\nToo many bad blocks in flash region 0x%08llx..0x%08llx\n",
1177                                                 (u64)flash_region_start, (u64)flash_region_end);
1178                         return FLASH_ERR_INVALID;
1179                 }
1180                 blk = OFFSET_TO_BLOCK(addr);
1181                 if (nfc_is_badblock(blk, g_bbt)) {
1182                         diag_printf("\nSkipping bad block %u at addr 0x%08llx\n", blk, addr);
1183                         g_block_offset++;
1184                         goto incr_address;
1185                 }
1186
1187                 sz = (len >= partial_block_size) ? partial_block_size : len;
1188
1189                 if (nfc_program_blk(addr, buf, sz) != 0) {
1190                         update++;
1191                         diag_printf("\nError: Failed to program flash block %u at addr 0x%08llx\n",
1192                                                 blk, (u64)addr);
1193                         mark_blk_bad(blk, g_bbt, BLK_BAD_RUNTIME);
1194                         // we don't need to update the table immediately here since even
1195                         // with power loss now, we should see the same program error again.
1196                         g_block_offset++;
1197                         goto incr_address;
1198                 }
1199                 diag_printf(".");
1200
1201                 len -= sz;
1202                 buf += sz;
1203                 if (len == 0)
1204                         break;
1205
1206 incr_address:
1207                 addr += partial_block_size;
1208                 partial_block_size = NF_BLK_SZ;
1209         }
1210         if (update) {
1211                 if (program_bbt_to_flash() != 0) {
1212                         diag_printf("\nError: Failed to update bad block table\n");
1213                         return -1;
1214                 }
1215         }
1216         return FLASH_ERR_OK;
1217 }
1218
1219 /*!
1220  * Read data from raw NAND flash address to memory. The MSB of the passed-
1221  * in flash address will be masked off inside the function.
1222  * It skips bad blocks and read good blocks of data for "len" bytes.
1223  *
1224  * @param addr                  NAND flash address.
1225  * @param buf                   memory buf where data will be copied to
1226  * @param len                   number of bytes
1227  * @return                              FLASH_ERR_OK (0) if successful; non-zero otherwise
1228  */
1229 int nfc_read_region(flash_addr_t addr, u8 *buf, u32 len)
1230 {
1231         u32 start_point = 0, pg_no;
1232         unsigned int offset = addr % NF_PG_SZ;
1233         int chk_bad = 1;
1234
1235         nfc_printf(NFC_DEBUG_MED, "%s: addr=0x%08llx, offset=%03x buf=0x%p, len=0x%08x\n",
1236                            __FUNCTION__, addr, offset, buf, len);
1237
1238         if (addr < (u32)flash_info.start || (addr + len) > (u32)flash_info.end || len == 0) {
1239                 diag_printf("** Error: flash address 0x%08llx..0x%08llx outside valid range %p..%p\n",
1240                                         (u64)addr, (u64)addr + len - 1, flash_info.start, flash_info.end);
1241                 return FLASH_ERR_INVALID;
1242         }
1243
1244         addr = nfc_l_to_p(addr);
1245         while (len > 0) {
1246                 int i;
1247
1248                 if (!flash_addr_valid(addr)) {
1249                         diag_printf("Too many bad blocks in flash region 0x%08llx..0x%08llx\n",
1250                                                 (u64)flash_region_start, (u64)flash_region_end);
1251                         return FLASH_ERR_INVALID;
1252                 }
1253                 if (chk_bad) {
1254                         int blk = OFFSET_TO_BLOCK(addr);
1255
1256                         if (nfc_is_badblock(blk, g_bbt)) {
1257                                 diag_printf("Skipping bad block %u at addr 0x%08llx\n", blk, (u64)addr);
1258                                 addr += NF_BLK_SZ;
1259                                 g_block_offset++;
1260                                 continue;
1261                         }
1262                         chk_bad = 0;
1263                 }
1264
1265                 pg_no = addr / NF_PG_SZ;
1266                 if (offset != 0) {
1267                         /* Find which interleaved NAND device */
1268                         start_point = offset / (NF_PG_SZ / num_of_nand_chips);
1269                 } else {
1270                         start_point = 0;
1271                 }
1272                 for (i = start_point; i < num_of_nand_chips; i++) {
1273                         int chunk_size = (NF_PG_SZ - offset) / num_of_nand_chips;
1274
1275                         if (chunk_size > len)
1276                                 chunk_size = len;
1277                         nfc_printf(NFC_DEBUG_MED, "Reading page %d addr 0x%08llx chip %d len 0x%03x\n",
1278                                            pg_no, (u64)addr, i, chunk_size);
1279                         if (nfc_read_page(i, pg_no, 0) != 0) {
1280                                 diag_printf("** Error: Failed to read flash block %u at addr 0x%08llx\n",
1281                                                         OFFSET_TO_BLOCK(addr), (u64)addr);
1282                                 return FLASH_ERR_INVALID;
1283                         }
1284                         // now do the copying
1285                         nfc_buf_read(buf, NAND_MAIN_BUF0 + offset, chunk_size);
1286
1287                         buf += chunk_size;
1288                         len -= chunk_size;
1289                         addr += NF_PG_SZ / num_of_nand_chips - offset;
1290                         offset = 0;
1291                 }
1292                 chk_bad = (addr % NF_BLK_SZ) == 0;
1293         }
1294
1295         return FLASH_ERR_OK;
1296 }
1297
1298 /*
1299  * Support only either program for main area only. Or spare-area only for 512B.
1300  * If one wants to write to the spare-area, then before calling this function,
1301  * the spare area NFC RAM buffer has to be setup already. This function doesn't touch
1302  * the spare area NFC RAM buffer.
1303  *
1304  * @param pg_no                 page number offset from 0
1305  * @param pg_off                byte offset within the page
1306  * @param buf                   data buffer in the RAM to be written to NAND flash
1307  * @param ecc_force             can force ecc to be off. Otherwise, by default it is on
1308  *                                              unless the page offset is non-zero
1309  *
1310  * @return      0 if successful; non-zero otherwise
1311  */
1312 // SP-only opearation is not supported anymore !!!
1313 static int nfc_write_pg_random(u32 pg_no, u32 pg_off, u8 *buf, u32 ecc_force)
1314 {
1315         u16 flash_status;
1316         u32 ecc = NFC_FLASH_CONFIG2_ECC_EN, v, i;
1317         u32 write_count = NF_PG_SZ, start_point = 0, rba, rba_count = 0;
1318
1319         // the 2nd condition is to test for unaligned page address -- ecc has to be off.
1320         if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
1321                 ecc = 0;
1322         }
1323
1324         diag_printf1("%s(0x%x, 0x%x, %d)\n", __FUNCTION__, pg_no, pg_off, ecc_force);
1325         if (g_nfc_version != MXC_NFC_V1) {
1326                 int i;
1327
1328                 for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
1329                         memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
1330                                 (void *)(NAND_SPAR_BUF0 + i * 16), 16);
1331                 }
1332         }
1333         if (g_nfc_version >= MXC_NFC_V3) {
1334                 /* Check if Page size is greater than NFC buffer */
1335                 do {
1336                         rba = nfc_reg_read(NAND_CONFIGURATION1_REG);
1337                         if ((rba >> 4) & 0x7) {
1338                                 nfc_reg_write(rba & ~0x70, NAND_CONFIGURATION1_REG);
1339                         }
1340                         if (write_count <= NFC_BUFSIZE) {
1341                                 // No need to worry about the spare area
1342                                 nfc_buf_write(NAND_MAIN_BUF0, buf, write_count);
1343                                 write_count = 0;
1344                         } else {
1345                                 // No need to worry about the spare area
1346                                 nfc_buf_write(NAND_MAIN_BUF0, buf, NFC_BUFSIZE);
1347                                 write_count -= NFC_BUFSIZE;
1348                                 buf += NFC_BUFSIZE;
1349                         }
1350                         // combine the two commands for program
1351                         nfc_reg_write((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
1352
1353                         for (i = start_point; i < num_of_nand_chips; i++) {
1354                                 rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
1355                                 /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
1356                                 if (rba > 7) {
1357                                         rba_count = 0;
1358                                         break;
1359                                 }
1360
1361                                 // For ECC
1362                                 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
1363                                 // setup config2 register for ECC enable or not
1364                                 write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
1365
1366                                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
1367
1368                                 // start auto-program
1369                                 nfc_reg_write(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
1370                                 if (i < (num_of_nand_chips - i))
1371                                         wait_for_auto_prog_done();
1372                                 else
1373                                         wait_op_done();
1374                                 pg_off = 0;
1375                                 rba_count++;
1376                                 rba = nfc_reg_read(NAND_CONFIGURATION1_REG);
1377                         }
1378                         flash_status = NFC_STATUS_READ();
1379                         // check I/O bit 0 to see if it is 0 for success
1380                         if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
1381                                 return -1;
1382                         }
1383                         start_point = i;
1384                 } while (write_count > 0);
1385         } else {
1386                 nfc_buf_write(NAND_MAIN_BUF0, buf, NF_PG_SZ);
1387 #ifdef BARKER_CODE_SWAP_LOC
1388                 // To replace the data at offset MXC_NAND_BOOT_LOAD_BARKER with
1389                 // the address of the NFC base. This is needed for certain platforms.
1390                 if (pg_no == 0) {
1391                         diag_printf("\n[INFO]: copy data at 0x%x to spare area and set it to 0x%x\n",
1392                                                 BARKER_CODE_SWAP_LOC, BARKER_CODE_VAL);
1393                         nfc_reg_write(nfc_reg_read(NFC_BASE + BARKER_CODE_SWAP_LOC), NAND_SPAR_BUF0);
1394                         // todo: set BARKER_CODE_VAL and BARKER_CODE_SWAP_LOC for skye, etc.
1395                         nfc_reg_write(BARKER_CODE_VAL, NFC_BASE + BARKER_CODE_SWAP_LOC);
1396                 }
1397 #endif
1398                 NFC_CMD_INPUT(FLASH_Send_Data);
1399                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
1400
1401                 NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
1402                 if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1403                         diag_printf("4K page with multi cycle write is not supported\n");
1404                         return -1;
1405                 }
1406                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1407                         NFC_DATA_INPUT_2k(RAM_BUF_1);
1408                         NFC_DATA_INPUT_2k(RAM_BUF_2);
1409                         NFC_DATA_INPUT_2k(RAM_BUF_3);
1410                 }
1411                 NFC_CMD_INPUT(FLASH_Program);
1412
1413                 flash_status = NFC_STATUS_READ();
1414                 // check I/O bit 0 to see if it is 0 for success
1415                 if ((flash_status & 0x1) != 0) {
1416                         diag_printf("** Error: failed to program page %u at 0x%08x status=0x%02x\n",
1417                                                 pg_no, pg_no * NF_PG_SZ + pg_off, flash_status);
1418                         return -1;
1419                 }
1420         }
1421         return 0;
1422 }
1423
1424 #ifdef NFC_V3_0
1425 /*
1426  * Do a page read at random address
1427  *
1428  * @param pg_no             page number offset from 0
1429  * @param pg_off             byte offset within the page
1430  * @param ecc_force        can force ecc to be off. Otherwise, by default it is on
1431  *                                    unless the page offset is non-zero
1432  * @param cs_line            indicates which NAND of interleaved NAND devices is used
1433  *
1434  * @return  0 if successful; non-zero otherwise
1435  */
1436 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line, u32 num_of_chips)
1437 {
1438         u32 ecc = NFC_FLASH_CONFIG2_ECC_EN;
1439         u32 v, res = 0;
1440         int i;
1441
1442         // clear the NAND_STATUS_SUM_REG register
1443         nfc_reg_write(0, NAND_STATUS_SUM_REG);
1444
1445         // the 2nd condition is to test for unaligned page address -- ecc has to be off.
1446         if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) {
1447                 ecc = 0;
1448         }
1449
1450         // Take care of config1 for RBA and SP_EN
1451         v = nfc_reg_read(NAND_CONFIGURATION1_REG) & ~0x71;
1452         nfc_reg_write(v, NAND_CONFIGURATION1_REG);
1453
1454         // For ECC
1455         v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
1456         // setup config2 register for ECC enable or not
1457         write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
1458
1459         start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, cs_line, num_of_chips);
1460
1461         if (g_is_2k_page || g_is_4k_page) {
1462                 // combine the two commands for 2k/4k page read
1463                 nfc_reg_write((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
1464         } else {
1465                 // just one command is enough for 512 page
1466                 nfc_reg_write(FLASH_Read_Mode1, NAND_CMD_REG);
1467         }
1468
1469         // start auto-read
1470         nfc_reg_write(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
1471         wait_op_done();
1472
1473         for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
1474                 memcpy((void *)(NAND_SPAR_BUF0 + i * 16),
1475                         (void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ), 16);
1476         }
1477         v = nfc_reg_read(NAND_STATUS_SUM_REG);
1478         // test for CS0 ECC error from the STATUS_SUM register
1479         if ((v & (0x0100 << cs_line)) != 0) {
1480                 // clear the status
1481                 nfc_reg_write(v & ~(0x0100 << cs_line), NAND_STATUS_SUM_REG);
1482                 diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%08lx) = 0x%08x\n",
1483                                         NAND_STATUS_SUM_REG, v);
1484                 diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%08lx) = 0x%08x\n", NAND_ECC_STATUS_RESULT_REG,
1485                                         nfc_reg_read(NAND_ECC_STATUS_RESULT_REG));
1486                 res = -1;
1487         }
1488         return res;
1489 }
1490 #else
1491 // for version V1 and V2 of NFC
1492 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line,
1493                                                           u32 num_of_nand_chips)
1494 {
1495         u32 t1, ecc = 1;
1496         u8 t2 = 0, t3 = 0, t4 = 0, t5 = 0, t6 = 0, t7 = 0, t8 = 0;
1497         int res = 0;
1498
1499         nfc_printf(NFC_DEBUG_MAX, "%s: reading page %u offset 0x%03x (addr 0x%08llx)\n",
1500                            __FUNCTION__, pg_no, pg_off, (flash_addr_t)pg_no * NF_PG_SZ + pg_off);
1501
1502         if (ecc_force == ECC_FORCE_OFF || pg_off != 0 )
1503                 ecc = 0;
1504
1505         NFC_CMD_INPUT(FLASH_Read_Mode1);
1506         start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, 0, num_of_nand_chips);
1507
1508         if (g_is_2k_page || g_is_4k_page) {
1509                 NFC_CMD_INPUT(FLASH_Read_Mode1_LG);
1510         }
1511
1512         NFC_DATA_OUTPUT(RAM_BUF_0, FDO_PAGE_SPARE, ecc);
1513         switch (g_nfc_version & 0xf0) {
1514         case MXC_NFC_V1:
1515                 t1 = readw(ECC_STATUS_RESULT_REG);
1516                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1517                         NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
1518                         t2 = readw(ECC_STATUS_RESULT_REG);
1519                         NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
1520                         t3 = readw(ECC_STATUS_RESULT_REG);
1521                         NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
1522                         t4 = readw(ECC_STATUS_RESULT_REG);
1523                 }
1524
1525                 if (ecc && ((t1 & 0xA) != 0x0 || (t2 & 0xA) != 0x0 ||
1526                                         (t3 & 0xA) != 0x0 || (t4 & 0xA) != 0x0)) {
1527                         diag_printf("\n** Error: ECC error page %u, col %u: ECC status=0x%x:0x%x:0x%x:0x%x\n",
1528                                                 pg_no, pg_off, t1, t2, t3, t4);
1529                         res = -1;
1530                         goto out;
1531                 }
1532                 break;
1533         case MXC_NFC_V2:
1534                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1535                         NFC_DATA_OUTPUT(RAM_BUF_1, FDO_PAGE_SPARE, ecc);
1536                         NFC_DATA_OUTPUT(RAM_BUF_2, FDO_PAGE_SPARE, ecc);
1537                         NFC_DATA_OUTPUT(RAM_BUF_3, FDO_PAGE_SPARE, ecc);
1538                 }
1539                 if (ecc) {
1540                         t1 = nfc_reg_read(ECC_STATUS_RESULT_REG);
1541                         if (g_is_2k_page || g_is_4k_page) {
1542                                 t2 = (t1 >> 4) & 0xF;
1543                                 t3 = (t1 >> 8) & 0xF;
1544                                 t4 = (t1 >> 12) & 0xF;
1545                                 if (g_is_4k_page) {
1546                                         t5 = (t1 >> 16) & 0xF;
1547                                         t6 = (t1 >> 20) & 0xF;
1548                                         t7 = (t1 >> 24) & 0xF;
1549                                         t8 = (t1 >> 28) & 0xF;
1550                                 }
1551                         }
1552                         if ((t1 = (t1 & 0xF)) > 4 || t2 > 4 || t3 > 4 || t4 > 4 ||
1553                                 t5 > 4 || t6 > 4 || t7 > 4 || t8 > 4) {
1554                                 diag_printf("\n** Error: ECC error reading block %u page %u\n",
1555                                                         pg_no / NF_PG_PER_BLK, pg_no % NF_PG_PER_BLK);
1556                                 diag_printf("   ECC status=%x:%x:%x:%x:%x:%x:%x:%x\n",
1557                                                         t1, t2, t3, t4, t5, t6, t7, t8);
1558                                 res = -1;
1559                                 goto out;
1560                         }
1561                 }
1562                 break;
1563         default:
1564                 diag_printf("Unknown NFC version: %d\n", g_nfc_version);
1565                 return -1;
1566         }
1567         if (g_nfc_version != MXC_NFC_V1) {
1568                 int i;
1569
1570                 for (i = 1; i < NFC_SPARE_BUF_SZ / 16; i++) {
1571                         memcpy((void *)(NAND_SPAR_BUF0 + i * 16),
1572                                    (void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ), 16);
1573                 }
1574         }
1575 #ifdef BARKER_CODE_SWAP_LOC
1576         // To replace the data at offset BARKER_CODE_SWAP_LOC with the address of the NFC base
1577         // This is needed for certain platforms
1578         if (pg_no == 0) {
1579                 diag_printf("\n[INFO]: copy back data from spare to 0x%x\n", BARKER_CODE_SWAP_LOC);
1580                 nfc_reg_write(nfc_reg_read(NAND_SPAR_BUF0), NFC_BASE + BARKER_CODE_SWAP_LOC);
1581         }
1582 #endif
1583
1584 out:
1585         return res;
1586 }
1587 #endif                  // ifndef NFC_V3_0
1588
1589 /*!
1590  * Read a page's both main and spare area from NAND flash to the internal RAM buffer.
1591  * It always reads data to the internal buffer 0.
1592  *
1593  * @param cs_line       which NAND device is used
1594  * @param pg_no    page number of the device
1595  * @param pg_off        offset within a page
1596  *
1597  * @return                              0 if no error or 1-bit error; -1 otherwise
1598  */
1599 static int nfc_read_page(u32 cs_line, u32 pg_no, u32 pg_off)
1600 {
1601         return nfc_read_pg_random(pg_no, pg_off, ECC_FORCE_ON, cs_line, num_of_nand_chips);
1602 }
1603
1604 static int nfc_write_page(u32 pg_no, u32 pg_off, u32 ecc_force)
1605 {
1606         u16 flash_status;
1607         u32 ecc = NFC_FLASH_CONFIG2_ECC_EN;
1608
1609         diag_printf1("Writing page %u addr 0x%08llx\n",
1610                                  pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
1611         if (ecc_force == ECC_FORCE_OFF || pg_off != 0) {
1612                 ecc = 0;
1613         }
1614
1615         if (g_nfc_version != MXC_NFC_V1) {
1616                 int i;
1617
1618                 for (i = NFC_SPARE_BUF_SZ / 16 - 1; i >= 0; i--) {
1619                         memcpy((void *)(NAND_SPAR_BUF0 + i * NFC_SPARE_BUF_SZ),
1620                                 (void *)(NAND_SPAR_BUF0 + i * 16), 16);
1621                 }
1622         }
1623         if (g_nfc_version == MXC_NFC_V3) {
1624                 int i;
1625                 u32 v;
1626                 u32 start_point = 0, rba, rba_count = 0;
1627
1628                 rba = nfc_reg_read(NAND_CONFIGURATION1_REG);
1629                 if ((rba >> 4) & 0x7) {
1630                         nfc_reg_write(rba & ~0x70, NAND_CONFIGURATION1_REG);
1631                 }
1632                 // combine the two commands for program
1633                 nfc_reg_write((FLASH_Program << 8) | FLASH_Send_Data, NAND_CMD_REG);
1634
1635                 for (i = start_point; i < num_of_nand_chips; i++) {
1636                         rba = rba_count * ((NF_PG_SZ / num_of_nand_chips) / 512);
1637                         /* Completely wrote out the NFC buffer, break and copy more to the NFC buffer */
1638                         if (rba > 7) {
1639                                 rba_count = 0;
1640                                 break;
1641                         }
1642
1643                         // For ECC
1644                         v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & ~NFC_FLASH_CONFIG2_ECC_EN;
1645                         // setup config2 register for ECC enable or not
1646                         write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
1647
1648                         start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, i, num_of_nand_chips);
1649
1650                         // start auto-program
1651                         nfc_reg_write(NAND_LAUNCH_AUTO_PROG, NAND_LAUNCH_REG);
1652                         if (i < (num_of_nand_chips - i))
1653                                 wait_for_auto_prog_done();
1654                         else
1655                                 wait_op_done();
1656                         pg_off = 0;
1657                         rba_count++;
1658                 }
1659                 flash_status = NFC_STATUS_READ();
1660                 // check I/O bit 0 to see if it is 0 for success
1661                 if ((flash_status & ((0x1 << num_of_nand_chips) - 1)) != 0) {
1662                         return -1;
1663                 }
1664                 rba = nfc_reg_read(NAND_CONFIGURATION1_REG);
1665                 start_point = i;
1666         } else {
1667                 NFC_CMD_INPUT(FLASH_Send_Data);
1668                 start_nfc_addr_ops(FLASH_Program, pg_no, pg_off, 0, 0, num_of_nand_chips);
1669
1670                 NFC_DATA_INPUT(RAM_BUF_0, NFC_MAIN_ONLY, ecc);
1671                 if (g_is_4k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1672                         diag_printf("4K page with multi cycle write is not supported\n");
1673                         return -1;
1674                 }
1675                 if (g_is_2k_page && PG_2K_DATA_OP_MULTI_CYCLES()) {
1676                         NFC_DATA_INPUT_2k(RAM_BUF_1);
1677                         NFC_DATA_INPUT_2k(RAM_BUF_2);
1678                         NFC_DATA_INPUT_2k(RAM_BUF_3);
1679                 }
1680                 NFC_CMD_INPUT(FLASH_Program);
1681
1682                 flash_status = NFC_STATUS_READ();
1683                 if ((flash_status & 0x1) != 0) {
1684                         diag_printf("** Error: failed to program page %u at addr 0x%08llx\n",
1685                                                 pg_no, (u64)pg_no * NF_PG_SZ + pg_off);
1686                         return -1;
1687                 }
1688         }
1689         return 0;
1690 }
1691
1692 // Read data into buffer
1693 #ifndef MXCFLASH_SELECT_MULTI
1694 int flash_read_buf(void *addr, void *data, int len)
1695 #else
1696 int nandflash_read_buf(void *addr, void *data, int len)
1697 #endif
1698 {
1699         flash_addr_t flash_addr = (unsigned long)addr;
1700         return nfc_read_region(flash_addr, data, len);
1701 }
1702
1703 void mxc_nfc_print_info(void)
1704 {
1705         diag_printf("[0x%08x bytes]: %u blocks of %u pages of %u bytes each.\n",
1706                                 NF_DEV_SZ, NF_BLK_CNT,
1707                                 NF_PG_PER_BLK, NF_PG_SZ);
1708 }
1709
1710 static int mxc_nfc_isbad_bbt(u16 *bbt, int block)
1711 {
1712         cyg_uint8 res;
1713
1714         block <<= 1;
1715         res = (get_byte(bbt, block >> 3) >> (block & 0x06)) & 0x03;
1716         res ^= 0x03;
1717         return res;
1718 }
1719
1720 static int mxc_nfc_search_bbt(struct nand_bbt_descr *td)
1721 {
1722         int i;
1723
1724         td->pages = -1;
1725         for (i = 0; i < NF_BBT_MAX_NR; i++) {
1726                 u32 blk = NF_BLK_CNT - i - 1;
1727                 flash_addr_t addr = blk * NF_BLK_SZ;
1728
1729                 if (nfc_read_pg_random(addr / NF_PG_SZ, addr % NF_PG_SZ,
1730                                                            ECC_FORCE_ON, 0, num_of_nand_chips) != 0) {
1731                         diag_printf("Failed to read bbt page %u at 0x%08llx\n",
1732                                                 (u32)(addr / NF_PG_SZ), addr);
1733                         continue;
1734                 }
1735                 if (check_short_pattern((void *)NAND_SPAR_BUF0, td) == 0) {
1736                         diag_printf1("found BBT at block %u addr %08llx\n", blk, (u64)addr);
1737                         td->pages = blk * NF_PG_PER_BLK;
1738                         td->version = get_byte((void *)NAND_SPAR_BUF0, td->veroffs);
1739                         mark_blk_bad(blk, g_bbt, BLK_RESERVED);
1740                         diag_printf1("Found version %d BBT at block %d (0x%08llx)\n",
1741                                                  td->version, td->pages / NF_PG_PER_BLK,
1742                                                  (u64)td->pages * NF_PG_SZ);
1743                         return 0;
1744                 }
1745         }
1746         return 1;
1747 }
1748
1749 /*
1750  * Look for the BBT depending on the passed-in lowlevel value.
1751  * @param       lowlevel        If true, then it does a low level scan based on factory
1752  *                                              marked BI(block info) field with ECC off to decide if a
1753  *                                              block is bad.
1754  *                                              If false, then it checks to see if an existing BBT in the
1755  *                                              flash or not. If not, then it returns -1. If yes, it will
1756  *                                              prints out the number of bad blocks.
1757  *
1758  * @return      number of bad blocks for the whole nand flash
1759  *
1760  * Note: For a brand new flash, this function has to be called with
1761  *               lowlevel=true.
1762  *
1763  *
1764  */
1765 static int mxc_nfc_scan(bool lowlevel)
1766 {
1767         u32 bad = 0, i;
1768         u32 count1 = 0, count2 = 0;
1769         u8 *buf = NULL;
1770         struct nand_bbt_descr *td = g_mxc_nfc_bbt_main_descr;
1771         struct nand_bbt_descr *md = g_mxc_nfc_bbt_mirror_descr;
1772
1773         nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
1774         mxc_nfc_scan_done = 0;
1775
1776         if (g_nfc_debug_measure) {
1777                 count1 = hal_timer_count();
1778         }
1779         // read out the last 4 blocks for marker
1780         // need to keep where is the td and md block number
1781         if (!lowlevel) {
1782                 struct nand_bbt_descr *bd;
1783
1784                 diag_printf1("Searching for BBT in the flash ...\n");
1785                 if (mxc_nfc_search_bbt(td) != 0) {
1786                         diag_printf("No main BBT found in flash\n");
1787                 }
1788                 if (md && mxc_nfc_search_bbt(md) != 0) {
1789                         diag_printf("No mirror BBT found in flash\n");
1790                 }
1791                 if (td->pages == -1 && (!md || md->pages == -1)) {
1792                         diag_printf("No BBT found. Need to do \"nand scan\" first\n");
1793                         return -1;
1794                 }
1795                 if (td->pages >= 0 && (md == NULL || md->version <= td->version)) {
1796                         bd = td;
1797                         nfc_printf(NFC_DEBUG_MIN, "Using normal bbt at page %d\n", bd->pages);
1798                 } else if (md != NULL && md->pages >= 0) {
1799                         bd = md;
1800                         nfc_printf(NFC_DEBUG_MIN, "Using mirror bbt at page %d\n", bd->pages);
1801                 } else {
1802                         diag_printf("** Error: Failed to read bbt from flash\n");
1803                         return -1;
1804                 }
1805                 nfc_read_page(0, bd->pages, 0);
1806                 for (i = 0; i < NF_BLK_CNT; i++) {
1807                         int res = mxc_nfc_isbad_bbt((u16 *)NAND_MAIN_BUF0, i);
1808                         if (res) {
1809                                 // construct the bad block table
1810                                 mark_blk_bad(i, g_bbt, res);
1811                                 bad++;
1812                         }
1813                 }
1814                 buf = g_bbt;
1815         } else {
1816                 diag_printf("Doing low level scan to construct BBT\n");
1817                 for (i = 0; i < NF_BLK_CNT; i++) {
1818                         int res = nfc_is_badblock(i, buf);
1819                         if (res) {
1820                                 // construct the bad block table
1821                                 if (!buf)
1822                                         mark_blk_bad(i, g_bbt, res);
1823                                 bad++;
1824                         }
1825                 }
1826         }
1827         diag_printf1("Total bad blocks: %d\n", bad);
1828         if (g_nfc_debug_measure) {
1829                 count2 = hal_timer_count();
1830                 diag_printf("counter1=0x%x, counter2=0x%x, diff=0x%x (%u usec)\n",
1831                                         count1, count2, count2 - count1,
1832                                         (count2 - count1) * 1000000 / 32768);
1833         }
1834         mxc_nfc_scan_done = 1;
1835         return bad;
1836 }
1837
1838 ////////////////////////// "nand" commands support /////////////////////////
1839 // Image management functions
1840 local_cmd_entry("info",
1841                                 "Show nand flash info (number of good/bad blocks)",
1842                                 "",
1843                                 nand_info,
1844                                 NAND_cmds
1845                    );
1846
1847 local_cmd_entry("show",
1848                                 "Show a page main/spare areas or spare area only (-s)",
1849                                 "-f <raw page address> | -b <block> [-s]",
1850                                 nand_show,
1851                                 NAND_cmds
1852                    );
1853
1854 local_cmd_entry("read",
1855                                 "Read data from nand flash into RAM",
1856                                 "-f <raw addr> -b <mem_load_addr> -l <byte len> [-c <col>]\n"
1857                                 "      Note -c is only for 2K-page for value <0, 2048+64-1>",
1858                                 nand_read,
1859                                 NAND_cmds
1860                    );
1861
1862 local_cmd_entry("write",
1863                                 "Write data from RAM into nand flash",
1864                                 "-f <raw address> -b <memory_address> -l <image_length> [-c <col_addr>]",
1865                                 nand_write,
1866                                 NAND_cmds
1867                    );
1868
1869 local_cmd_entry("erase",
1870                                 "Erase nand flash contents",
1871                                 "-f <raw address> -l <length> [-o]\n"
1872                                 "             -o: force erase (even for bad blocks)",
1873                                 nand_erase,
1874                                 NAND_cmds
1875                    );
1876
1877 local_cmd_entry("scan",
1878                                 "Scan bad blocks and may also save bad block table into the NAND flash.",
1879                                 "[-o] [-r]\n"
1880                                 "No argument: save existing bad block table (BBT)\n"
1881                                 "            -r: re-scan with ECC off and save BBT -- for brand NEW flash\n"
1882                                 "            -o: force erase all, reconstruct BBT (no ECC) and save BBT -- for development.",
1883                                 nand_scan,
1884                                 NAND_cmds
1885                    );
1886
1887 local_cmd_entry("debug",
1888                                 "Various NAND debug features ",
1889                                 "<0> no debug messages <default>\n"
1890                                 "             <1> min debug messages\n"
1891                                 "             <2> med debug messages\n"
1892                                 "             <3> max debug messages\n"
1893                                 "             <4> enable(default)/disable h/w ECC for both r/w\n"
1894                                 "             <5> disable(default)/enalbe spare-only read\n"
1895                                 "             <9> enable/disable measurement\n"
1896                                 "             no parameter - display current debug setup",
1897                                 nand_debug_fun,
1898                                 NAND_cmds
1899                                 );
1900
1901 local_cmd_entry("bad",
1902                                 "Mark bad block in BBT",
1903                                 "[-f <raw address>] [-b <block number>] [-c]\n"
1904                                 "           -c: clear bad block mark\n"
1905                                 "           -f and -b are mutually exclusive",
1906                                 nand_bad,
1907                                 NAND_cmds
1908                                 );
1909
1910 // Define table boundaries
1911 CYG_HAL_TABLE_BEGIN( __NAND_cmds_TAB__, NAND_cmds);
1912 CYG_HAL_TABLE_END( __NAND_cmds_TAB_END__, NAND_cmds);
1913
1914 extern struct cmd __NAND_cmds_TAB__[], __NAND_cmds_TAB_END__;
1915
1916 // CLI function
1917 static cmd_fun do_nand_cmds;
1918 RedBoot_nested_cmd("nand",
1919                    "Utility function to NAND flash using raw address",
1920                    "{cmds}",
1921                    do_nand_cmds,
1922                    __NAND_cmds_TAB__, &__NAND_cmds_TAB_END__
1923                   );
1924
1925 static void nand_usage(char *why)
1926 {
1927         diag_printf("*** invalid 'nand' command: %s\n", why);
1928         cmd_usage(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__, "nand ");
1929 }
1930
1931 static u32 curr_addr;
1932 static void nand_show(int argc, char *argv[])
1933 {
1934         u32 ra, block;
1935         bool flash_addr_set = false;
1936         bool block_set = false;
1937         bool spar_only = false;
1938         struct option_info opts[3];
1939
1940         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
1941                           &ra, &flash_addr_set, "NAND FLASH memory byte address");
1942         init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
1943                           &block, &block_set, "NAND FLASH memory block number");
1944         init_opts(&opts[2], 's', false, OPTION_ARG_TYPE_FLG,
1945                           &spar_only, NULL, "Spare only");
1946
1947         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
1948                 return;
1949         }
1950         if (flash_addr_set && block_set) {
1951                 nand_usage("options -f and -b are mutually exclusive");
1952                 return;
1953         } else if (flash_addr_set) {
1954                 curr_addr = ra;
1955         } else if (block_set) {
1956                 ra = BLOCK_TO_OFFSET(block) + (unsigned long)flash_info.start;
1957                 curr_addr = ra;
1958         } else {
1959                 ra = curr_addr;
1960                 curr_addr += NF_PG_SZ;
1961         }
1962
1963         if (ra % NF_PG_SZ) {
1964                 diag_printf("** Error: flash address must be page aligned\n");
1965                 return;
1966         }
1967
1968         ra &= MXC_NAND_ADDR_MASK;
1969         if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
1970                 diag_printf("This is a bad block\n");
1971         }
1972
1973         print_page(ra, spar_only);
1974 }
1975
1976 /*!
1977  * For low level nand read command. It doesn't check for bad block or not
1978  */
1979 static void nand_read(int argc, char *argv[])
1980 {
1981         int len;
1982         u32 mem_addr, ra, col, i, pg_no, pg_off;
1983         bool mem_addr_set = false;
1984         bool flash_addr_set = false;
1985         bool length_set = false;
1986         bool col_set = false;
1987         struct option_info opts[4];
1988         int j = 0;
1989         bool ecc_status = g_ecc_enable;
1990
1991         init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
1992                           &mem_addr, &mem_addr_set, "memory base address");
1993         init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
1994                           &ra, &flash_addr_set, "FLASH memory base address");
1995         init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
1996                           &len, &length_set, "image length [in FLASH]");
1997         init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
1998                           &col, &col_set, "column addr");
1999
2000         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2001                 nand_usage("invalid arguments");
2002                 return;
2003         }
2004
2005         if (ra % NF_PG_SZ) {
2006                 diag_printf("** Error: flash address must be page aligned\n");
2007                 return;
2008         }
2009
2010         if (!mem_addr_set || !flash_addr_set || !length_set) {
2011                 nand_usage("** Error: required parameter missing");
2012                 return;
2013         }
2014         if ((mem_addr < (CYG_ADDRESS)ram_start) ||
2015                 ((mem_addr+len) >= (CYG_ADDRESS)ram_end)) {
2016                 diag_printf("** WARNING: RAM address: 0x%08x may be invalid\n", mem_addr);
2017                 diag_printf("   valid range is 0x%p-0x%p\n", ram_start, ram_end);
2018         }
2019
2020         if (col_set) {
2021                 diag_printf("Random read at page %u, column 0x%04x\n",
2022                                         ra / NF_PG_SZ, col);
2023
2024                 if (g_is_2k_page || g_is_4k_page) {
2025                         g_ecc_enable = false;
2026                 }
2027                 nfc_read_pg_random(ra / NF_PG_SZ, col, ECC_FORCE_OFF, 0, num_of_nand_chips);
2028                 if (g_is_2k_page || g_is_4k_page) {
2029                         g_ecc_enable = ecc_status;
2030                 }
2031                 nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ);
2032                 return;
2033         }
2034
2035         // ensure integer multiple of page size
2036         len = (len + NF_PG_SZ - 1) & ~(NF_PG_SZ - 1);
2037         ra &= MXC_NAND_ADDR_MASK;
2038         do {
2039                 if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
2040                         diag_printf("\n** Error: flash address: 0x%08x out of range\n", ra);
2041                         return;
2042                 }
2043                 if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
2044                         diag_printf("\nSkipping bad block %u at addr=0x%08llx\n",
2045                                                 OFFSET_TO_BLOCK(ra), (u64)ra);
2046                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ;
2047                         continue;
2048                 }
2049                 pg_no = ra / NF_PG_SZ;
2050                 pg_off = ra % NF_PG_SZ;
2051                 for (i = 0; i < num_of_nand_chips; i++) {
2052                         if (nfc_read_page(i, pg_no, pg_off) != 0) {
2053                                 diag_printf("\n** Error: uncorrectable ECC at addr 0x%08x\n", ra);
2054                                 diag_printf("use 'nand bad -b %u' to mark this block in BBT\n",
2055                                                         pg_no / NF_PG_PER_BLK);
2056                         }
2057                         if ((j++ % 0x20) == 0)
2058                                 diag_printf("\n%s 0x%08x: ", __FUNCTION__, ra);
2059                         diag_printf(".");
2060
2061                         nfc_buf_read((void *)mem_addr, NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
2062
2063                         ra += NF_PG_SZ / num_of_nand_chips;
2064                         mem_addr += NF_PG_SZ / num_of_nand_chips;
2065                         len -= NF_PG_SZ / num_of_nand_chips;
2066                         pg_off = 0;
2067                 }
2068         } while (len > 0);
2069         diag_printf("\n");
2070 }
2071
2072 static void nand_write(int argc, char *argv[])
2073 {
2074         int len, len_st, j = 0;
2075         u32 mem_addr, mem_addr_st, ra, col;
2076         bool mem_addr_set = false;
2077         bool flash_addr_set = false;
2078         bool length_set = false;
2079         bool col_set = false;
2080         struct option_info opts[4];
2081         bool ecc_status = g_ecc_enable;
2082
2083         init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
2084                           &mem_addr, &mem_addr_set, "memory base address");
2085         init_opts(&opts[1], 'f', true, OPTION_ARG_TYPE_NUM,
2086                           &ra, &flash_addr_set, "FLASH memory base address");
2087         init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
2088                           &len, &length_set, "image length [in FLASH]");
2089         init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_NUM,
2090                           &col, &col_set, "column addr");
2091         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2092                 nand_usage("invalid arguments");
2093                 return;
2094         }
2095
2096         if (!mem_addr_set || !flash_addr_set || !length_set) {
2097                 nand_usage("required parameter missing");
2098                 return;
2099         }
2100
2101         if ((mem_addr < (CYG_ADDRESS)ram_start) ||
2102                 ((mem_addr + len) >= (CYG_ADDRESS)ram_end)) {
2103                 diag_printf("** WARNING: RAM address range: %p..%p may be invalid\n",
2104                                         (void *)mem_addr, (void *)(mem_addr + len));
2105                 diag_printf("   valid range is %p-%p\n", (void *)ram_start, (void *)ram_end);
2106         }
2107
2108         if (col_set) {
2109                 diag_printf("Random write at page %u, column %u\n", ra / NF_PG_SZ, col);
2110
2111                 if (g_is_2k_page || g_is_4k_page) {
2112                         g_ecc_enable = false;
2113                 }
2114                 nfc_write_pg_random(ra / NF_PG_SZ, col, (u8 *)mem_addr, 0);
2115                 if (g_is_2k_page || g_is_4k_page) {
2116                         g_ecc_enable = ecc_status;
2117                 }
2118                 return;
2119         }
2120
2121         if ((ra % NF_PG_SZ) != 0) {
2122                 diag_printf("** Error: flash address must be page aligned\n");
2123                 return;
2124         }
2125
2126         mem_addr_st = mem_addr;
2127         len_st = len;
2128         ra &= MXC_NAND_ADDR_MASK;
2129
2130         mxc_nfc_buf_clear(NAND_SPAR_BUF0, 0xff, NF_SPARE_SZ);
2131         do {
2132                 if (OFFSET_TO_BLOCK(ra) > (NF_BLK_CNT - 1)) {
2133                         diag_printf("\nFlash address 0x%08x out of range\n", ra);
2134                         return;
2135                 }
2136                 if (nfc_is_badblock(OFFSET_TO_BLOCK(ra), g_bbt)) {
2137                         diag_printf("\nSkipping bad block %u at addr=0x%08llx\n",
2138                                                 OFFSET_TO_BLOCK(ra), (u64)ra);
2139                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ;
2140                         continue;
2141                 }
2142
2143                 if ((ra % NF_BLK_SZ) == 0) {
2144                          mem_addr_st = mem_addr;
2145                          len_st = len;
2146                 }
2147                 if (nfc_write_pg_random(ra / NF_PG_SZ, ra % NF_PG_SZ, (u8 *)mem_addr, 0) != 0) {
2148                         if (g_nfc_debug_level >= NFC_DEBUG_DEF) {
2149                                 diag_printf("\nWarning %d: program error at addr 0x%x\n", __LINE__, ra);
2150                         }
2151                         mark_blk_bad(OFFSET_TO_BLOCK(ra), g_bbt, BLK_BAD_RUNTIME);
2152                         ra = (OFFSET_TO_BLOCK(ra) + 1) *  NF_BLK_SZ; //make sure block size aligned
2153                         mem_addr = mem_addr_st; // rewind to block boundary
2154                         len = len_st;
2155                         continue;
2156                 }
2157                 if ((j++ % 0x20) == 0)
2158                         diag_printf("\nProgramming 0x%08x: ", ra);
2159                 diag_printf(".");
2160
2161                 len -= NF_PG_SZ;
2162                 ra += NF_PG_SZ;
2163                 mem_addr += NF_PG_SZ;
2164         } while (len > 0);
2165         diag_printf("\n");
2166 }
2167
2168 void nand_debug_fun(int argc, char *argv[])
2169 {
2170         int opt;
2171         const char *dbg_lvl_str;
2172
2173         if (argc == 3) {
2174                 opt = argv[2][0] - '0';
2175                 switch (opt) {
2176                 case 0:
2177                         g_nfc_debug_level = NFC_DEBUG_NONE;
2178                         break;
2179                 case 1:
2180                         g_nfc_debug_level = NFC_DEBUG_MIN;
2181                         break;
2182                 case 2:
2183                         g_nfc_debug_level = NFC_DEBUG_MED;
2184                         break;
2185                 case 3:
2186                         g_nfc_debug_level = NFC_DEBUG_MAX;
2187                         break;
2188                 case 4:
2189                         g_ecc_enable = g_ecc_enable? false: true;
2190                         break;
2191                 case 5:
2192                         // toggle g_spare_only_read_ok
2193                         g_spare_only_read_ok = g_spare_only_read_ok? false: true;
2194                         break;
2195                 case 9:
2196                         g_nfc_debug_measure = g_nfc_debug_measure? false: true;
2197                         break;
2198
2199                 default:
2200                         diag_printf("%s(%s) not supported\n", __FUNCTION__, argv[2]);
2201                 }
2202         }
2203         switch (g_nfc_debug_level) {
2204         case NFC_DEBUG_NONE:
2205                 dbg_lvl_str = "none";
2206                 break;
2207         case NFC_DEBUG_MIN:
2208                 dbg_lvl_str = "min";
2209                 break;
2210         case NFC_DEBUG_MED:
2211                 dbg_lvl_str = "med";
2212                 break;
2213         case NFC_DEBUG_MAX:
2214                 dbg_lvl_str = "max";
2215                 break;
2216         default:
2217                 dbg_lvl_str = "invalid";
2218         }
2219         diag_printf("Current debug options are:\n");
2220         diag_printf("    h/w ECC: %s\n", g_ecc_enable ? "on" : "off");
2221         diag_printf("    sp-only read: %s\n", g_spare_only_read_ok ? "on" : "off");
2222         diag_printf("    measurement: %s\n", g_nfc_debug_measure ? "on" : "off");
2223         diag_printf("    message level: %s\n", dbg_lvl_str);
2224 }
2225
2226 static void nand_erase(int argc, char *argv[])
2227 {
2228         u32 len, ra;
2229         bool faddr_set = false;
2230         bool force_erase_set = false;
2231         bool length_set = false;
2232         struct option_info opts[4];
2233
2234         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
2235                   &ra, &faddr_set, "FLASH memory base address");
2236         init_opts(&opts[1], 'l', true, OPTION_ARG_TYPE_NUM,
2237                   &len, &length_set, "length in bytes");
2238         init_opts(&opts[2], 'o', false, OPTION_ARG_TYPE_FLG,
2239                   &force_erase_set, &force_erase_set, "force erases block");
2240
2241         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2242                 nand_usage("invalid arguments");
2243                 return;
2244         }
2245
2246         if (!faddr_set || !length_set) {
2247                 nand_usage("missing argument");
2248                 return;
2249         }
2250         if ((ra % NF_BLK_SZ) != 0) {
2251                 diag_printf("Address must be block aligned!\n");
2252                 diag_printf("Block size is 0x%x\n", NF_BLK_SZ);
2253                 return;
2254         }
2255         if ((len % NF_BLK_SZ) != 0) {
2256                 diag_printf("length must be block aligned!\n");
2257                 diag_printf("Block size is 0x%x\n", NF_BLK_SZ);
2258                 return;
2259         }
2260         if (len == 0) {
2261                 diag_printf("length must be > 0!\n");
2262                 return;
2263         }
2264
2265         if (!verify_action("About to erase 0x%08x bytes from nand offset 0x%08x", len, ra)) {
2266                 diag_printf("** Aborted\n");
2267                 return;
2268         }
2269
2270         diag_printf1("Enabling flash from %p..%p\n", (u8 *)ra, (u8 *)ra + len - 1);
2271         FLASH_Enable((u8 *)ra, (u8 *)ra + len);
2272         if (force_erase_set == true) {
2273                 diag_printf("Force erase ...");
2274                 nfc_erase_region(ra, len, 0, 1);
2275                 diag_printf("\n");
2276         } else {
2277                 nfc_erase_region(ra, len, 1, 1);
2278         }
2279         FLASH_Disable((u8 *)ra, (u8 *)ra + len);
2280         diag_printf("\n");
2281 }
2282
2283 extern void romupdate(int argc, char *argv[]);
2284 static void nand_scan(int argc, char *argv[])
2285 {
2286         bool force_erase = false;
2287         bool force_rescan = false;
2288         struct option_info opts[2];
2289
2290         init_opts(&opts[0], 'o', false, OPTION_ARG_TYPE_FLG,
2291                   &force_erase, NULL, "force erases block first");
2292
2293         init_opts(&opts[1], 'r', false, OPTION_ARG_TYPE_FLG,
2294                   &force_rescan, NULL, "force low level re-scan");
2295
2296         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2297                 nand_usage("invalid arguments");
2298                 return;
2299         }
2300
2301         if (!force_erase && !force_rescan && !mxc_nfc_scan_done) {
2302                 diag_printf("Need to build BBT first with \"nand scan [-o|-r]\"\n");
2303                 return;
2304         }
2305         if (force_erase) {
2306                 void *bbt = g_bbt;
2307
2308                 diag_printf("Force erase first ...\n");
2309                 g_bbt = NULL;
2310                 // do force erase, skipping bad blocks. After this call, g_bbt should be re-built
2311                 // for the whole NAND flash.
2312                 if (nfc_erase_region(0, NF_DEV_SZ, true, false) != 0) {
2313                         g_bbt = bbt;
2314                         return;
2315                 }
2316                 g_bbt = bbt;
2317                 mxc_nfc_scan_done = 0;
2318                 diag_printf("\n");
2319         }
2320         if (force_rescan) {
2321                 diag_printf("Force re-scan ...\n");
2322                 memset(g_bbt, 0, g_bbt_sz);
2323                 mxc_nfc_scan(true);
2324         }
2325         // program g_bbt into the flash
2326         diag_printf("Writing BBT to flash\n");
2327         if (program_bbt_to_flash() != 0) {
2328                 diag_printf("Error: Failed to write BBT to flash\n");
2329         }
2330         if (force_erase) {
2331                 romupdate(0, NULL);
2332         }
2333 }
2334
2335 static void nand_info(int argc, char *argv[])
2336 {
2337         u32 i, j = 0;
2338
2339         diag_printf("\nType:\t\t %s\n", NF_VEND_INFO);
2340         diag_printf("Total size:\t 0x%08x bytes (%d MiB)\n", NF_DEV_SZ, NF_DEV_SZ / SZ_1M);
2341         diag_printf("Total blocks:\t 0x%x (%d)\n", NF_BLK_CNT, NF_BLK_CNT);
2342         diag_printf("Block size:\t 0x%x (%d)\n", NF_BLK_SZ, NF_BLK_SZ);
2343         diag_printf("Page size:\t 0x%x (%d)\n", NF_PG_SZ, NF_PG_SZ);
2344         diag_printf("Spare size:\t 0x%x (%d)\n", NF_SPARE_SZ, NF_SPARE_SZ);
2345         diag_printf("Pages per block: 0x%x (%d)\n", NF_PG_PER_BLK, NF_PG_PER_BLK);
2346
2347         if (mxc_nfc_scan(false) == -1) {
2348                 return;
2349         }
2350         diag_printf("\n");
2351         for (i = 0; i < NF_BLK_CNT; i++) {
2352                 int res = nfc_is_badblock(i, g_bbt);
2353                 if (res & ~BLK_RESERVED) {
2354                         diag_printf("block %d at offset 0x%08x is a %s bad block\n",
2355                                                 i, i * NF_BLK_SZ, res == BLK_BAD_FACTORY ? "factory" : "runtime");
2356                         j++;
2357                 }
2358         }
2359         diag_printf("==================================\n");
2360         diag_printf("Found %d bad block(s) out of %d\n", j, i);
2361 }
2362
2363 static void nand_bad(int argc, char *argv[])
2364 {
2365         u32 ra;
2366         u32 block;
2367         bool ra_set = false;
2368         bool block_set = false;
2369         bool clear = false;
2370         struct option_info opts[3];
2371         int bad;
2372
2373         init_opts(&opts[0], 'f', true, OPTION_ARG_TYPE_NUM,
2374                           &ra, &ra_set, "FLASH memory base address");
2375         init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
2376                           &block, &block_set, "block number");
2377         init_opts(&opts[2], 'c', false, OPTION_ARG_TYPE_FLG,
2378                           &clear, NULL, "clear bad block marker");
2379
2380         if (!scan_opts(argc, argv, 2, opts, NUM_ELEMS(opts), NULL, 0, NULL)) {
2381                 nand_usage("invalid arguments");
2382                 return;
2383         }
2384
2385         if (!ra_set && !block_set) {
2386                 nand_usage("missing argument");
2387                 return;
2388         }
2389         if (ra_set && block_set) {
2390                 nand_usage("options -f and -b are mutually exclusive");
2391                 return;
2392         } else if (ra_set) {
2393                 block = OFFSET_TO_BLOCK(ra & MXC_NAND_ADDR_MASK);
2394         } else {
2395                 ra = BLOCK_TO_OFFSET(block) + (unsigned long)flash_info.start;
2396         }
2397         if ((ra % NF_BLK_SZ) != 0) {
2398                 diag_printf("Address is not block aligned!\n");
2399                 diag_printf("Block size is 0x%08x\n", NF_BLK_SZ);
2400                 return;
2401         }
2402
2403         bad = nfc_is_badblock(block, g_bbt);
2404         if ((bad && !clear) || (!bad && clear)) {
2405                 diag_printf("block %5u at address 0x%08x is already %s\n",
2406                                         block, ra, bad ? "bad" : "good");
2407                 return;
2408         }
2409         if (clear && bad != BLK_BAD_RUNTIME) {
2410                 diag_printf("Refusing to mark a factory bad block as good!\n");
2411                 return;
2412         }
2413         if (!verify_action("Mark block %u at address 0x%08x %s in BBT",
2414                                            block, ra, clear ? "good" : "bad")) {
2415                 diag_printf("** Aborted\n");
2416                 return;
2417         }
2418
2419         nfc_printf(NFC_DEBUG_MIN, "Marking block %5u at 0x%08x %s\n",
2420                            block, ra, clear ? "good" : "bad");
2421         mark_blk_bad(block, g_bbt, clear ? 0 : BLK_BAD_RUNTIME);
2422         mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr,
2423                                            g_mxc_nfc_bbt_mirror_descr);
2424 }
2425
2426 static void do_nand_cmds(int argc, char *argv[])
2427 {
2428         struct cmd *cmd;
2429
2430         if (!mxcnfc_init_ok) {
2431                 flash_hwr_init();
2432                 if (!mxcnfc_init_ok) {
2433 #ifdef CYGHWR_DEVS_FLASH_MXC_MULTI
2434                         diag_printf("Warning: NAND flash hasn't been initialized. Try \"factive nand\" first\n\n");
2435 #else
2436                         diag_printf("Error: NAND flash hasn't been initialized\n");
2437 #endif
2438                         return;
2439                 }
2440         }
2441
2442         if (argc < 2) {
2443                 nand_usage("too few arguments");
2444                 return;
2445         }
2446
2447         if ((cmd = cmd_search(__NAND_cmds_TAB__, &__NAND_cmds_TAB_END__,
2448                                                   argv[1])) != NULL) {
2449                 cmd->fun(argc, argv);
2450                 return;
2451         }
2452         nand_usage("unrecognized command");
2453 }
2454
2455 /*!
2456  * Display a memory region by 16-bit words
2457  * @param pkt   pointer to the starting address of the memory
2458  * @param len   byte length of the buffer to be displayed
2459  */
2460 static void print_pkt_16(u16 *pkt, u32 len)
2461 {
2462         diag_printf("******************** %d bytes********************\n", len);
2463         u32 i = 0, tempLen = (len + 1) / 2;
2464
2465         while (tempLen != 0) {
2466                 if (tempLen >= 8) {
2467                         diag_printf("[%03x-%03x] ", i * 2, (i * 2) + 14);
2468                         diag_printf("%04x %04x %04x %04x %04x %04x %04x %04x\n",
2469                                                 pkt[i], pkt[i + 1], pkt[i + 2], pkt[i + 3],
2470                                                 pkt[i + 4], pkt[i + 5], pkt[i + 6], pkt[i + 7]);
2471                         tempLen -= 8;
2472                         i += 8;
2473                 } else {
2474                         if (tempLen != 0) {
2475                                 diag_printf("[%03x-%03x]", i * 2, (i + tempLen) * 2);
2476                                 while (tempLen-- != 0) {
2477                                         diag_printf(" %04x", pkt[i++]);
2478                                 }
2479                                 diag_printf("\n");
2480                         }
2481                         diag_printf("*************************************************\n");
2482                         return;
2483                 }
2484         }
2485 }
2486
2487 // addr = starting byte address within NAND flash
2488 static void print_page(u32 addr, bool spare_only)
2489 {
2490         u32 i, pg_no, pg_off;
2491         u32 blk_num = OFFSET_TO_BLOCK(addr), pg_num = OFFSET_TO_PAGE(addr);
2492
2493         if (addr % NF_PG_SZ) {
2494                 diag_printf("Non page-aligned read not supported here: 0x%x\n", addr);
2495                 return;
2496         }
2497         pg_no = addr / NF_PG_SZ;
2498         pg_off = addr % NF_PG_SZ;
2499         for (i = 0; i < num_of_nand_chips; i++) {
2500                 if (nfc_read_page(i, pg_no, pg_off) != 0) {
2501                         diag_printf("Error %d: uncorrectable. But still printing ...\n", __LINE__);
2502                 }
2503                 pg_off = 0;
2504                 diag_printf("\n============ Printing block(%d) page(%d)  ==============\n",
2505                                         blk_num, pg_num);
2506
2507                 diag_printf("<<<<<<<<< spare area >>>>>>>>>\n");
2508                 print_pkt_16((u16*)NAND_SPAR_BUF0, NF_SPARE_SZ);
2509
2510                 if (!spare_only) {
2511                         diag_printf("<<<<<<<<< main area >>>>>>>>>\n");
2512                         print_pkt_16((u16*)NAND_MAIN_BUF0, NF_PG_SZ / num_of_nand_chips);
2513                 }
2514
2515                 diag_printf("\n");
2516         }
2517 }