2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
29 #ifndef CONFIG_SYS_CLK_FREQ_C210
30 #define CONFIG_SYS_CLK_FREQ_C210 24000000
33 /* s5pc210: return pll clock frequency */
34 static unsigned long s5pc210_get_pll_clk(int pllreg)
36 struct s5pc210_clock *clk =
37 (struct s5pc210_clock *)samsung_get_base_clock();
38 unsigned long r, m, p, s, k = 0, mask, fout;
43 r = readl(&clk->apll_con0);
46 r = readl(&clk->mpll_con0);
49 r = readl(&clk->epll_con0);
50 k = readl(&clk->epll_con1);
53 r = readl(&clk->vpll_con0);
54 k = readl(&clk->vpll_con1);
57 printf("Unsupported PLL (%d)\n", pllreg);
62 * APLL_CON: MIDV [25:16]
63 * MPLL_CON: MIDV [25:16]
64 * EPLL_CON: MIDV [24:16]
65 * VPLL_CON: MIDV [24:16]
67 if (pllreg == APLL || pllreg == MPLL)
79 freq = CONFIG_SYS_CLK_FREQ_C210;
83 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
84 fout = (m + k / 65536) * (freq / (p * (1 << s)));
85 } else if (pllreg == VPLL) {
87 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
88 fout = (m + k / 1024) * (freq / (p * (1 << s)));
92 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
93 fout = m * (freq / (p * (1 << (s - 1))));
99 /* s5pc210: return ARM clock frequency */
100 static unsigned long s5pc210_get_arm_clk(void)
102 struct s5pc210_clock *clk =
103 (struct s5pc210_clock *)samsung_get_base_clock();
105 unsigned long dout_apll;
106 unsigned int apll_ratio;
108 div = readl(&clk->div_cpu0);
110 /* APLL_RATIO: [26:24] */
111 apll_ratio = (div >> 24) & 0x7;
113 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
118 /* s5pc210: return pwm clock frequency */
119 static unsigned long s5pc210_get_pwm_clk(void)
121 struct s5pc210_clock *clk =
122 (struct s5pc210_clock *)samsung_get_base_clock();
123 unsigned long pclk, sclk;
131 sel = readl(&clk->src_peril0);
132 sel = (sel >> 24) & 0xf;
135 sclk = get_pll_clk(MPLL);
137 sclk = get_pll_clk(EPLL);
139 sclk = get_pll_clk(VPLL);
147 ratio = readl(&clk->div_peril3);
150 pclk = sclk / (ratio + 1);
155 /* s5pc210: return uart clock frequency */
156 static unsigned long s5pc210_get_uart_clk(int dev_index)
158 struct s5pc210_clock *clk =
159 (struct s5pc210_clock *)samsung_get_base_clock();
160 unsigned long uclk, sclk;
173 sel = readl(&clk->src_peril0);
174 sel = (sel >> (dev_index << 2)) & 0xf;
177 sclk = get_pll_clk(MPLL);
179 sclk = get_pll_clk(EPLL);
181 sclk = get_pll_clk(VPLL);
190 * UART3_RATIO [12:15]
191 * UART4_RATIO [16:19]
192 * UART5_RATIO [23:20]
194 ratio = readl(&clk->div_peril0);
195 ratio = (ratio >> (dev_index << 2)) & 0xf;
197 uclk = sclk / (ratio + 1);
202 unsigned long get_pll_clk(int pllreg)
204 return s5pc210_get_pll_clk(pllreg);
207 unsigned long get_arm_clk(void)
209 return s5pc210_get_arm_clk();
212 unsigned long get_pwm_clk(void)
214 return s5pc210_get_pwm_clk();
217 unsigned long get_uart_clk(int dev_index)
219 return s5pc210_get_uart_clk(dev_index);