arch/arm/cpu/armv7/socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/sdram.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define MAIN_VCO_BASE (                                 \
  23         (CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<             \
  24                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |   \
  25         (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<             \
  26                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)     \
  27         )
  28
  29 #define PERI_VCO_BASE (                                 \
  30         (CONFIG_HPS_PERPLLGRP_VCO_PSRC <<               \
  31                 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |     \
  32         (CONFIG_HPS_PERPLLGRP_VCO_DENOM <<              \
  33                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |    \
  34         (CONFIG_HPS_PERPLLGRP_VCO_NUMER <<              \
  35                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)      \
  36         )
  37
  38 #define SDR_VCO_BASE (                                  \
  39         (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<               \
  40                 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |     \
  41         (CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<              \
  42                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |    \
  43         (CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<              \
  44                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)      \
  45         )
  46
  47 u32 spl_boot_device(void)
  48 {
  49         return BOOT_DEVICE_RAM;
  50 }
  51
  52 /*
  53  * Board initialization after bss clearance
  54  */
  55 void spl_board_init(void)
  56 {
  57         unsigned long sdram_size;
  58 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  59         cm_config_t cm_default_cfg = {
  60                 /* main group */
  61                 MAIN_VCO_BASE,
  62                 (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  63                         CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  64                 (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  65                         CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  66                 (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  67                         CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  68                 (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  69                         CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  70                 (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
  71                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  72                 (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
  73                         CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
  74                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
  75                         CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
  76                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
  77                         CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
  78                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
  79                         CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
  80                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
  81                         CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
  82                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
  83                         CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
  84                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
  85                         CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
  86                 (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
  87                         CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
  88                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
  89                         CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
  90                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
  91                         CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
  92
  93                 /* peripheral group */
  94                 PERI_VCO_BASE,
  95                 (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
  96                         CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
  97                 (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
  98                         CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
  99                 (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
 100                         CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
 101                 (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
 102                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
 103                 (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
 104                         CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
 105                 (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
 106                         CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
 107                 (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
 108                         CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
 109                 (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
 110                         CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
 111                 (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
 112                         CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
 113                 (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
 114                         CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
 115                 (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
 116                         CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
 117                 (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
 118                         CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
 119                 (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
 120                         CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
 121                 (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
 122                         CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 123
 124                 /* sdram pll group */
 125                 SDR_VCO_BASE,
 126                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
 127                         CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
 128                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
 129                         CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
 130                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
 131                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
 132                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
 133                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
 134                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
 135                         CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
 136                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
 137                         CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
 138                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
 139                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
 140                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
 141                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 142
 143         };
 144
 145         debug("Freezing all I/O banks\n");
 146         /* freeze all IO banks */
 147         sys_mgr_frzctrl_freeze_req();
 148
 149         socfpga_sdram_enable();
 150         socfpga_uart0_enable();
 151         socfpga_osc1timer_enable();
 152
 153         timer_init();
 154
 155         debug("Reconfigure Clock Manager\n");
 156         /* reconfigure the PLLs */
 157         cm_basic_init(&cm_default_cfg);
 158
 159         /* Enable bootrom to configure IOs. */
 160         sysmgr_enable_warmrstcfgio();
 161
 162         /* configure the IOCSR / IO buffer settings */
 163         if (scan_mgr_configure_iocsr())
 164                 hang();
 165
 166         /* configure the pin muxing through system manager */
 167         sysmgr_pinmux_init();
 168 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 169
 170         /* de-assert reset for peripherals and bridges based on handoff */
 171         reset_deassert_peripherals_handoff();
 172
 173         debug("Unfreezing/Thaw all I/O banks\n");
 174         /* unfreeze / thaw all IO banks */
 175         sys_mgr_frzctrl_thaw_req();
 176
 177         /* enable console uart printing */
 178         preloader_console_init();
 179
 180         if (sdram_mmr_init_full(0xffffffff) != 0) {
 181                 puts("SDRAM init failed.\n");
 182                 hang();
 183         }
 184
 185         debug("SDRAM: Calibrating PHY\n");
 186         /* SDRAM calibration */
 187         if (sdram_calibration_full() == 0) {
 188                 puts("SDRAM calibration failed.\n");
 189                 hang();
 190         }
 191
 192         sdram_size = sdram_calculate_size();
 193         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 194 }