3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <ipu_pixfmt.h>
22 #ifdef CONFIG_FSL_ESDHC
23 #include <fsl_esdhc.h>
26 char *get_reset_cause(void)
29 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
31 cause = readl(&src_regs->srsr);
32 writel(cause, &src_regs->srsr);
51 return "unknown reset";
55 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
56 #if defined(CONFIG_MX53)
57 #define MEMCTL_BASE ESDCTL_BASE_ADDR
59 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
61 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
62 static const unsigned char bank_lookup[] = {3, 2};
64 /* these MMDC registers are common to the IMX53 and IMX6 */
65 struct esd_mmdc_regs {
75 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
76 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
77 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
78 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
79 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
82 * imx_ddr_size - return size in bytes of DRAM according MMDC config
83 * The MMDC MDCTL register holds the number of bits for row, col, and data
84 * width and the MMDC MDMISC register holds the number of banks. Combine
85 * all these bits to determine the meme size the MMDC has been configured for
87 unsigned imx_ddr_size(void)
89 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
90 unsigned ctl = readl(&mem->ctl);
91 unsigned misc = readl(&mem->misc);
92 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
94 bits += ESD_MMDC_CTL_GET_ROW(ctl);
95 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
96 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
97 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
98 bits += ESD_MMDC_CTL_GET_CS1(ctl);
100 /* The MX6 can do only 3840 MiB of DRAM */
108 #if defined(CONFIG_DISPLAY_CPUINFO)
110 const char *get_imx_type(u32 imxtype)
114 return "6Q"; /* Quad-core version of the mx6 */
116 return "6D"; /* Dual-core version of the mx6 */
118 return "6DL"; /* Dual Lite version of the mx6 */
119 case MXC_CPU_MX6SOLO:
120 return "6SOLO"; /* Solo version of the mx6 */
122 return "6SL"; /* Solo-Lite version of the mx6 */
124 return "6SX"; /* SoloX version of the mx6 */
134 int print_cpuinfo(void)
138 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
139 struct udevice *thermal_dev;
143 cpurev = get_cpu_rev();
145 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
146 get_imx_type((cpurev & 0xFF000) >> 12),
147 (cpurev & 0x000F0) >> 4,
148 (cpurev & 0x0000F) >> 0,
149 mxc_get_clock(MXC_ARM_CLK) / 1000000);
151 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
152 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
154 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
157 printf("CPU: Temperature %d C\n", cpu_tmp);
159 printf("CPU: Temperature: invalid sensor data\n");
161 printf("CPU: Temperature: Can't find sensor device\n");
165 printf("Reset cause: %s\n", get_reset_cause());
170 int cpu_eth_init(bd_t *bis)
174 #if defined(CONFIG_FEC_MXC)
175 rc = fecmxc_initialize(bis);
181 #ifdef CONFIG_FSL_ESDHC
183 * Initializes on-chip MMC controllers.
184 * to override, implement board_mmc_init()
186 int cpu_mmc_init(bd_t *bis)
188 return fsl_esdhc_mmc_init(bis);
192 u32 get_ahb_clk(void)
194 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
197 reg = __raw_readl(&imx_ccm->cbcdr);
198 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
199 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
201 return get_periph_clk() / (ahb_podf + 1);
204 #if defined(CONFIG_VIDEO_IPUV3)
205 void arch_preboot_os(void)
207 /* disable video before launching O/S */
212 void set_chipselect_size(int const cs_size)
215 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
216 reg = readl(&iomuxc_regs->gpr[1]);
220 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
223 case CS0_64M_CS1_64M:
224 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
227 case CS0_64M_CS1_32M_CS2_32M:
228 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
231 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
232 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
236 printf("Unknown chip select size: %d\n", cs_size);
240 writel(reg, &iomuxc_regs->gpr[1]);