arch/arm/mach-socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/nic301.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static struct pl310_regs *const pl310 =
  26         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  27 static struct scu_registers *scu_regs =
  28         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  29 static struct nic301_registers *nic301_regs =
  30         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  31
  32 u32 spl_boot_device(void)
  33 {
  34         return BOOT_DEVICE_RAM;
  35 }
  36
  37 static void socfpga_nic301_slave_ns(void)
  38 {
  39         writel(0x1, &nic301_regs->lwhps2fpgaregs);
  40         writel(0x1, &nic301_regs->hps2fpgaregs);
  41         writel(0x1, &nic301_regs->acp);
  42         writel(0x1, &nic301_regs->rom);
  43         writel(0x1, &nic301_regs->ocram);
  44         writel(0x1, &nic301_regs->sdrdata);
  45 }
  46
  47 void board_init_f(ulong dummy)
  48 {
  49 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  50         const struct cm_config *cm_default_cfg = cm_get_default_config();
  51 #endif
  52         struct socfpga_system_manager *sysmgr_regs =
  53                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  54         unsigned long sdram_size;
  55         unsigned long reg;
  56
  57         /*
  58          * First C code to run. Clear fake OCRAM ECC first as SBE
  59          * and DBE might triggered during power on
  60          */
  61         reg = readl(&sysmgr_regs->eccgrp_ocram);
  62         if (reg & SYSMGR_ECC_OCRAM_SERR)
  63                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  64                        &sysmgr_regs->eccgrp_ocram);
  65         if (reg & SYSMGR_ECC_OCRAM_DERR)
  66                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  67                        &sysmgr_regs->eccgrp_ocram);
  68
  69         memset(__bss_start, 0, __bss_end - __bss_start);
  70
  71         socfpga_nic301_slave_ns();
  72
  73         /* Configure ARM MPU SNSAC register. */
  74         setbits_le32(&scu_regs->sacr, 0xfff);
  75
  76         /* Remap SDRAM to 0x0 */
  77         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
  78         writel(0x1, &pl310->pl310_addr_filter_start);
  79
  80 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  81         debug("Freezing all I/O banks\n");
  82         /* freeze all IO banks */
  83         sys_mgr_frzctrl_freeze_req();
  84
  85         /* Put everything into reset but L4WD0. */
  86         socfpga_per_reset_all();
  87         /* Put FPGA bridges into reset too. */
  88         socfpga_bridges_reset(1);
  89
  90         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
  91         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  92         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  93
  94         timer_init();
  95
  96         debug("Reconfigure Clock Manager\n");
  97         /* reconfigure the PLLs */
  98         cm_basic_init(cm_default_cfg);
  99
 100         /* Enable bootrom to configure IOs. */
 101         sysmgr_config_warmrstcfgio(1);
 102
 103         /* configure the IOCSR / IO buffer settings */
 104         if (scan_mgr_configure_iocsr())
 105                 hang();
 106
 107         sysmgr_config_warmrstcfgio(0);
 108
 109         /* configure the pin muxing through system manager */
 110         sysmgr_config_warmrstcfgio(1);
 111         sysmgr_pinmux_init();
 112         sysmgr_config_warmrstcfgio(0);
 113
 114 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 115
 116         /* De-assert reset for peripherals and bridges based on handoff */
 117         reset_deassert_peripherals_handoff();
 118         socfpga_bridges_reset(0);
 119
 120         debug("Unfreezing/Thaw all I/O banks\n");
 121         /* unfreeze / thaw all IO banks */
 122         sys_mgr_frzctrl_thaw_req();
 123
 124         /* enable console uart printing */
 125         preloader_console_init();
 126
 127         if (sdram_mmr_init_full(0xffffffff) != 0) {
 128                 puts("SDRAM init failed.\n");
 129                 hang();
 130         }
 131
 132         debug("SDRAM: Calibrating PHY\n");
 133         /* SDRAM calibration */
 134         if (sdram_calibration_full() == 0) {
 135                 puts("SDRAM calibration failed.\n");
 136                 hang();
 137         }
 138
 139         sdram_size = sdram_calculate_size();
 140         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 141
 142         /* Sanity check ensure correct SDRAM size specified */
 143         if (get_ram_size(0, sdram_size) != sdram_size) {
 144                 puts("SDRAM size check failed!\n");
 145                 hang();
 146         }
 147
 148         socfpga_bridges_reset(1);
 149
 150         board_init_r(NULL, 0);
 151 }