board/esd/hh405/hh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/processor.h>
  29 #include <command.h>
  30 #include <malloc.h>
  31 #include <pci.h>
  32 #include <sm501.h>
  33
  34
  35 #ifdef CONFIG_VIDEO_SM501
  36
  37 #define SWAP32(x)        ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
  38                           (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
  39
  40 #ifdef CONFIG_VIDEO_SM501_8BPP
  41 #error CONFIG_VIDEO_SM501_8BPP not supported.
  42 #endif /* CONFIG_VIDEO_SM501_8BPP */
  43
  44 #ifdef CONFIG_VIDEO_SM501_16BPP
  45 #define BPP     16
  46
  47 /*
  48  * 800x600 display B084SN03: PCLK = 40MHz
  49  * => 2*PCLK = 80MHz
  50  * 336/4 = 84MHz
  51  * => PCLK = 84MHz
  52  */
  53 static const SMI_REGS init_regs_800x600 [] =
  54 {
  55 #if 1 /* test-only */
  56         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
  57 #else
  58         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
  59 #endif
  60         {0x00004, SWAP32(0x00000000)},
  61         /* clocks for pm1... */
  62         {0x00048, SWAP32(0x00021807)},
  63         {0x0004C, SWAP32(0x221a0a01)},
  64         {0x00054, SWAP32(0x00000001)},
  65         /* clocks for pm0... */
  66         {0x00040, SWAP32(0x00021807)},
  67         {0x00044, SWAP32(0x221a0a01)},
  68         {0x00054, SWAP32(0x00000000)},
  69         /* panel control regs... */
  70         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
  71         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
  72         {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
  73         {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
  74         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
  75         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
  76         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
  77         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
  78         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
  79         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
  80         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
  81         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
  82         {0x80200, SWAP32(0x00010000)}, /* crt display control */
  83         {0, 0}
  84 };
  85
  86 /*
  87  * 1024x768 display G150XG02: PCLK = 65MHz
  88  * => 2*PCLK = 130MHz
  89  * 288/2 = 144MHz
  90  * => PCLK = 72MHz
  91  */
  92 static const SMI_REGS init_regs_1024x768 [] =
  93 {
  94         {0x00004, SWAP32(0x00000000)},
  95         /* clocks for pm1... */
  96         {0x00048, SWAP32(0x00021807)},
  97         {0x0004C, SWAP32(0x011a0a01)},
  98         {0x00054, SWAP32(0x00000001)},
  99         /* clocks for pm0... */
 100         {0x00040, SWAP32(0x00021807)},
 101         {0x00044, SWAP32(0x011a0a01)},
 102         {0x00054, SWAP32(0x00000000)},
 103         /* panel control regs... */
 104         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
 105         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 106         {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
 107         {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
 108         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 109         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 110         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 111         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 112         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 113         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 114         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 115         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 116         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 117         {0, 0}
 118 };
 119
 120 #endif /* CONFIG_VIDEO_SM501_16BPP */
 121
 122 #ifdef CONFIG_VIDEO_SM501_32BPP
 123 #define BPP     32
 124
 125 /*
 126  * 800x600 display B084SN03: PCLK = 40MHz
 127  * => 2*PCLK = 80MHz
 128  * 336/4 = 84MHz
 129  * => PCLK = 84MHz
 130  */
 131 static const SMI_REGS init_regs_800x600 [] =
 132 {
 133 #if 0 /* test-only */
 134         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
 135 #else
 136         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
 137 #endif
 138         {0x00004, SWAP32(0x00000000)},
 139         /* clocks for pm1... */
 140         {0x00048, SWAP32(0x00021807)},
 141         {0x0004C, SWAP32(0x221a0a01)},
 142         {0x00054, SWAP32(0x00000001)},
 143         /* clocks for pm0... */
 144         {0x00040, SWAP32(0x00021807)},
 145         {0x00044, SWAP32(0x221a0a01)},
 146         {0x00054, SWAP32(0x00000000)},
 147         /* panel control regs... */
 148         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 149         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 150         {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
 151         {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
 152         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
 153         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
 154         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 155         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
 156         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
 157         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
 158         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
 159         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
 160         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 161         {0, 0}
 162 };
 163
 164 /*
 165  * 1024x768 display G150XG02: PCLK = 65MHz
 166  * => 2*PCLK = 130MHz
 167  * 288/2 = 144MHz
 168  * => PCLK = 72MHz
 169  */
 170 static const SMI_REGS init_regs_1024x768 [] =
 171 {
 172         {0x00004, SWAP32(0x00000000)},
 173         /* clocks for pm1... */
 174         {0x00048, SWAP32(0x00021807)},
 175         {0x0004C, SWAP32(0x011a0a01)},
 176         {0x00054, SWAP32(0x00000001)},
 177         /* clocks for pm0... */
 178         {0x00040, SWAP32(0x00021807)},
 179         {0x00044, SWAP32(0x011a0a01)},
 180         {0x00054, SWAP32(0x00000000)},
 181         /* panel control regs... */
 182         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 183         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 184         {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
 185         {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
 186         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 187         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 188         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 189         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 190         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 191         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 192         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 193         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 194         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 195         {0, 0}
 196 };
 197
 198 #endif /* CONFIG_VIDEO_SM501_32BPP */
 199
 200 #endif /* CONFIG_VIDEO_SM501 */
 201
 202 #if 0
 203 #define FPGA_DEBUG
 204 #endif
 205
 206 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 207 extern void lxt971_no_sleep(void);
 208
 209 /* fpga configuration data - gzip compressed and generated by bin2c */
 210 const unsigned char fpgadata[] =
 211 {
 212 #include "fpgadata.c"
 213 };
 214
 215 /*
 216  * include common fpga code (for esd boards)
 217  */
 218 #include "../common/fpga.c"
 219
 220
 221 /* Prototypes */
 222 int gunzip(void *, int, unsigned char *, unsigned long *);
 223
 224
 225 /* logo bitmap data - gzip compressed and generated by bin2c */
 226 unsigned char logo_bmp_320[] =
 227 {
 228 #include "logo_320_240_4bpp.c"
 229 };
 230
 231 unsigned char logo_bmp_320_8bpp[] =
 232 {
 233 #include "logo_320_240_8bpp.c"
 234 };
 235
 236 unsigned char logo_bmp_640[] =
 237 {
 238 #include "logo_640_480_24bpp.c"
 239 };
 240
 241 unsigned char logo_bmp_1024[] =
 242 {
 243 #include "logo_1024_768_8bpp.c"
 244 };
 245
 246
 247 /*
 248  * include common lcd code (for esd boards)
 249  */
 250 #include "../common/lcd.c"
 251
 252 #include "../common/s1d13704_320_240_4bpp.h"
 253 #include "../common/s1d13705_320_240_8bpp.h"
 254 #include "../common/s1d13806_640_480_16bpp.h"
 255 #include "../common/s1d13806_1024_768_8bpp.h"
 256
 257
 258 /*
 259  * include common auto-update code (for esd boards)
 260  */
 261 #include "../common/auto_update.h"
 262
 263 au_image_t au_image[] = {
 264         {"hh405/preinst.img", 0, -1, AU_SCRIPT},
 265         {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
 266         {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
 267         {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
 268         {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
 269         {"hh405/postinst.img", 0, 0, AU_SCRIPT},
 270 };
 271
 272 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 273
 274
 275 int board_revision(void)
 276 {
 277         unsigned long osrh_reg;
 278         unsigned long isr1h_reg;
 279         unsigned long tcr_reg;
 280         unsigned long value;
 281
 282         /*
 283          * Get version of HH405 board from GPIO's
 284          */
 285
 286         /*
 287          * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
 288          */
 289         osrh_reg = in32(GPIO0_OSRH);
 290         isr1h_reg = in32(GPIO0_ISR1H);
 291         tcr_reg = in32(GPIO0_TCR);
 292         out32(GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
 293         out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
 294         out32(GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
 295
 296         udelay(1000);            /* wait some time before reading input */
 297         value = in32(GPIO0_IR) & 0x80400000;         /* get config bits */
 298
 299         /*
 300          * Restore GPIO settings
 301          */
 302         out32(GPIO0_OSRH, osrh_reg);                   /* output select */
 303         out32(GPIO0_ISR1H, isr1h_reg);                 /* input select  */
 304         out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
 305
 306         if (value & 0x80000000) {
 307                 /* Revision 1.0 or 1.1 detected */
 308                 return 0x0101;
 309         } else {
 310                 if (value & 0x00400000) {
 311                         /* unused */
 312                         return 0x0103;
 313                 } else {
 314                         /* Revision >= 2.0 detected */
 315                         /* rev. 2.x uses four SM501 GPIOs for revision coding */
 316                         return 0x0200;
 317                 }
 318         }
 319 }
 320
 321
 322 int board_early_init_f (void)
 323 {
 324         /*
 325          * IRQ 0-15  405GP internally generated; active high; level sensitive
 326          * IRQ 16    405GP internally generated; active low; level sensitive
 327          * IRQ 17-24 RESERVED
 328          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 329          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 330          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 331          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 332          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 333          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 334          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 335          */
 336         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 337         mtdcr(uicer, 0x00000000);       /* disable all ints */
 338         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 339         mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
 340         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 341         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 342         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 343
 344         /*
 345          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 346          */
 347         mtebc (epcr, 0xa8400000); /* ebc always driven */
 348
 349         return 0;
 350 }
 351
 352
 353 int misc_init_r (void)
 354 {
 355         DECLARE_GLOBAL_DATA_PTR;
 356
 357         volatile unsigned short *fpga_ctrl =
 358                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 359         volatile unsigned short *lcd_contrast =
 360                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
 361         volatile unsigned short *lcd_backlight =
 362                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
 363         unsigned char *dst;
 364         ulong len = sizeof(fpgadata);
 365         int status;
 366         int index;
 367         int i;
 368         char *str;
 369         unsigned long contrast0 = 0xffffffff;
 370
 371         dst = malloc(CFG_FPGA_MAX_SIZE);
 372         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 373                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 374                 do_reset (NULL, 0, 0, NULL);
 375         }
 376
 377         status = fpga_boot(dst, len);
 378         if (status != 0) {
 379                 printf("\nFPGA: Booting failed ");
 380                 switch (status) {
 381                 case ERROR_FPGA_PRG_INIT_LOW:
 382                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 383                         break;
 384                 case ERROR_FPGA_PRG_INIT_HIGH:
 385                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 386                         break;
 387                 case ERROR_FPGA_PRG_DONE:
 388                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 389                         break;
 390                 }
 391
 392                 /* display infos on fpgaimage */
 393                 index = 15;
 394                 for (i=0; i<4; i++) {
 395                         len = dst[index];
 396                         printf("FPGA: %s\n", &(dst[index+1]));
 397                         index += len+3;
 398                 }
 399                 putc ('\n');
 400                 /* delayed reboot */
 401                 for (i=20; i>0; i--) {
 402                         printf("Rebooting in %2d seconds \r",i);
 403                         for (index=0;index<1000;index++)
 404                                 udelay(1000);
 405                 }
 406                 putc ('\n');
 407                 do_reset(NULL, 0, 0, NULL);
 408         }
 409
 410         puts("FPGA:  ");
 411
 412         /* display infos on fpgaimage */
 413         index = 15;
 414         for (i=0; i<4; i++) {
 415                 len = dst[index];
 416                 printf("%s ", &(dst[index+1]));
 417                 index += len+3;
 418         }
 419         putc ('\n');
 420
 421         free(dst);
 422
 423         /*
 424          * Reset FPGA via FPGA_INIT pin
 425          */
 426         out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 427         out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 428         udelay(1000); /* wait 1ms */
 429         out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT);   /* reset high */
 430         udelay(1000); /* wait 1ms */
 431
 432         /*
 433          * Write Board revision into FPGA
 434          */
 435         *fpga_ctrl |= gd->board_type & 0x0003;
 436         if (gd->board_type >= 0x0200) {
 437                 *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
 438         }
 439
 440         /*
 441          * Setup and enable EEPROM write protection
 442          */
 443         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 444
 445         /*
 446          * Set NAND-FLASH GPIO signals to default
 447          */
 448         out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
 449         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
 450
 451         /*
 452          * Reset touch-screen controller
 453          */
 454         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
 455         udelay(1000);
 456         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
 457
 458         /*
 459          * Enable power on PS/2 interface (with reset)
 460          */
 461         *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
 462         for (i=0;i<500;i++)
 463                 udelay(1000);
 464         *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
 465
 466         /*
 467          * Get contrast value from environment variable
 468          */
 469         str = getenv("contrast0");
 470         if (str) {
 471                 contrast0 = simple_strtol(str, NULL, 16);
 472                 if (contrast0 > 255) {
 473                         printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
 474                         contrast0 = 0;
 475                 }
 476         }
 477
 478         /*
 479          * Init lcd interface and display logo
 480          */
 481
 482         str = getenv("bd_type");
 483         if (strcmp(str, "ppc230") == 0) {
 484                 /*
 485                  * Switch backlight on
 486                  */
 487                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
 488                 *lcd_backlight = 0x0000;
 489
 490                 lcd_setup(1, 0);
 491                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 492                          regs_13806_1024_768_8bpp,
 493                          sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
 494                          logo_bmp_1024, sizeof(logo_bmp_1024));
 495         } else if (strcmp(str, "ppc220") == 0) {
 496                 /*
 497                  * Switch backlight on
 498                  */
 499                 *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
 500                 *lcd_backlight = 0x0000;
 501
 502                 lcd_setup(1, 0);
 503                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 504                          regs_13806_640_480_16bpp,
 505                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 506                          logo_bmp_640, sizeof(logo_bmp_640));
 507         } else if (strcmp(str, "ppc215") == 0) {
 508                 /*
 509                  * Set default display contrast voltage
 510                  */
 511                 if (contrast0 == 0xffffffff) {
 512                         *lcd_contrast = 0x0082;
 513                 } else {
 514                         *lcd_contrast = contrast0;
 515                 }
 516                 *lcd_backlight = 0xffff;
 517                 /*
 518                  * Switch backlight on
 519                  */
 520                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
 521                 /*
 522                  * Set lcd clock (small epson)
 523                  */
 524                 *fpga_ctrl |= LCD_CLK_06250;
 525                 udelay(100);               /* wait for 100 us */
 526
 527                 lcd_setup(0, 1);
 528                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 529                          regs_13705_320_240_8bpp,
 530                          sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
 531                          logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
 532         } else if (strcmp(str, "ppc210") == 0) {
 533                 /*
 534                  * Set default display contrast voltage
 535                  */
 536                 if (contrast0 == 0xffffffff) {
 537                         *lcd_contrast = 0x0060;
 538                 } else {
 539                         *lcd_contrast = contrast0;
 540                 }
 541                 *lcd_backlight = 0xffff;
 542                 /*
 543                  * Switch backlight on
 544                  */
 545                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
 546                 /*
 547                  * Set lcd clock (small epson)
 548                  */
 549                 *fpga_ctrl |= LCD_CLK_08330;
 550
 551                 lcd_setup(0, 1);
 552                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 553                          regs_13704_320_240_4bpp,
 554                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 555                          logo_bmp_320, sizeof(logo_bmp_320));
 556 #ifdef CONFIG_VIDEO_SM501
 557         } else {
 558                 pci_dev_t devbusfn;
 559
 560                 /*
 561                  * Is SM501 connected (ppc221/ppc231)?
 562                  */
 563                 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 564                 if (devbusfn != -1) {
 565                         puts("VGA:   SM501 with 8 MB ");
 566                         if (strcmp(str, "ppc221") == 0) {
 567                                 printf("(800*600, %dbpp)\n", BPP);
 568                         } else if (strcmp(str, "ppc231") == 0) {
 569                                 printf("(1024*768, %dbpp)\n", BPP);
 570                         } else {
 571                                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 572                                 return 0;
 573                         }
 574                 } else {
 575                         printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 576                         return 0;
 577                 }
 578 #endif /* CONFIG_VIDEO_SM501 */
 579         }
 580
 581         return (0);
 582 }
 583
 584
 585 /*
 586  * Check Board Identity:
 587  */
 588
 589 int checkboard (void)
 590 {
 591         DECLARE_GLOBAL_DATA_PTR;
 592
 593         char str[64];
 594         int i = getenv_r ("serial#", str, sizeof(str));
 595
 596         puts ("Board: ");
 597
 598         if (i == -1) {
 599                 puts ("### No HW ID - assuming HH405");
 600         } else {
 601                 puts(str);
 602         }
 603
 604         if (getenv_r("bd_type", str, sizeof(str)) != -1) {
 605                 printf(" (%s", str);
 606         } else {
 607                 puts(" (Missing bd_type!");
 608         }
 609
 610         gd->board_type = board_revision();
 611         printf(", Rev %ld.%ld)\n",
 612                (gd->board_type >> 8) & 0xff,
 613                gd->board_type & 0xff);
 614
 615         /*
 616          * Disable sleep mode in LXT971
 617          */
 618         lxt971_no_sleep();
 619
 620         return 0;
 621 }
 622
 623
 624 long int initdram (int board_type)
 625 {
 626         unsigned long val;
 627
 628         mtdcr(memcfga, mem_mb0cf);
 629         val = mfdcr(memcfgd);
 630
 631 #if 0
 632         printf("\nmb0cf=%x\n", val); /* test-only */
 633         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 634 #endif
 635
 636         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 637 }
 638
 639
 640 int testdram (void)
 641 {
 642         /* TODO: XXX XXX XXX */
 643         printf ("test: 16 MB - ok\n");
 644
 645         return (0);
 646 }
 647
 648
 649 #ifdef CONFIG_IDE_RESET
 650 void ide_set_reset(int on)
 651 {
 652         volatile unsigned short *fpga_mode =
 653                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 654
 655         /*
 656          * Assert or deassert CompactFlash Reset Pin
 657          */
 658         if (on) {               /* assert RESET */
 659                 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
 660         } else {                /* release RESET */
 661                 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
 662         }
 663 }
 664 #endif /* CONFIG_IDE_RESET */
 665
 666
 667 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 668 #include <linux/mtd/nand.h>
 669 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 670
 671 void nand_init(void)
 672 {
 673         nand_probe(CFG_NAND_BASE);
 674         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 675                 print_size(nand_dev_desc[0].totlen, "\n");
 676         }
 677 }
 678 #endif
 679
 680
 681 #if defined(CFG_EEPROM_WREN)
 682 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 683  *         <state>     -1: deliver current state
 684  *                     0: disable write
 685  *                     1: enable write
 686  *  Returns:           -1: wrong device address
 687  *                      0: dis-/en- able done
 688  *                   0/1: current state if <state> was -1.
 689  */
 690 int eeprom_write_enable (unsigned dev_addr, int state)
 691 {
 692         if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 693                 return -1;
 694         } else {
 695                 switch (state) {
 696                 case 1:
 697                         /* Enable write access, clear bit GPIO_SINT2. */
 698                         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
 699                         state = 0;
 700                         break;
 701                 case 0:
 702                         /* Disable write access, set bit GPIO_SINT2. */
 703                         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 704                         state = 0;
 705                         break;
 706                 default:
 707                         /* Read current status back. */
 708                         state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
 709                         break;
 710                 }
 711         }
 712         return state;
 713 }
 714
 715 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 716 {
 717         int query = argc == 1;
 718         int state = 0;
 719
 720         if (query) {
 721                 /* Query write access state. */
 722                 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 723                 if (state < 0) {
 724                         puts ("Query of write access state failed.\n");
 725                 } else {
 726                         printf ("Write access for device 0x%0x is %sabled.\n",
 727                                 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 728                         state = 0;
 729                 }
 730         } else {
 731                 if ('0' == argv[1][0]) {
 732                         /* Disable write access. */
 733                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
 734                 } else {
 735                         /* Enable write access. */
 736                         state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 737                 }
 738                 if (state < 0) {
 739                         puts ("Setup of write access state failed.\n");
 740                 }
 741         }
 742
 743         return state;
 744 }
 745
 746 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 747            "eepwren - Enable / disable / query EEPROM write access\n",
 748            NULL);
 749 #endif /* #if defined(CFG_EEPROM_WREN) */
 750
 751
 752 #ifdef CONFIG_VIDEO_SM501
 753 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 754 /*
 755  * Return text to be printed besides the logo.
 756  */
 757 void video_get_info_str (int line_number, char *info)
 758 {
 759         DECLARE_GLOBAL_DATA_PTR;
 760
 761         char str[64];
 762         char str2[64];
 763         int i = getenv_r("serial#", str2, sizeof(str));
 764
 765         if (line_number == 1) {
 766                 sprintf(str, " Board: ");
 767
 768                 if (i == -1) {
 769                         strcat(str, "### No HW ID - assuming HH405");
 770                 } else {
 771                         strcat(str, str2);
 772                 }
 773
 774                 if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
 775                         strcat(str, " (");
 776                         strcat(str, str2);
 777                 } else {
 778                         strcat(str, " (Missing bd_type!");
 779                 }
 780
 781                 sprintf(str2, ", Rev %ld.%ld)",
 782                        (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
 783                 strcat(str, str2);
 784                 strcpy(info, str);
 785         } else {
 786                 info [0] = '\0';
 787         }
 788 }
 789 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
 790
 791 /*
 792  * Returns SM501 register base address. First thing called in the driver.
 793  */
 794 unsigned int board_video_init (void)
 795 {
 796         pci_dev_t devbusfn;
 797         u32 addr;
 798
 799         /*
 800          * Is SM501 connected (ppc221/ppc231)?
 801          */
 802         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 803         if (devbusfn != -1) {
 804                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
 805                 return (addr & 0xfffffffe);
 806         }
 807
 808         return 0;
 809 }
 810
 811 /*
 812  * Returns SM501 framebuffer address
 813  */
 814 unsigned int board_video_get_fb (void)
 815 {
 816         pci_dev_t devbusfn;
 817         u32 addr;
 818
 819         /*
 820          * Is SM501 connected (ppc221/ppc231)?
 821          */
 822         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 823         if (devbusfn != -1) {
 824                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
 825                 return (addr & 0xfffffffe);
 826         }
 827
 828         return 0;
 829 }
 830
 831 /*
 832  * Called after initializing the SM501 and before clearing the screen.
 833  */
 834 void board_validate_screen (unsigned int base)
 835 {
 836 }
 837
 838 /*
 839  * Return a pointer to the initialization sequence.
 840  */
 841 const SMI_REGS *board_get_regs (void)
 842 {
 843         char *str;
 844
 845         str = getenv("bd_type");
 846         if (strcmp(str, "ppc221") == 0) {
 847                 return init_regs_800x600;
 848         } else {
 849                 return init_regs_1024x768;
 850         }
 851 }
 852
 853 int board_get_width (void)
 854 {
 855         char *str;
 856
 857         str = getenv("bd_type");
 858         if (strcmp(str, "ppc221") == 0) {
 859                 return 800;
 860         } else {
 861                 return 1024;
 862         }
 863 }
 864
 865 int board_get_height (void)
 866 {
 867         char *str;
 868
 869         str = getenv("bd_type");
 870         if (strcmp(str, "ppc221") == 0) {
 871                 return 600;
 872         } else {
 873                 return 768;
 874         }
 875 }
 876
 877 #endif /* CONFIG_VIDEO_SM501 */