board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/immap_fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  42 extern void ddr_enable_ecc(unsigned int dram_size);
  43 #endif
  44
  45 long int fixed_sdram(void);
  46
  47 int checkboard (void)
  48 {
  49         printf ("Board: MPC8572DS, System ID: 0x%02x, "
  50                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  51                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  52                 in8(PIXIS_BASE + PIXIS_PVER));
  53         return 0;
  54 }
  55
  56 phys_size_t initdram(int board_type)
  57 {
  58         phys_size_t dram_size = 0;
  59
  60         puts("Initializing....");
  61
  62 #ifdef CONFIG_SPD_EEPROM
  63         dram_size = fsl_ddr_sdram();
  64
  65         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  66
  67         dram_size *= 0x100000;
  68 #else
  69         dram_size = fixed_sdram();
  70 #endif
  71
  72 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  73         /*
  74          * Initialize and enable DDR ECC.
  75          */
  76         ddr_enable_ecc(dram_size);
  77 #endif
  78         puts("    DDR: ");
  79         return dram_size;
  80 }
  81
  82 #if !defined(CONFIG_SPD_EEPROM)
  83 /*
  84  * Fixed sdram init -- doesn't use serial presence detect.
  85  */
  86
  87 phys_size_t fixed_sdram (void)
  88 {
  89         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  90         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  91         uint d_init;
  92
  93         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  94         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  95
  96         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  97         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  98         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  99         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 100         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 101         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 102         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 103         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 104         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 105         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 106
 107 #if defined (CONFIG_DDR_ECC)
 108         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 109         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 110         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 111 #endif
 112         asm("sync;isync");
 113
 114         udelay(500);
 115
 116         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 117
 118 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 119         d_init = 1;
 120         debug("DDR - 1st controller: memory initializing\n");
 121         /*
 122          * Poll until memory is initialized.
 123          * 512 Meg at 400 might hit this 200 times or so.
 124          */
 125         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 126                 udelay(1000);
 127         }
 128         debug("DDR: memory initialized\n\n");
 129         asm("sync; isync");
 130         udelay(500);
 131 #endif
 132
 133         return 512 * 1024 * 1024;
 134 }
 135
 136 #endif
 137
 138 #ifdef CONFIG_PCIE1
 139 static struct pci_controller pcie1_hose;
 140 #endif
 141
 142 #ifdef CONFIG_PCIE2
 143 static struct pci_controller pcie2_hose;
 144 #endif
 145
 146 #ifdef CONFIG_PCIE3
 147 static struct pci_controller pcie3_hose;
 148 #endif
 149
 150 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 151 extern void fsl_pci_init(struct pci_controller *hose);
 152
 153 int first_free_busno=0;
 154 #ifdef CONFIG_PCI
 155 void pci_init_board(void)
 156 {
 157         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 158         uint devdisr = gur->devdisr;
 159         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 160         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 161
 162         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 163                         devdisr, io_sel, host_agent);
 164
 165         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 166                 printf ("    eTSEC1 is in sgmii mode.\n");
 167         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 168                 printf ("    eTSEC2 is in sgmii mode.\n");
 169         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 170                 printf ("    eTSEC3 is in sgmii mode.\n");
 171         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 172                 printf ("    eTSEC4 is in sgmii mode.\n");
 173
 174
 175 #ifdef CONFIG_PCIE3
 176         {
 177                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 178                 struct pci_controller *hose = &pcie3_hose;
 179                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 180                         (host_agent == 5) || (host_agent == 6);
 181                 int pcie_configured  = io_sel >= 1;
 182                 struct pci_region *r = hose->regions;
 183                 u32 temp32;
 184
 185                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 186                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 187                                         pcie_ep ? "End Point" : "Root Complex",
 188                                         (uint)pci);
 189                         if (pci->pme_msg_det) {
 190                                 pci->pme_msg_det = 0xffffffff;
 191                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 192                         }
 193                         printf ("\n");
 194
 195                         /* inbound */
 196                         r += fsl_pci_setup_inbound_windows(r);
 197
 198                         /* outbound memory */
 199                         pci_set_region(r++,
 200                                         CONFIG_SYS_PCIE3_MEM_BASE,
 201                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 202                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 203                                         PCI_REGION_MEM);
 204
 205                         /* outbound io */
 206                         pci_set_region(r++,
 207                                         CONFIG_SYS_PCIE3_IO_BASE,
 208                                         CONFIG_SYS_PCIE3_IO_PHYS,
 209                                         CONFIG_SYS_PCIE3_IO_SIZE,
 210                                         PCI_REGION_IO);
 211
 212                         hose->region_count = r - hose->regions;
 213                         hose->first_busno=first_free_busno;
 214                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 215
 216                         fsl_pci_init(hose);
 217
 218                         first_free_busno=hose->last_busno+1;
 219                         printf ("    PCIE3 on bus %02x - %02x\n",
 220                                         hose->first_busno,hose->last_busno);
 221
 222                         /*
 223                          * Activate ULI1575 legacy chip by performing a fake
 224                          * memory access.  Needed to make ULI RTC work.
 225                          * Device 1d has the first on-board memory BAR.
 226                          */
 227
 228                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 229                                         PCI_BASE_ADDRESS_1, &temp32);
 230                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
 231                                 debug(" uli1572 read to %x\n", temp32);
 232                                 in_be32((unsigned *)temp32);
 233                         }
 234                 } else {
 235                         printf ("    PCIE3: disabled\n");
 236                 }
 237
 238         }
 239 #else
 240         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 241 #endif
 242
 243 #ifdef CONFIG_PCIE2
 244         {
 245                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 246                 struct pci_controller *hose = &pcie2_hose;
 247                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 248                         (host_agent == 6) || (host_agent == 0);
 249                 int pcie_configured  = io_sel & 4;
 250                 struct pci_region *r = hose->regions;
 251
 252                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 253                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 254                                         pcie_ep ? "End Point" : "Root Complex",
 255                                         (uint)pci);
 256                         if (pci->pme_msg_det) {
 257                                 pci->pme_msg_det = 0xffffffff;
 258                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 259                         }
 260                         printf ("\n");
 261
 262                         /* inbound */
 263                         r += fsl_pci_setup_inbound_windows(r);
 264
 265                         /* outbound memory */
 266                         pci_set_region(r++,
 267                                         CONFIG_SYS_PCIE2_MEM_BASE,
 268                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 269                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 270                                         PCI_REGION_MEM);
 271
 272                         /* outbound io */
 273                         pci_set_region(r++,
 274                                         CONFIG_SYS_PCIE2_IO_BASE,
 275                                         CONFIG_SYS_PCIE2_IO_PHYS,
 276                                         CONFIG_SYS_PCIE2_IO_SIZE,
 277                                         PCI_REGION_IO);
 278
 279                         hose->region_count = r - hose->regions;
 280                         hose->first_busno=first_free_busno;
 281                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 282
 283                         fsl_pci_init(hose);
 284                         first_free_busno=hose->last_busno+1;
 285                         printf ("    PCIE2 on bus %02x - %02x\n",
 286                                         hose->first_busno,hose->last_busno);
 287
 288                 } else {
 289                         printf ("    PCIE2: disabled\n");
 290                 }
 291
 292         }
 293 #else
 294         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 295 #endif
 296 #ifdef CONFIG_PCIE1
 297         {
 298                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 299                 struct pci_controller *hose = &pcie1_hose;
 300                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 301                         (host_agent == 5);
 302                 int pcie_configured  = io_sel & 6;
 303                 struct pci_region *r = hose->regions;
 304
 305                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 306                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 307                                         pcie_ep ? "End Point" : "Root Complex",
 308                                         (uint)pci);
 309                         if (pci->pme_msg_det) {
 310                                 pci->pme_msg_det = 0xffffffff;
 311                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 312                         }
 313                         printf ("\n");
 314
 315                         /* inbound */
 316                         r += fsl_pci_setup_inbound_windows(r);
 317
 318                         /* outbound memory */
 319                         pci_set_region(r++,
 320                                         CONFIG_SYS_PCIE1_MEM_BASE,
 321                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 322                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 323                                         PCI_REGION_MEM);
 324
 325                         /* outbound io */
 326                         pci_set_region(r++,
 327                                         CONFIG_SYS_PCIE1_IO_BASE,
 328                                         CONFIG_SYS_PCIE1_IO_PHYS,
 329                                         CONFIG_SYS_PCIE1_IO_SIZE,
 330                                         PCI_REGION_IO);
 331
 332                         hose->region_count = r - hose->regions;
 333                         hose->first_busno=first_free_busno;
 334
 335                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 336
 337                         fsl_pci_init(hose);
 338
 339                         first_free_busno=hose->last_busno+1;
 340                         printf("    PCIE1 on bus %02x - %02x\n",
 341                                         hose->first_busno,hose->last_busno);
 342
 343                 } else {
 344                         printf ("    PCIE1: disabled\n");
 345                 }
 346
 347         }
 348 #else
 349         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 350 #endif
 351 }
 352 #endif
 353
 354 int board_early_init_r(void)
 355 {
 356         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 357         const u8 flash_esel = 2;
 358
 359         /*
 360          * Remap Boot flash + PROMJET region to caching-inhibited
 361          * so that flash can be erased properly.
 362          */
 363
 364         /* Flush d-cache and invalidate i-cache of any FLASH data */
 365         flush_dcache();
 366         invalidate_icache();
 367
 368         /* invalidate existing TLB entry for flash + promjet */
 369         disable_tlb(flash_esel);
 370
 371         set_tlb(1, flashbase, flashbase,                /* tlb, epn, rpn */
 372                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 373                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 374
 375         return 0;
 376 }
 377
 378 #ifdef CONFIG_GET_CLK_FROM_ICS307
 379 /* decode S[0-2] to Output Divider (OD) */
 380 static unsigned char ics307_S_to_OD[] = {
 381         10, 2, 8, 4, 5, 7, 3, 6
 382 };
 383
 384 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 385  * the control bytes being programmed into it. */
 386 /* XXX: This function should probably go into a common library */
 387 static unsigned long
 388 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 389 {
 390         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 391         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 392         unsigned long RDW = cw2 & 0x7F;
 393         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 394         unsigned long freq;
 395
 396         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 397
 398         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 399          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 400          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 401          *
 402          * R6:R0 = Reference Divider Word (RDW)
 403          * V8:V0 = VCO Divider Word (VDW)
 404          * S2:S0 = Output Divider Select (OD)
 405          * F1:F0 = Function of CLK2 Output
 406          * TTL = duty cycle
 407          * C1:C0 = internal load capacitance for cyrstal
 408          */
 409
 410         /* Adding 1 to get a "nicely" rounded number, but this needs
 411          * more tweaking to get a "properly" rounded number. */
 412
 413         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 414
 415         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 416                         freq);
 417         return freq;
 418 }
 419
 420 unsigned long get_board_sys_clk(ulong dummy)
 421 {
 422         return ics307_clk_freq (
 423                         in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 424                         in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 425                         in8(PIXIS_BASE + PIXIS_VSYSCLK2)
 426                         );
 427 }
 428
 429 unsigned long get_board_ddr_clk(ulong dummy)
 430 {
 431         return ics307_clk_freq (
 432                         in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 433                         in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 434                         in8(PIXIS_BASE + PIXIS_VDDRCLK2)
 435                         );
 436 }
 437 #else
 438 unsigned long get_board_sys_clk(ulong dummy)
 439 {
 440         u8 i;
 441         ulong val = 0;
 442
 443         i = in8(PIXIS_BASE + PIXIS_SPD);
 444         i &= 0x07;
 445
 446         switch (i) {
 447                 case 0:
 448                         val = 33333333;
 449                         break;
 450                 case 1:
 451                         val = 40000000;
 452                         break;
 453                 case 2:
 454                         val = 50000000;
 455                         break;
 456                 case 3:
 457                         val = 66666666;
 458                         break;
 459                 case 4:
 460                         val = 83333333;
 461                         break;
 462                 case 5:
 463                         val = 100000000;
 464                         break;
 465                 case 6:
 466                         val = 133333333;
 467                         break;
 468                 case 7:
 469                         val = 166666666;
 470                         break;
 471         }
 472
 473         return val;
 474 }
 475
 476 unsigned long get_board_ddr_clk(ulong dummy)
 477 {
 478         u8 i;
 479         ulong val = 0;
 480
 481         i = in8(PIXIS_BASE + PIXIS_SPD);
 482         i &= 0x38;
 483         i >>= 3;
 484
 485         switch (i) {
 486                 case 0:
 487                         val = 33333333;
 488                         break;
 489                 case 1:
 490                         val = 40000000;
 491                         break;
 492                 case 2:
 493                         val = 50000000;
 494                         break;
 495                 case 3:
 496                         val = 66666666;
 497                         break;
 498                 case 4:
 499                         val = 83333333;
 500                         break;
 501                 case 5:
 502                         val = 100000000;
 503                         break;
 504                 case 6:
 505                         val = 133333333;
 506                         break;
 507                 case 7:
 508                         val = 166666666;
 509                         break;
 510         }
 511         return val;
 512 }
 513 #endif
 514
 515 #ifdef CONFIG_TSEC_ENET
 516 int board_eth_init(bd_t *bis)
 517 {
 518         struct tsec_info_struct tsec_info[4];
 519         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 520         int num = 0;
 521
 522 #ifdef CONFIG_TSEC1
 523         SET_STD_TSEC_INFO(tsec_info[num], 1);
 524         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 525                 tsec_info[num].flags |= TSEC_SGMII;
 526         num++;
 527 #endif
 528 #ifdef CONFIG_TSEC2
 529         SET_STD_TSEC_INFO(tsec_info[num], 2);
 530         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 531                 tsec_info[num].flags |= TSEC_SGMII;
 532         num++;
 533 #endif
 534 #ifdef CONFIG_TSEC3
 535         SET_STD_TSEC_INFO(tsec_info[num], 3);
 536         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 537                 tsec_info[num].flags |= TSEC_SGMII;
 538         num++;
 539 #endif
 540 #ifdef CONFIG_TSEC4
 541         SET_STD_TSEC_INFO(tsec_info[num], 4);
 542         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 543                 tsec_info[num].flags |= TSEC_SGMII;
 544         num++;
 545 #endif
 546
 547         if (!num) {
 548                 printf("No TSECs initialized\n");
 549
 550                 return 0;
 551         }
 552
 553         fsl_sgmii_riser_init(tsec_info, num);
 554
 555         tsec_eth_init(bis, tsec_info, num);
 556
 557         return 0;
 558 }
 559 #endif
 560
 561 #if defined(CONFIG_OF_BOARD_SETUP)
 562 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 563                         struct pci_controller *hose);
 564
 565 void ft_board_setup(void *blob, bd_t *bd)
 566 {
 567         ulong base, size;
 568
 569         ft_cpu_setup(blob, bd);
 570
 571         base = getenv_bootm_low();
 572         size = getenv_bootm_size();
 573
 574         fdt_fixup_memory(blob, (u64)base, (u64)size);
 575
 576 #ifdef CONFIG_PCIE3
 577         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 578 #endif
 579 #ifdef CONFIG_PCIE2
 580         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 581 #endif
 582 #ifdef CONFIG_PCIE1
 583         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 584 #endif
 585 }
 586 #endif
 587
 588 #ifdef CONFIG_MP
 589 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 590
 591 void board_lmb_reserve(struct lmb *lmb)
 592 {
 593         cpu_mp_lmb_reserve(lmb);
 594 }
 595 #endif