board/freescale/t4qds/eth.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <asm/mmu.h>
  11 #include <asm/processor.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/fsl_ddr_sdram.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <asm/fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include "../common/qixis.h"
  27 #include "../common/fman.h"
  28
  29 #include "t4240qds_qixis.h"
  30
  31 #define EMI_NONE        0xFFFFFFFF
  32 #define EMI1_RGMII      0
  33 #define EMI1_SLOT1      1
  34 #define EMI1_SLOT2      2
  35 #define EMI1_SLOT3      3
  36 #define EMI1_SLOT4      4
  37 #define EMI1_SLOT5      5
  38 #define EMI1_SLOT7      7
  39 #define EMI2            8
  40 /* Slot6 and Slot8 do not have EMI connections */
  41
  42 static int mdio_mux[NUM_FM_PORTS];
  43
  44 static const char *mdio_names[] = {
  45         "T4240QDS_MDIO0",
  46         "T4240QDS_MDIO1",
  47         "T4240QDS_MDIO2",
  48         "T4240QDS_MDIO3",
  49         "T4240QDS_MDIO4",
  50         "T4240QDS_MDIO5",
  51         "NULL",
  52         "T4240QDS_MDIO7",
  53         "T4240QDS_10GC",
  54 };
  55
  56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  58 static u8 slot_qsgmii_phyaddr[5][4] = {
  59         {0, 0, 0, 0},/* not used, to make index match slot No. */
  60         {0, 1, 2, 3},
  61         {4, 5, 6, 7},
  62         {8, 9, 0xa, 0xb},
  63         {0xc, 0xd, 0xe, 0xf},
  64 };
  65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  66
  67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  68 {
  69         return mdio_names[muxval];
  70 }
  71
  72 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  73 {
  74         struct mii_dev *bus;
  75         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  76
  77         if (!name) {
  78                 printf("No bus for muxval %x\n", muxval);
  79                 return NULL;
  80         }
  81
  82         bus = miiphy_get_dev_by_name(name);
  83
  84         if (!bus) {
  85                 printf("No bus by name %s\n", name);
  86                 return NULL;
  87         }
  88
  89         return bus;
  90 }
  91
  92 struct t4240qds_mdio {
  93         u8 muxval;
  94         struct mii_dev *realbus;
  95 };
  96
  97 static void t4240qds_mux_mdio(u8 muxval)
  98 {
  99         u8 brdcfg4;
 100         if ((muxval < 6) || (muxval == 7)) {
 101                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 102                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 103                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 104                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 105         }
 106 }
 107
 108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 109                                 int regnum)
 110 {
 111         struct t4240qds_mdio *priv = bus->priv;
 112
 113         t4240qds_mux_mdio(priv->muxval);
 114
 115         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 116 }
 117
 118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 119                                 int regnum, u16 value)
 120 {
 121         struct t4240qds_mdio *priv = bus->priv;
 122
 123         t4240qds_mux_mdio(priv->muxval);
 124
 125         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 126 }
 127
 128 static int t4240qds_mdio_reset(struct mii_dev *bus)
 129 {
 130         struct t4240qds_mdio *priv = bus->priv;
 131
 132         return priv->realbus->reset(priv->realbus);
 133 }
 134
 135 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 136 {
 137         struct t4240qds_mdio *pmdio;
 138         struct mii_dev *bus = mdio_alloc();
 139
 140         if (!bus) {
 141                 printf("Failed to allocate T4240QDS MDIO bus\n");
 142                 return -1;
 143         }
 144
 145         pmdio = malloc(sizeof(*pmdio));
 146         if (!pmdio) {
 147                 printf("Failed to allocate T4240QDS private data\n");
 148                 free(bus);
 149                 return -1;
 150         }
 151
 152         bus->read = t4240qds_mdio_read;
 153         bus->write = t4240qds_mdio_write;
 154         bus->reset = t4240qds_mdio_reset;
 155         sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 156
 157         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 158
 159         if (!pmdio->realbus) {
 160                 printf("No bus with name %s\n", realbusname);
 161                 free(bus);
 162                 free(pmdio);
 163                 return -1;
 164         }
 165
 166         pmdio->muxval = muxval;
 167         bus->priv = pmdio;
 168
 169         return mdio_register(bus);
 170 }
 171
 172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 173                                 enum fm_port port, int offset)
 174 {
 175         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 176                 switch (port) {
 177                 case FM1_DTSEC1:
 178                         if (qsgmiiphy_fix[port])
 179                                 fdt_set_phy_handle(blob, prop, pa,
 180                                                    "sgmii_phy21");
 181                         break;
 182                 case FM1_DTSEC2:
 183                         if (qsgmiiphy_fix[port])
 184                                 fdt_set_phy_handle(blob, prop, pa,
 185                                                    "sgmii_phy22");
 186                         break;
 187                 case FM1_DTSEC3:
 188                         if (qsgmiiphy_fix[port])
 189                                 fdt_set_phy_handle(blob, prop, pa,
 190                                                    "sgmii_phy23");
 191                         break;
 192                 case FM1_DTSEC4:
 193                         if (qsgmiiphy_fix[port])
 194                                 fdt_set_phy_handle(blob, prop, pa,
 195                                                    "sgmii_phy24");
 196                         break;
 197                 case FM1_DTSEC6:
 198                         if (qsgmiiphy_fix[port])
 199                                 fdt_set_phy_handle(blob, prop, pa,
 200                                                    "sgmii_phy12");
 201                         break;
 202                 case FM1_DTSEC9:
 203                         if (qsgmiiphy_fix[port])
 204                                 fdt_set_phy_handle(blob, prop, pa,
 205                                                    "sgmii_phy14");
 206                         else
 207                                 fdt_set_phy_handle(blob, prop, pa,
 208                                                    "phy_sgmii4");
 209                         break;
 210                 case FM1_DTSEC10:
 211                         if (qsgmiiphy_fix[port])
 212                                 fdt_set_phy_handle(blob, prop, pa,
 213                                                    "sgmii_phy13");
 214                         else
 215                                 fdt_set_phy_handle(blob, prop, pa,
 216                                                    "phy_sgmii3");
 217                         break;
 218                 case FM2_DTSEC1:
 219                         if (qsgmiiphy_fix[port])
 220                                 fdt_set_phy_handle(blob, prop, pa,
 221                                                    "sgmii_phy41");
 222                         break;
 223                 case FM2_DTSEC2:
 224                         if (qsgmiiphy_fix[port])
 225                                 fdt_set_phy_handle(blob, prop, pa,
 226                                                    "sgmii_phy42");
 227                         break;
 228                 case FM2_DTSEC3:
 229                         if (qsgmiiphy_fix[port])
 230                                 fdt_set_phy_handle(blob, prop, pa,
 231                                                    "sgmii_phy43");
 232                         break;
 233                 case FM2_DTSEC4:
 234                         if (qsgmiiphy_fix[port])
 235                                 fdt_set_phy_handle(blob, prop, pa,
 236                                                    "sgmii_phy44");
 237                         break;
 238                 case FM2_DTSEC6:
 239                         if (qsgmiiphy_fix[port])
 240                                 fdt_set_phy_handle(blob, prop, pa,
 241                                                    "sgmii_phy32");
 242                         break;
 243                 case FM2_DTSEC9:
 244                         if (qsgmiiphy_fix[port])
 245                                 fdt_set_phy_handle(blob, prop, pa,
 246                                                    "sgmii_phy34");
 247                         else
 248                                 fdt_set_phy_handle(blob, prop, pa,
 249                                                    "phy_sgmii12");
 250                         break;
 251                 case FM2_DTSEC10:
 252                         if (qsgmiiphy_fix[port])
 253                                 fdt_set_phy_handle(blob, prop, pa,
 254                                                    "sgmii_phy33");
 255                         else
 256                                 fdt_set_phy_handle(blob, prop, pa,
 257                                                    "phy_sgmii11");
 258                         break;
 259                 default:
 260                         break;
 261                 }
 262         }
 263 }
 264
 265 void fdt_fixup_board_enet(void *fdt)
 266 {
 267         int i;
 268         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 269         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 270
 271         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 272         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 273                 switch (fm_info_get_enet_if(i)) {
 274                 case PHY_INTERFACE_MODE_SGMII:
 275                         switch (mdio_mux[i]) {
 276                         case EMI1_SLOT1:
 277                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 278                                 break;
 279                         case EMI1_SLOT2:
 280                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 281                                 break;
 282                         case EMI1_SLOT3:
 283                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 284                                 break;
 285                         case EMI1_SLOT4:
 286                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 287                                 break;
 288                         default:
 289                                 break;
 290                         }
 291                         break;
 292                 case PHY_INTERFACE_MODE_XGMII:
 293                         /* check if it's XFI interface for 10g */
 294                         if ((prtcl2 == 56) || (prtcl2 == 57)) {
 295                                 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
 296                                 break;
 297                         }
 298                         switch (i) {
 299                         case FM1_10GEC1:
 300                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 301                                 break;
 302                         case FM1_10GEC2:
 303                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 304                                 break;
 305                         case FM2_10GEC1:
 306                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 307                                 break;
 308                         case FM2_10GEC2:
 309                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 310                                 break;
 311                         default:
 312                                 break;
 313                         }
 314                         break;
 315                 default:
 316                         break;
 317                 }
 318         }
 319 }
 320
 321 static void initialize_qsgmiiphy_fix(void)
 322 {
 323         int i;
 324         unsigned short reg;
 325
 326         for (i = 1; i <= 4; i++) {
 327                 /*
 328                  * Try to read if a SGMII card is used, we do it slot by slot.
 329                  * if a SGMII PHY address is valid on a slot, then we mark
 330                  * all ports on the slot, then fix the PHY address for the
 331                  * marked port when doing dtb fixup.
 332                  */
 333                 if (miiphy_read(mdio_names[i],
 334                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 335                         debug("Slot%d PHY ID register 2 read failed\n", i);
 336                         continue;
 337                 }
 338
 339                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 340
 341                 if (reg == 0xFFFF) {
 342                         /* No physical device present at this address */
 343                         continue;
 344                 }
 345
 346                 switch (i) {
 347                 case 1:
 348                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 349                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 350                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 351                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 352                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 353                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 354                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 355                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 356                         break;
 357                 case 2:
 358                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 359                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 360                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 361                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 362                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 363                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 364                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 365                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 366                         break;
 367                 case 3:
 368                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 369                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 370                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 371                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 372                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 373                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 374                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 375                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 376                         break;
 377                 case 4:
 378                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 379                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 380                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 381                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 382                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 383                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 384                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 385                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 386                         break;
 387                 default:
 388                         break;
 389                 }
 390         }
 391 }
 392
 393 int board_eth_init(bd_t *bis)
 394 {
 395 #if defined(CONFIG_FMAN_ENET)
 396         int i, idx, lane, slot;
 397         struct memac_mdio_info dtsec_mdio_info;
 398         struct memac_mdio_info tgec_mdio_info;
 399         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 400         u32 srds_prtcl_s1, srds_prtcl_s2;
 401
 402         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 403                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 404         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 405         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 406                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 407         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 408
 409         /* Initialize the mdio_mux array so we can recognize empty elements */
 410         for (i = 0; i < NUM_FM_PORTS; i++)
 411                 mdio_mux[i] = EMI_NONE;
 412
 413         dtsec_mdio_info.regs =
 414                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 415
 416         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 417
 418         /* Register the 1G MDIO bus */
 419         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 420
 421         tgec_mdio_info.regs =
 422                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 423         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 424
 425         /* Register the 10G MDIO bus */
 426         fm_memac_mdio_init(bis, &tgec_mdio_info);
 427
 428         /* Register the muxing front-ends to the MDIO buses */
 429         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 430         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 431         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 432         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 433         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 434         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 435         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 436         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 437
 438         initialize_qsgmiiphy_fix();
 439
 440         switch (srds_prtcl_s1) {
 441         case 1:
 442         case 2:
 443         case 4:
 444                 /* XAUI/HiGig in Slot1 and Slot2 */
 445                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 446                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 447                 break;
 448         case 28:
 449         case 36:
 450                 /* SGMII in Slot1 and Slot2 */
 451                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 452                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 453                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 454                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 455                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 456                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 457                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 458                         fm_info_set_phy_address(FM1_DTSEC9,
 459                                                 slot_qsgmii_phyaddr[1][3]);
 460                         fm_info_set_phy_address(FM1_DTSEC10,
 461                                                 slot_qsgmii_phyaddr[1][2]);
 462                 }
 463                 break;
 464         case 38:
 465                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 466                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 467                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 468                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 469                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 470                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 471                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 472                         fm_info_set_phy_address(FM1_DTSEC9,
 473                                                 slot_qsgmii_phyaddr[1][3]);
 474                         fm_info_set_phy_address(FM1_DTSEC10,
 475                                                 slot_qsgmii_phyaddr[1][2]);
 476                 }
 477                 break;
 478         case 40:
 479         case 46:
 480         case 48:
 481                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 482                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 483                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 484                         fm_info_set_phy_address(FM1_DTSEC10,
 485                                                 slot_qsgmii_phyaddr[1][3]);
 486                         fm_info_set_phy_address(FM1_DTSEC9,
 487                                                 slot_qsgmii_phyaddr[1][2]);
 488                 }
 489                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 490                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 491                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 492                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 493                 break;
 494         default:
 495                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 496                 break;
 497         }
 498
 499         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 500                 idx = i - FM1_DTSEC1;
 501                 switch (fm_info_get_enet_if(i)) {
 502                 case PHY_INTERFACE_MODE_SGMII:
 503                         lane = serdes_get_first_lane(FSL_SRDS_1,
 504                                                 SGMII_FM1_DTSEC1 + idx);
 505                         if (lane < 0)
 506                                 break;
 507                         slot = lane_to_slot_fsm1[lane];
 508                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 509                                 idx + 1, slot);
 510                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 511                                 fm_disable_port(i);
 512                         switch (slot) {
 513                         case 1:
 514                                 mdio_mux[i] = EMI1_SLOT1;
 515                                 fm_info_set_mdio(i,
 516                                         mii_dev_for_muxval(mdio_mux[i]));
 517                                 break;
 518                         case 2:
 519                                 mdio_mux[i] = EMI1_SLOT2;
 520                                 fm_info_set_mdio(i,
 521                                         mii_dev_for_muxval(mdio_mux[i]));
 522                                 break;
 523                         };
 524                         break;
 525                 case PHY_INTERFACE_MODE_RGMII:
 526                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 527                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 528                                 idx + 1, 2);
 529                         if (i == FM1_DTSEC5)
 530                                 fm_info_set_phy_address(i, 2);
 531                         mdio_mux[i] = EMI1_RGMII;
 532                         fm_info_set_mdio(i,
 533                                 mii_dev_for_muxval(mdio_mux[i]));
 534                         break;
 535                 default:
 536                         break;
 537                 }
 538         }
 539
 540         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 541                 idx = i - FM1_10GEC1;
 542                 switch (fm_info_get_enet_if(i)) {
 543                 case PHY_INTERFACE_MODE_XGMII:
 544                         lane = serdes_get_first_lane(FSL_SRDS_1,
 545                                                 XAUI_FM1_MAC9 + idx);
 546                         if (lane < 0)
 547                                 break;
 548                         slot = lane_to_slot_fsm1[lane];
 549                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 550                                 fm_disable_port(i);
 551                         mdio_mux[i] = EMI2;
 552                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 553                         break;
 554                 default:
 555                         break;
 556                 }
 557         }
 558
 559 #if (CONFIG_SYS_NUM_FMAN == 2)
 560         switch (srds_prtcl_s2) {
 561         case 1:
 562         case 2:
 563         case 4:
 564                 /* XAUI/HiGig in Slot3 and Slot4 */
 565                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 566                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 567                 break;
 568         case 7:
 569         case 13:
 570         case 14:
 571         case 16:
 572         case 22:
 573         case 23:
 574         case 25:
 575         case 26:
 576                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 577                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 578                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 579                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 580                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 581                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 582                 break;
 583         case 28:
 584         case 36:
 585                 /* SGMII in Slot3 and Slot4 */
 586                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 587                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 588                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 589                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 590                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 591                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 592                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 593                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 594                 break;
 595         case 38:
 596                 /* QSGMII in Slot3 and Slot4 */
 597                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 598                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 599                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 600                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 601                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 602                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 603                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 604                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 605                 break;
 606         case 40:
 607         case 46:
 608         case 48:
 609                 /* SGMII in Slot3 */
 610                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 611                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 612                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 613                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 614                 /* QSGMII in Slot4 */
 615                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 616                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 617                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 618                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 619                 break;
 620         case 50:
 621         case 52:
 622         case 54:
 623                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 624                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 625                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 626                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 627                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 628                 break;
 629         case 56:
 630         case 57:
 631                 /* XFI in Slot3, SGMII in Slot4 */
 632                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 633                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 634                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 635                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 636                 break;
 637         default:
 638                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 639                 break;
 640         }
 641
 642         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 643                 idx = i - FM2_DTSEC1;
 644                 switch (fm_info_get_enet_if(i)) {
 645                 case PHY_INTERFACE_MODE_SGMII:
 646                         lane = serdes_get_first_lane(FSL_SRDS_2,
 647                                                 SGMII_FM2_DTSEC1 + idx);
 648                         if (lane < 0)
 649                                 break;
 650                         slot = lane_to_slot_fsm2[lane];
 651                         debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 652                                 idx + 1, slot);
 653                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 654                                 fm_disable_port(i);
 655                         switch (slot) {
 656                         case 3:
 657                                 mdio_mux[i] = EMI1_SLOT3;
 658                                 fm_info_set_mdio(i,
 659                                         mii_dev_for_muxval(mdio_mux[i]));
 660                                 break;
 661                         case 4:
 662                                 mdio_mux[i] = EMI1_SLOT4;
 663                                 fm_info_set_mdio(i,
 664                                         mii_dev_for_muxval(mdio_mux[i]));
 665                                 break;
 666                         };
 667                         break;
 668                 case PHY_INTERFACE_MODE_RGMII:
 669                         /*
 670                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 671                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 672                          * then it's routed via via EC2 to the second on-board
 673                          * RGMII port.
 674                          */
 675                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 676                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 677                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 678                         mdio_mux[i] = EMI1_RGMII;
 679                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 680                         break;
 681                 default:
 682                         break;
 683                 }
 684         }
 685
 686         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 687                 idx = i - FM2_10GEC1;
 688                 switch (fm_info_get_enet_if(i)) {
 689                 case PHY_INTERFACE_MODE_XGMII:
 690                         lane = serdes_get_first_lane(FSL_SRDS_2,
 691                                                 XAUI_FM2_MAC9 + idx);
 692                         if (lane < 0)
 693                                 break;
 694                         slot = lane_to_slot_fsm2[lane];
 695                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 696                                 fm_disable_port(i);
 697                         mdio_mux[i] = EMI2;
 698                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 699                         break;
 700                 default:
 701                         break;
 702                 }
 703         }
 704 #endif /* CONFIG_SYS_NUM_FMAN */
 705
 706         cpu_eth_init(bis);
 707 #endif /* CONFIG_FMAN_ENET */
 708
 709         return pci_eth_init(bis);
 710 }