board/gateworks/gw_ventana/gsc.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <asm/errno.h>
  10 #include <common.h>
  11 #include <i2c.h>
  12 #include <linux/ctype.h>
  13
  14 #include "gsc.h"
  15
  16 /*
  17  * The Gateworks System Controller will fail to ACK a master transaction if
  18  * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
  19  * When this does occur, it will never be busy long enough to fail more than
  20  * 2 back-to-back transfers.  Thus we wrap i2c_read and i2c_write with
  21  * 3 retries.
  22  */
  23 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  24 {
  25         int retry = 3;
  26         int n = 0;
  27         int ret;
  28
  29         while (n++ < retry) {
  30                 ret = i2c_read(chip, addr, alen, buf, len);
  31                 if (!ret)
  32                         break;
  33                 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
  34                       n, ret);
  35                 if (ret != -ENODEV)
  36                         break;
  37                 mdelay(10);
  38         }
  39         return ret;
  40 }
  41
  42 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  43 {
  44         int retry = 3;
  45         int n = 0;
  46         int ret;
  47
  48         while (n++ < retry) {
  49                 ret = i2c_write(chip, addr, alen, buf, len);
  50                 if (!ret)
  51                         break;
  52                 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
  53                       n, ret);
  54                 if (ret != -ENODEV)
  55                         break;
  56                 mdelay(10);
  57         }
  58         mdelay(100);
  59         return ret;
  60 }
  61
  62 static void read_hwmon(const char *name, uint reg, uint size)
  63 {
  64         unsigned char buf[3];
  65         uint ui;
  66
  67         printf("%-8s:", name);
  68         memset(buf, 0, sizeof(buf));
  69         if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
  70                 puts("fRD\n");
  71         } else {
  72                 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
  73                 if (ui == 0xffffff)
  74                         puts("invalid\n");
  75                 else
  76                         printf("%d\n", ui);
  77         }
  78 }
  79
  80 int gsc_info(int verbose)
  81 {
  82         const char *model = getenv("model");
  83         unsigned char buf[16];
  84
  85         i2c_set_bus_num(0);
  86         if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
  87                 return CMD_RET_FAILURE;
  88
  89         printf("GSC:   v%d", buf[GSC_SC_FWVER]);
  90         printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
  91         printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
  92                 ? "en" : "dis");
  93         if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
  94                 buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
  95                 puts(" WDT_RESET");
  96                 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
  97                               &buf[GSC_SC_STATUS], 1);
  98         }
  99         puts("\n");
 100         if (!verbose)
 101                 return CMD_RET_SUCCESS;
 102
 103         read_hwmon("Temp",     GSC_HWMON_TEMP, 2);
 104         read_hwmon("VIN",      GSC_HWMON_VIN, 3);
 105         read_hwmon("VBATT",    GSC_HWMON_VBATT, 3);
 106         read_hwmon("VDD_3P3",  GSC_HWMON_VDD_3P3, 3);
 107         read_hwmon("VDD_ARM",  GSC_HWMON_VDD_CORE, 3);
 108         read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3);
 109         read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
 110         read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3);
 111         read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3);
 112         read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
 113         read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
 114         read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
 115         switch (model[3]) {
 116         case '1': /* GW51xx */
 117                 read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
 118                 break;
 119         case '2': /* GW52xx */
 120                 break;
 121         case '3': /* GW53xx */
 122                 read_hwmon("VDD_IO4",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
 123                 read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
 124                 break;
 125         case '4': /* GW54xx */
 126                 read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
 127                 read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
 128                 break;
 129         case '5': /* GW55xx */
 130                 break;
 131         }
 132         return 0;
 133 }
 134
 135 #ifdef CONFIG_CMD_GSC
 136 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 137 {
 138         unsigned char reg;
 139
 140         if (argc < 2)
 141                 return CMD_RET_USAGE;
 142
 143         if (strcasecmp(argv[1], "enable") == 0) {
 144                 int timeout = 0;
 145
 146                 if (argc > 2)
 147                         timeout = simple_strtoul(argv[2], NULL, 10);
 148                 i2c_set_bus_num(0);
 149                 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
 150                         return CMD_RET_FAILURE;
 151                 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
 152                 if (timeout == 60)
 153                         reg |= (1 << GSC_SC_CTRL1_WDTIME);
 154                 else
 155                         timeout = 30;
 156                 reg |= (1 << GSC_SC_CTRL1_WDEN);
 157                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
 158                         return CMD_RET_FAILURE;
 159                 printf("GSC Watchdog enabled with timeout=%d seconds\n",
 160                        timeout);
 161         } else if (strcasecmp(argv[1], "disable") == 0) {
 162                 i2c_set_bus_num(0);
 163                 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
 164                         return CMD_RET_FAILURE;
 165                 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
 166                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
 167                         return CMD_RET_FAILURE;
 168                 printf("GSC Watchdog disabled\n");
 169         } else {
 170                 return CMD_RET_USAGE;
 171         }
 172         return CMD_RET_SUCCESS;
 173 }
 174
 175 static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 176 {
 177         if (argc < 2)
 178                 return gsc_info(1);
 179
 180         if (strcasecmp(argv[1], "wd") == 0)
 181                 return do_gsc_wd(cmdtp, flag, --argc, ++argv);
 182
 183         return CMD_RET_USAGE;
 184 }
 185
 186 U_BOOT_CMD(
 187         gsc, 4, 1, do_gsc, "GSC configuration",
 188         "[wd enable [30|60]]|[wd disable]\n"
 189         );
 190
 191 #endif /* CONFIG_CMD_GSC */