board/hymod/hymod.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00
  24  */
  25
  26 #include <common.h>
  27 #include <mpc8260.h>
  28 #include <ioports.h>
  29 #include <i2c.h>
  30 #include <asm/iopin_8260.h>
  31
  32 /* ------------------------------------------------------------------------- */
  33
  34 /* imports from eeprom.c */
  35 extern int eeprom_load (unsigned, hymod_eeprom_t *);
  36 extern int eeprom_fetch (unsigned, char *, ulong);
  37 extern void eeprom_print (hymod_eeprom_t *);
  38
  39 /* imports from fetch.c */
  40 extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
  41
  42 /* imports from common/main.c */
  43 extern char console_buffer[CFG_CBSIZE];
  44
  45 /* ------------------------------------------------------------------------- */
  46
  47 /*
  48  * I/O Port configuration table
  49  *
  50  * if conf is 1, then that port pin will be configured at boot time
  51  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  52  */
  53
  54 const iop_conf_t iop_conf_tab[4][32] = {
  55
  56         /* Port A configuration */
  57         {                                                       /*        conf ppar psor pdir podr pdat */
  58                                                                         /* PA31 */ {1, 1, 1, 0, 0, 0},
  59                                                                         /* FCC1 MII COL */
  60                                                                         /* PA30 */ {1, 1, 1, 0, 0, 0},
  61                                                                         /* FCC1 MII CRS */
  62                                                                         /* PA29 */ {1, 1, 1, 1, 0, 0},
  63                                                                         /* FCC1 MII TX_ER */
  64                                                                         /* PA28 */ {1, 1, 1, 1, 0, 0},
  65                                                                         /* FCC1 MII TX_EN */
  66                                                                         /* PA27 */ {1, 1, 1, 0, 0, 0},
  67                                                                         /* FCC1 MII RX_DV */
  68                                                                         /* PA26 */ {1, 1, 1, 0, 0, 0},
  69                                                                         /* FCC1 MII RX_ER */
  70                                                                         /* PA25 */ {1, 0, 0, 1, 0, 0},
  71                                                                         /* FCC2 MII MDIO */
  72                                                                         /* PA24 */ {1, 0, 0, 1, 0, 0},
  73                                                                         /* FCC2 MII MDC */
  74                                                                         /* PA23 */ {1, 0, 0, 1, 0, 0},
  75                                                                         /* FCC3 MII MDIO */
  76                                                                         /* PA22 */ {1, 0, 0, 1, 0, 0},
  77                                                                         /* FCC3 MII MDC */
  78                                                                         /* PA21 */ {1, 1, 0, 1, 0, 0},
  79                                                                         /* FCC1 MII TxD[3] */
  80                                                                         /* PA20 */ {1, 1, 0, 1, 0, 0},
  81                                                                         /* FCC1 MII TxD[2] */
  82                                                                         /* PA19 */ {1, 1, 0, 1, 0, 0},
  83                                                                         /* FCC1 MII TxD[1] */
  84                                                                         /* PA18 */ {1, 1, 0, 1, 0, 0},
  85                                                                         /* FCC1 MII TxD[0] */
  86                                                                         /* PA17 */ {1, 1, 0, 0, 0, 0},
  87                                                                         /* FCC1 MII RxD[3] */
  88                                                                         /* PA16 */ {1, 1, 0, 0, 0, 0},
  89                                                                         /* FCC1 MII RxD[2] */
  90                                                                         /* PA15 */ {1, 1, 0, 0, 0, 0},
  91                                                                         /* FCC1 MII RxD[1] */
  92                                                                         /* PA14 */ {1, 1, 0, 0, 0, 0},
  93                                                                         /* FCC1 MII RxD[0] */
  94                                                                         /* PA13 */ {1, 0, 0, 1, 0, 0},
  95                                                                         /* FCC1 MII MDIO */
  96                                                                         /* PA12 */ {1, 0, 0, 1, 0, 0},
  97                                                                         /* FCC1 MII MDC */
  98                                                                         /* PA11 */ {1, 0, 0, 1, 0, 0},
  99                                                                         /* SEL_CD */
 100                                                                         /* PA10 */ {1, 0, 0, 0, 0, 0},
 101                                                                         /* FLASH STS1 */
 102                                                                         /* PA9  */ {1, 0, 0, 0, 0, 0},
 103                                                                         /* FLASH STS0 */
 104                                                                         /* PA8  */ {1, 0, 0, 0, 0, 0},
 105                                                                         /* FLASH ~PE */
 106                                                                         /* PA7  */ {1, 0, 0, 0, 0, 0},
 107                                                                         /* WATCH ~HRESET */
 108                                                                         /* PA6  */ {1, 0, 0, 0, 1, 0},
 109                                                                         /* VC DONE */
 110                                                                         /* PA5  */ {1, 0, 0, 1, 1, 0},
 111                                                                         /* VC INIT */
 112                                                                         /* PA4  */ {1, 0, 0, 1, 0, 0},
 113                                                                         /* VC ~PROG */
 114                                                                         /* PA3  */ {1, 0, 0, 1, 0, 0},
 115                                                                         /* VM ENABLE */
 116                                                                         /* PA2  */ {1, 0, 0, 0, 1, 0},
 117                                                                         /* VM DONE */
 118                                                                         /* PA1  */ {1, 0, 0, 1, 1, 0},
 119                                                                         /* VM INIT */
 120                                                                         /* PA0  */ {1, 0, 0, 1, 0, 0}
 121                                                                         /* VM ~PROG */
 122          },
 123
 124         /* Port B configuration */
 125         {                                                       /*        conf ppar psor pdir podr pdat */
 126                                                                         /* PB31 */ {1, 1, 0, 1, 0, 0},
 127                                                                         /* FCC2 MII TX_ER */
 128                                                                         /* PB30 */ {1, 1, 0, 0, 0, 0},
 129                                                                         /* FCC2 MII RX_DV */
 130                                                                         /* PB29 */ {1, 1, 1, 1, 0, 0},
 131                                                                         /* FCC2 MII TX_EN */
 132                                                                         /* PB28 */ {1, 1, 0, 0, 0, 0},
 133                                                                         /* FCC2 MII RX_ER */
 134                                                                         /* PB27 */ {1, 1, 0, 0, 0, 0},
 135                                                                         /* FCC2 MII COL */
 136                                                                         /* PB26 */ {1, 1, 0, 0, 0, 0},
 137                                                                         /* FCC2 MII CRS */
 138                                                                         /* PB25 */ {1, 1, 0, 1, 0, 0},
 139                                                                         /* FCC2 MII TxD[3] */
 140                                                                         /* PB24 */ {1, 1, 0, 1, 0, 0},
 141                                                                         /* FCC2 MII TxD[2] */
 142                                                                         /* PB23 */ {1, 1, 0, 1, 0, 0},
 143                                                                         /* FCC2 MII TxD[1] */
 144                                                                         /* PB22 */ {1, 1, 0, 1, 0, 0},
 145                                                                         /* FCC2 MII TxD[0] */
 146                                                                         /* PB21 */ {1, 1, 0, 0, 0, 0},
 147                                                                         /* FCC2 MII RxD[0] */
 148                                                                         /* PB20 */ {1, 1, 0, 0, 0, 0},
 149                                                                         /* FCC2 MII RxD[1] */
 150                                                                         /* PB19 */ {1, 1, 0, 0, 0, 0},
 151                                                                         /* FCC2 MII RxD[2] */
 152                                                                         /* PB18 */ {1, 1, 0, 0, 0, 0},
 153                                                                         /* FCC2 MII RxD[3] */
 154                                                                         /* PB17 */ {1, 1, 0, 0, 0, 0},
 155                                                                         /* FCC3 MII RX_DV */
 156                                                                         /* PB16 */ {1, 1, 0, 0, 0, 0},
 157                                                                         /* FCC3 MII RX_ER */
 158                                                                         /* PB15 */ {1, 1, 0, 1, 0, 0},
 159                                                                         /* FCC3 MII TX_ER */
 160                                                                         /* PB14 */ {1, 1, 0, 1, 0, 0},
 161                                                                         /* FCC3 MII TX_EN */
 162                                                                         /* PB13 */ {1, 1, 0, 0, 0, 0},
 163                                                                         /* FCC3 MII COL */
 164                                                                         /* PB12 */ {1, 1, 0, 0, 0, 0},
 165                                                                         /* FCC3 MII CRS */
 166                                                                         /* PB11 */ {1, 1, 0, 0, 0, 0},
 167                                                                         /* FCC3 MII RxD[3] */
 168                                                                         /* PB10 */ {1, 1, 0, 0, 0, 0},
 169                                                                         /* FCC3 MII RxD[2] */
 170                                                                         /* PB9  */ {1, 1, 0, 0, 0, 0},
 171                                                                         /* FCC3 MII RxD[1] */
 172                                                                         /* PB8  */ {1, 1, 0, 0, 0, 0},
 173                                                                         /* FCC3 MII RxD[0] */
 174                                                                         /* PB7  */ {1, 1, 0, 1, 0, 0},
 175                                                                         /* FCC3 MII TxD[3] */
 176                                                                         /* PB6  */ {1, 1, 0, 1, 0, 0},
 177                                                                         /* FCC3 MII TxD[2] */
 178                                                                         /* PB5  */ {1, 1, 0, 1, 0, 0},
 179                                                                         /* FCC3 MII TxD[1] */
 180                                                                         /* PB4  */ {1, 1, 0, 1, 0, 0},
 181                                                                         /* FCC3 MII TxD[0] */
 182                                                                         /* PB3  */ {0, 0, 0, 0, 0, 0},
 183                                                                         /* pin doesn't exist */
 184                                                                         /* PB2  */ {0, 0, 0, 0, 0, 0},
 185                                                                         /* pin doesn't exist */
 186                                                                         /* PB1  */ {0, 0, 0, 0, 0, 0},
 187                                                                         /* pin doesn't exist */
 188                                                                         /* PB0  */ {0, 0, 0, 0, 0, 0}
 189                                                                         /* pin doesn't exist */
 190          },
 191
 192         /* Port C */
 193         {                                                       /*        conf ppar psor pdir podr pdat */
 194                                                                         /* PC31 */ {1, 0, 0, 0, 0, 0},
 195                                                                         /* MEZ ~IACK */
 196          /* PC30 */ {0, 0, 0, 0, 0, 0},
 197                                                                         /* PC29 */ {1, 1, 0, 0, 0, 0},
 198                                                                         /* CLK SCCx */
 199                                                                         /* PC28 */ {1, 1, 0, 0, 0, 0},
 200                                                                         /* CLK4 */
 201                                                                         /* PC27 */ {1, 1, 0, 0, 0, 0},
 202                                                                         /* CLK SCCF */
 203                                                                         /* PC26 */ {1, 1, 0, 0, 0, 0},
 204                                                                         /* CLK 32K */
 205                                                                         /* PC25 */ {1, 1, 0, 0, 0, 0},
 206                                                                         /* BRG4/CLK7 */
 207          /* PC24 */ {0, 0, 0, 0, 0, 0},
 208                                                                         /* PC23 */ {1, 1, 0, 0, 0, 0},
 209                                                                         /* CLK SCCx */
 210                                                                         /* PC22 */ {1, 1, 0, 0, 0, 0},
 211                                                                         /* FCC1 MII RX_CLK */
 212                                                                         /* PC21 */ {1, 1, 0, 0, 0, 0},
 213                                                                         /* FCC1 MII TX_CLK */
 214                                                                         /* PC20 */ {1, 1, 0, 0, 0, 0},
 215                                                                         /* CLK SCCF */
 216                                                                         /* PC19 */ {1, 1, 0, 0, 0, 0},
 217                                                                         /* FCC2 MII RX_CLK */
 218                                                                         /* PC18 */ {1, 1, 0, 0, 0, 0},
 219                                                                         /* FCC2 MII TX_CLK */
 220                                                                         /* PC17 */ {1, 1, 0, 0, 0, 0},
 221                                                                         /* FCC3 MII RX_CLK */
 222                                                                         /* PC16 */ {1, 1, 0, 0, 0, 0},
 223                                                                         /* FCC3 MII TX_CLK */
 224                                                                         /* PC15 */ {1, 0, 0, 0, 0, 0},
 225                                                                         /* SCC1 UART ~CTS */
 226                                                                         /* PC14 */ {1, 0, 0, 0, 0, 0},
 227                                                                         /* SCC1 UART ~CD */
 228                                                                         /* PC13 */ {1, 0, 0, 0, 0, 0},
 229                                                                         /* SCC2 UART ~CTS */
 230                                                                         /* PC12 */ {1, 0, 0, 0, 0, 0},
 231                                                                         /* SCC2 UART ~CD */
 232                                                                         /* PC11 */ {1, 0, 0, 1, 0, 0},
 233                                                                         /* SCC1 UART ~DTR */
 234                                                                         /* PC10 */ {1, 0, 0, 1, 0, 0},
 235                                                                         /* SCC1 UART ~DSR */
 236                                                                         /* PC9  */ {1, 0, 0, 1, 0, 0},
 237                                                                         /* SCC2 UART ~DTR */
 238                                                                         /* PC8  */ {1, 0, 0, 1, 0, 0},
 239                                                                         /* SCC2 UART ~DSR */
 240                                                                         /* PC7  */ {1, 0, 0, 0, 0, 0},
 241                                                                         /* TEMP ~ALERT */
 242                                                                         /* PC6  */ {1, 0, 0, 0, 0, 0},
 243                                                                         /* FCC3 INT */
 244                                                                         /* PC5  */ {1, 0, 0, 0, 0, 0},
 245                                                                         /* FCC2 INT */
 246                                                                         /* PC4  */ {1, 0, 0, 0, 0, 0},
 247                                                                         /* FCC1 INT */
 248                                                                         /* PC3  */ {1, 1, 1, 1, 0, 0},
 249                                                                         /* SDMA IDMA2 ~DACK */
 250                                                                         /* PC2  */ {1, 1, 1, 0, 0, 0},
 251                                                                         /* SDMA IDMA2 ~DONE */
 252                                                                         /* PC1  */ {1, 1, 0, 0, 0, 0},
 253                                                                         /* SDMA IDMA2 ~DREQ */
 254                                                                         /* PC0  */ {1, 1, 0, 1, 0, 0}
 255                                                                         /* BRG7 */
 256          },
 257
 258         /* Port D */
 259         {                                                       /*        conf ppar psor pdir podr pdat */
 260                                                                         /* PD31 */ {1, 1, 0, 0, 0, 0},
 261                                                                         /* SCC1 UART RxD */
 262                                                                         /* PD30 */ {1, 1, 1, 1, 0, 0},
 263                                                                         /* SCC1 UART TxD */
 264                                                                         /* PD29 */ {1, 0, 0, 1, 0, 0},
 265                                                                         /* SCC1 UART ~RTS */
 266                                                                         /* PD28 */ {1, 1, 0, 0, 0, 0},
 267                                                                         /* SCC2 UART RxD */
 268                                                                         /* PD27 */ {1, 1, 0, 1, 0, 0},
 269                                                                         /* SCC2 UART TxD */
 270                                                                         /* PD26 */ {1, 0, 0, 1, 0, 0},
 271                                                                         /* SCC2 UART ~RTS */
 272                                                                         /* PD25 */ {1, 0, 0, 0, 0, 0},
 273                                                                         /* SCC1 UART ~RI */
 274                                                                         /* PD24 */ {1, 0, 0, 0, 0, 0},
 275                                                                         /* SCC2 UART ~RI */
 276                                                                         /* PD23 */ {1, 0, 0, 1, 0, 0},
 277                                                                         /* CLKGEN PD */
 278                                                                         /* PD22 */ {1, 0, 0, 0, 0, 0},
 279                                                                         /* USER3 */
 280                                                                         /* PD21 */ {1, 0, 0, 0, 0, 0},
 281                                                                         /* USER2 */
 282                                                                         /* PD20 */ {1, 0, 0, 0, 0, 0},
 283                                                                         /* USER1 */
 284                                                                         /* PD19 */ {1, 1, 1, 0, 0, 0},
 285                                                                         /* SPI ~SEL */
 286                                                                         /* PD18 */ {1, 1, 1, 0, 0, 0},
 287                                                                         /* SPI CLK */
 288                                                                         /* PD17 */ {1, 1, 1, 0, 0, 0},
 289                                                                         /* SPI MOSI */
 290                                                                         /* PD16 */ {1, 1, 1, 0, 0, 0},
 291                                                                         /* SPI MISO */
 292                                                                         /* PD15 */ {1, 1, 1, 0, 1, 0},
 293                                                                         /* I2C SDA */
 294                                                                         /* PD14 */ {1, 1, 1, 0, 1, 0},
 295                                                                         /* I2C SCL */
 296                                                                         /* PD13 */ {1, 0, 0, 1, 0, 1},
 297                                                                         /* TEMP ~STDBY */
 298                                                                         /* PD12 */ {1, 0, 0, 1, 0, 1},
 299                                                                         /* FCC3 ~RESET */
 300                                                                         /* PD11 */ {1, 0, 0, 1, 0, 1},
 301                                                                         /* FCC2 ~RESET */
 302                                                                         /* PD10 */ {1, 0, 0, 1, 0, 1},
 303                                                                         /* FCC1 ~RESET */
 304                                                                         /* PD9  */ {1, 0, 0, 0, 0, 0},
 305                                                                         /* PD9 */
 306                                                                         /* PD8  */ {1, 0, 0, 0, 0, 0},
 307                                                                         /* PD8 */
 308                                                                         /* PD7  */ {1, 0, 0, 1, 0, 1},
 309                                                                         /* PD7 */
 310                                                                         /* PD6  */ {1, 0, 0, 1, 0, 1},
 311                                                                         /* PD6 */
 312                                                                         /* PD5  */ {1, 0, 0, 1, 0, 1},
 313                                                                         /* PD5 */
 314                                                                         /* PD4  */ {1, 0, 0, 1, 0, 1},
 315                                                                         /* PD4 */
 316                                                                         /* PD3  */ {0, 0, 0, 0, 0, 0},
 317                                                                         /* pin doesn't exist */
 318                                                                         /* PD2  */ {0, 0, 0, 0, 0, 0},
 319                                                                         /* pin doesn't exist */
 320                                                                         /* PD1  */ {0, 0, 0, 0, 0, 0},
 321                                                                         /* pin doesn't exist */
 322                                                                         /* PD0  */ {0, 0, 0, 0, 0, 0}
 323                                                                         /* pin doesn't exist */
 324          }
 325 };
 326
 327 /* ------------------------------------------------------------------------- */
 328
 329 /*
 330  * AMI FS6377 Clock Generator configuration table
 331  *
 332  * the "fs6377_regs[]" table entries correspond to FS6377 registers
 333  * 0 - 15 (total of 16 bytes).
 334  *
 335  * the data is written to the FS6377 via the i2c bus using address in
 336  * "fs6377_addr" (address is 7 bits - R/W bit not included).
 337  */
 338
 339 uchar fs6377_addr = 0x5c;
 340
 341 uchar fs6377_regs[16] = {
 342         12, 75, 64, 25, 144, 128, 25, 192,
 343         0, 16, 135, 192, 224, 64, 64, 192
 344 };
 345
 346 iopin_t pa11 = { IOPIN_PORTA, 11, 0 };
 347
 348 /* ------------------------------------------------------------------------- */
 349
 350 /*
 351  * special board initialisation, after clocks and timebase have been
 352  * set up but before environment and serial are initialised.
 353  *
 354  * added so that very early initialisations can be done using the i2c
 355  * driver (which requires the clocks, to calculate the dividers, and
 356  * the timebase, for udelay())
 357  */
 358
 359 int board_postclk_init (void)
 360 {
 361         i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
 362
 363         /*
 364          * Initialise the FS6377 clock chip
 365          *
 366          * the secondary address is the register number from where to
 367          * start the write - I want to write all the registers
 368          *
 369          * don't bother checking return status - we have no console yet
 370          * to print it on, nor any RAM to store it in - it will be obvious
 371          * if this doesn't work
 372          */
 373         (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
 374                                           sizeof (fs6377_regs));
 375
 376         return (0);
 377 }
 378
 379 /* ------------------------------------------------------------------------- */
 380
 381 /*
 382  * Check Board Identity: Hardwired to HYMOD
 383  */
 384
 385 int checkboard (void)
 386 {
 387         puts ("Board: HYMOD\n");
 388         return (0);
 389 }
 390
 391 /* ------------------------------------------------------------------------- */
 392
 393 /*
 394  * miscellaneous (early - while running in flash) initialisations.
 395  */
 396
 397 #define _NOT_USED_      0xFFFFFFFF
 398
 399 uint upmb_table[] = {
 400         /* Read Single Beat (RSS) - offset 0x00 */
 401         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 402         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 403         /* Read Burst (RBS) - offset 0x08 */
 404         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 405         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 406         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 407         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 408         /* Write Single Beat (WSS) - offset 0x18 */
 409         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 410         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 411         /* Write Burst (WSS) - offset 0x20 */
 412         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 413         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 414         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 415         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 416         /* Refresh Timer (PTS) - offset 0x30 */
 417         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 418         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 419         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 420         /* Exception Condition (EXS) - offset 0x3c */
 421         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 422 };
 423
 424 uint upmc_table[] = {
 425         /* Read Single Beat (RSS) - offset 0x00 */
 426         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 427         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 428         /* Read Burst (RBS) - offset 0x08 */
 429         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 430         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 431         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 432         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 433         /* Write Single Beat (WSS) - offset 0x18 */
 434         0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
 435         0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 436         /* Write Burst (WSS) - offset 0x20 */
 437         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 438         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 439         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 440         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 441         /* Refresh Timer (PTS) - offset 0x30 */
 442         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 443         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 444         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 445         /* Exception Condition (EXS) - offset 0x3c */
 446         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 447 };
 448
 449 int misc_init_f (void)
 450 {
 451         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 452         volatile memctl8260_t *memctl = &immap->im_memctl;
 453
 454         printf ("UPMs:  ");
 455
 456         upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
 457         memctl->memc_mbmr = CFG_MBMR;
 458
 459         upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
 460         memctl->memc_mcmr = CFG_MCMR;
 461
 462         printf ("configured\n");
 463         return (0);
 464 }
 465
 466 /* ------------------------------------------------------------------------- */
 467
 468 long initdram (int board_type)
 469 {
 470         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 471         volatile memctl8260_t *memctl = &immap->im_memctl;
 472         volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
 473         ulong psdmr = CFG_PSDMR;
 474         int i;
 475
 476         /*
 477          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 478          *
 479          * "At system reset, initialization software must set up the
 480          *  programmable parameters in the memory controller banks registers
 481          *  (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured,
 482          *  system software should execute the following initialization sequence
 483          *  for each SDRAM device.
 484          *
 485          *  1. Issue a PRECHARGE-ALL-BANKS command
 486          *  2. Issue eight CBR REFRESH commands
 487          *  3. Issue a MODE-SET command to initialize the mode register
 488          *
 489          *  The initial commands are executed by setting P/LSDMR[OP] and
 490          *  accessing the SDRAM with a single-byte transaction."
 491          *
 492          * The appropriate BRx/ORx registers have already been set when we
 493          * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
 494          */
 495
 496         memctl->memc_psrt = CFG_PSRT;
 497         memctl->memc_mptpr = CFG_MPTPR;
 498
 499         memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 500         *ramaddr = c;
 501
 502         memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
 503         for (i = 0; i < 8; i++)
 504                 *ramaddr = c;
 505
 506         memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
 507         *ramaddr = c;
 508
 509         memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 510         *ramaddr = c;
 511
 512         return (CFG_SDRAM_SIZE << 20);
 513 }
 514
 515 /* ------------------------------------------------------------------------- */
 516 /* miscellaneous initialisations after relocation into ram (misc_init_r)     */
 517 /*                                                                           */
 518 /* loads the data in the main board and mezzanine board eeproms into         */
 519 /* the hymod configuration struct stored in the board information area.      */
 520 /*                                                                           */
 521 /* if the contents of either eeprom is invalid, prompts for a serial         */
 522 /* number (and an ethernet address if required) then fetches a file          */
 523 /* containing information to be stored in the eeprom from the tftp server    */
 524 /* (the file name is based on the serial number and a built-in path)         */
 525
 526 /* these are relative to the root of the server's tftp directory */
 527 static char *bddb_cfgdir = "/hymod/bddb";
 528 static char *global_env_path = "/hymod/global_env";
 529
 530 static ulong get_serno (const char *prompt)
 531 {
 532         for (;;) {
 533                 int n;
 534                 char *p;
 535                 ulong serno;
 536
 537                 n = readline (prompt);
 538
 539                 if (n < 0)
 540                         return (0);
 541
 542                 if (n == 0)
 543                         continue;
 544
 545                 serno = simple_strtol (console_buffer, &p, 10);
 546
 547                 if (p > console_buffer && *p == '\0')
 548                         return (serno);
 549
 550                 printf ("Invalid number (%s) - please re-enter\n", console_buffer);
 551         }
 552 }
 553
 554 static int read_eeprom (char *label, unsigned offset, hymod_eeprom_t * ep)
 555 {
 556         char filename[50], prompt[50];
 557         ulong serno;
 558         int count = 0;
 559
 560         sprintf (prompt, "Enter %s board serial number: ", label);
 561
 562         for (;;) {
 563
 564                 if (eeprom_load (offset, ep))
 565                         return (1);
 566
 567                 printf ("*** %s board EEPROM contents are %sinvalid\n",
 568                                 label, count == 0 ? "" : "STILL ");
 569
 570                 puts ("*** will attempt to fetch from server (Ctrl-C to abort)\n");
 571
 572                 if ((serno = get_serno (prompt)) == 0) {
 573                         puts ("\n*** interrupted! - ignoring eeprom contents\n");
 574                         return (0);
 575                 }
 576
 577                 sprintf (filename, "%s/%010lu.cfg", bddb_cfgdir, serno);
 578
 579                 printf ("*** fetching %s board EEPROM contents from server\n",
 580                                 label);
 581
 582                 if (eeprom_fetch (offset, filename, 0x100000) == 0) {
 583                         puts ("*** fetch failed - ignoring eeprom contents\n");
 584                         return (0);
 585                 }
 586
 587                 count++;
 588         }
 589 }
 590
 591 static ulong main_serno;
 592
 593 static int env_fetch_callback (uchar * name, uchar * value)
 594 {
 595         char *ov, nv[CFG_CBSIZE], *p, *q, *nn;
 596         int override = 1, append = 0, nl;
 597
 598         nn = name;
 599         if (*nn == '-') {
 600                 override = 0;
 601                 nn++;
 602         }
 603
 604         if ((nl = strlen (nn)) > 0 && nn[nl - 1] == '+') {
 605                 append = 1;
 606                 nn[--nl] = '\0';
 607         }
 608
 609         p = value;
 610         q = nv;
 611
 612         while ((*q = *p++) != '\0')
 613                 if (*q == '%') {
 614                         switch (*p++) {
 615
 616                         case '\0':                      /* whoops - back up */
 617                                 p--;
 618                                 break;
 619
 620                         case '%':                       /* a single percent character */
 621                                 q++;
 622                                 break;
 623
 624                         case 's':                       /* main board serial number as string */
 625                                 q += sprintf (q, "%010lu", main_serno);
 626                                 break;
 627
 628                         case 'S':                       /* main board serial number as number */
 629                                 q += sprintf (q, "%lu", main_serno);
 630                                 break;
 631
 632                         default:                        /* ignore any others */
 633                                 break;
 634                         }
 635                 } else
 636                         q++;
 637
 638         if ((ov = getenv (nn)) != NULL) {
 639
 640                 if (append) {
 641
 642                         if (strstr (ov, nv) == NULL) {
 643                                 int ovl, nvl;
 644
 645                                 printf ("Appending '%s' to env cmd '%s'\n", nv, nn);
 646
 647                                 ovl = strlen (ov);
 648                                 nvl = strlen (nv);
 649
 650                                 while (nvl >= 0) {
 651                                         nv[ovl + 1 + nvl] = nv[nvl];
 652                                         nvl--;
 653                                 }
 654
 655                                 nv[ovl] = ' ';
 656
 657                                 while (--ovl >= 0)
 658                                         nv[ovl] = ov[ovl];
 659
 660                                 setenv (nn, nv);
 661                         }
 662
 663                         return (1);
 664                 }
 665
 666                 if (!override || strcmp (ov, nv) == 0)
 667                         return (1);
 668
 669                 printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", nn, ov, nv);
 670         } else
 671                 printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
 672
 673         setenv (nn, nv);
 674         return (1);
 675 }
 676
 677 int misc_init_r (void)
 678 {
 679         DECLARE_GLOBAL_DATA_PTR;
 680
 681         hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 682         int rc;
 683
 684         memset ((void *) cp, 0, sizeof (*cp));
 685
 686         /* set up main board config info */
 687
 688         if (i2c_probe (CFG_I2C_EEPROM_ADDR | HYMOD_EEOFF_MAIN)) {
 689
 690                 if (read_eeprom
 691                         ("main", HYMOD_EEOFF_MAIN << 8, &cp->main.eeprom))
 692                         cp->main.eeprom_valid = 1;
 693
 694                 puts ("EEPROM:main...");
 695
 696                 if (cp->main.eeprom_valid) {
 697                         printf ("OK (ver %u)\n", cp->main.eeprom.ver);
 698                         eeprom_print (&cp->main.eeprom);
 699                         main_serno = cp->main.eeprom.serno;
 700                 } else
 701                         puts ("BAD\n");
 702
 703                 cp->main.mmap[0].prog.exists = 1;
 704                 cp->main.mmap[0].prog.size = FPGA_MAIN_CFG_SIZE;
 705                 cp->main.mmap[0].prog.base = FPGA_MAIN_CFG_BASE;
 706
 707                 cp->main.mmap[0].reg.exists = 1;
 708                 cp->main.mmap[0].reg.size = FPGA_MAIN_REG_SIZE;
 709                 cp->main.mmap[0].reg.base = FPGA_MAIN_REG_BASE;
 710
 711                 cp->main.mmap[0].port.exists = 1;
 712                 cp->main.mmap[0].port.size = FPGA_MAIN_PORT_SIZE;
 713                 cp->main.mmap[0].port.base = FPGA_MAIN_PORT_BASE;
 714
 715                 cp->main.iopins[0].prog_pin.port = FPGA_MAIN_PROG_PORT;
 716                 cp->main.iopins[0].prog_pin.pin = FPGA_MAIN_PROG_PIN;
 717                 cp->main.iopins[0].prog_pin.flag = 1;
 718                 cp->main.iopins[0].init_pin.port = FPGA_MAIN_INIT_PORT;
 719                 cp->main.iopins[0].init_pin.pin = FPGA_MAIN_INIT_PIN;
 720                 cp->main.iopins[0].init_pin.flag = 1;
 721                 cp->main.iopins[0].done_pin.port = FPGA_MAIN_DONE_PORT;
 722                 cp->main.iopins[0].done_pin.pin = FPGA_MAIN_DONE_PIN;
 723                 cp->main.iopins[0].done_pin.flag = 1;
 724 #ifdef FPGA_MAIN_ENABLE_PORT
 725                 cp->main.iopins[0].enable_pin.port = FPGA_MAIN_ENABLE_PORT;
 726                 cp->main.iopins[0].enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
 727                 cp->main.iopins[0].enable_pin.flag = 1;
 728 #endif
 729         } else
 730                 puts ("EEPROM:main...NOT PRESENT\n");
 731
 732         /* set up mezzanine board config info */
 733
 734         if (i2c_probe (CFG_I2C_EEPROM_ADDR | HYMOD_EEOFF_MEZZ)) {
 735
 736                 if (read_eeprom
 737                         ("mezz", HYMOD_EEOFF_MEZZ << 8, &cp->mezz.eeprom))
 738                         cp->mezz.eeprom_valid = 1;
 739
 740                 puts ("EEPROM:mezz...");
 741
 742                 if (cp->mezz.eeprom_valid) {
 743                         printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
 744                         eeprom_print (&cp->mezz.eeprom);
 745                 } else
 746                         puts ("BAD\n");
 747
 748                 cp->mezz.mmap[0].prog.exists = 1;
 749                 cp->mezz.mmap[0].prog.size = FPGA_MEZZ_CFG_SIZE;
 750                 cp->mezz.mmap[0].prog.base = FPGA_MEZZ_CFG_BASE;
 751
 752                 cp->mezz.mmap[0].reg.exists = 0;
 753
 754                 cp->mezz.mmap[0].port.exists = 0;
 755
 756                 cp->mezz.iopins[0].prog_pin.port = FPGA_MEZZ_PROG_PORT;
 757                 cp->mezz.iopins[0].prog_pin.pin = FPGA_MEZZ_PROG_PIN;
 758                 cp->mezz.iopins[0].prog_pin.flag = 1;
 759                 cp->mezz.iopins[0].init_pin.port = FPGA_MEZZ_INIT_PORT;
 760                 cp->mezz.iopins[0].init_pin.pin = FPGA_MEZZ_INIT_PIN;
 761                 cp->mezz.iopins[0].init_pin.flag = 1;
 762                 cp->mezz.iopins[0].done_pin.port = FPGA_MEZZ_DONE_PORT;
 763                 cp->mezz.iopins[0].done_pin.pin = FPGA_MEZZ_DONE_PIN;
 764                 cp->mezz.iopins[0].done_pin.flag = 1;
 765 #ifdef FPGA_MEZZ_ENABLE_PORT
 766                 cp->mezz.iopins[0].enable_pin.port = FPGA_MEZZ_ENABLE_PORT;
 767                 cp->mezz.iopins[0].enable_pin.pin = FPGA_MEZZ_ENABLE_PIN;
 768                 cp->mezz.iopins[0].enable_pin.flag = 1;
 769 #endif
 770
 771                 if (cp->mezz.eeprom_valid &&
 772                         cp->mezz.eeprom.bdtype == HYMOD_BDTYPE_DISPLAY) {
 773                         /*
 774                          * mezzanine board is a display board - switch the SEL_CD
 775                          * input of the FS6377 clock generator (via I/O Port Pin PA11) to
 776                          * high (or 1) to select the 27MHz required by the display board
 777                          */
 778                         iopin_set_high (&pa11);
 779
 780                         puts ("SEL_CD:toggled for display board\n");
 781                 }
 782         } else
 783                 puts ("EEPROM:mezz...NOT PRESENT\n");
 784
 785         cp->crc =
 786                         crc32 (0, (unsigned char *) cp, offsetof (hymod_conf_t, crc));
 787
 788         if (getenv ("global_env_loaded") == NULL) {
 789
 790                 puts ("*** global environment has not been loaded\n");
 791                 puts ("*** fetching from server (Control-C to Abort)\n");
 792
 793                 rc = fetch_and_parse (global_env_path, 0x100000,
 794                                                           env_fetch_callback);
 795
 796                 if (rc == 0)
 797                         puts ("*** Fetch of environment failed!\n");
 798                 else
 799                         setenv ("global_env_loaded", "yes");
 800         }
 801         return (0);
 802 }