2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
39 #include <asm/arch/da8xx-fb.h>
41 #include "../common/karo.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
52 #define GMII_SEL (CTRL_BASE + 0x650)
55 #define UART_SYSCFG_OFFSET 0x54
56 #define UART_SYSSTS_OFFSET 0x58
58 #define UART_RESET (0x1 << 1)
59 #define UART_CLK_RUNNING_MASK 0x1
60 #define UART_SMART_IDLE_EN (0x1 << 0x3)
63 #define TSICR_REG 0x54
64 #define TIOCP_CFG_REG 0x10
67 /* RGMII mode define */
68 #define RGMII_MODE_ENABLE 0xA
69 #define RMII_MODE_ENABLE 0x5
70 #define MII_MODE_ENABLE 0x0
72 #define NO_OF_MAC_ADDR 1
75 /* PAD Control Fields */
76 #define SLEWCTRL (0x1 << 6)
77 #define RXACTIVE (0x1 << 5)
78 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
79 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
80 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
81 #define MODE(val) (val)
85 * Field names corresponds to the pad signal name
177 int ecap0_in_pwm0_out;
196 int xdma_event_intr0;
197 int xdma_event_intr1;
301 #define PAD_CTRL_BASE 0x800
302 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
306 * Configure the pin mux for the module
308 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
313 for (i = 0; i < num_pins; i++)
314 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
317 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
318 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
319 #define PRM_RSTST_WDT1_RST (1 << 4)
320 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
321 #define PRM_RSTST_ICEPICK_RST (1 << 9)
323 static u32 prm_rstst __attribute__((section(".data")));
326 * Basic board specific setup
328 static const struct pin_mux tx48_pads[] = {
329 { OFFSET(i2c0_sda), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
330 { OFFSET(i2c0_scl), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
333 static const struct pin_mux tx48_i2c_pads[] = {
334 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
335 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
338 static const struct gpio tx48_gpios[] = {
339 { AM33XX_GPIO_NR(3, 5), GPIOF_INPUT, "I2C1_SDA", },
340 { AM33XX_GPIO_NR(3, 6), GPIOF_INPUT, "I2C1_SCL", },
343 static const struct pin_mux stk5_pads[] = {
345 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
347 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
348 /* LCD POWER_ENABLE */
349 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
350 /* LCD Backlight (PWM) */
351 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
353 { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
356 static const struct gpio stk5_gpios[] = {
357 { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
358 { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", },
361 static const struct pin_mux stk5_lcd_pads[] = {
363 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
364 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
365 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
366 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
367 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
368 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
369 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
370 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
371 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
372 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
373 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
374 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
375 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
376 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
377 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
378 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
379 /* LCD control signals */
380 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
381 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
382 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
383 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
386 static const struct gpio stk5_lcd_gpios[] = {
387 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
388 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
389 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
392 static const struct pin_mux stk5v5_pads[] = {
393 /* CAN transceiver control */
394 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
397 static const struct gpio stk5v5_gpios[] = {
398 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
402 static u16 tx48_cmap[256];
403 vidinfo_t panel_info = {
404 /* set to max. size supported by SoC */
408 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
412 #define FB_SYNC_OE_LOW_ACT (1 << 31)
413 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
415 static struct fb_videomode tx48_fb_modes[] = {
417 /* Standard VGA timing */
422 .pixclock = KHZ2PICOS(25175),
429 .sync = FB_SYNC_CLK_LAT_FALL,
432 /* Emerging ETV570 640 x 480 display. Syncs low active,
433 * DE high active, 115.2 mm x 86.4 mm display area
434 * VGA compatible timing
440 .pixclock = KHZ2PICOS(25175),
447 .sync = FB_SYNC_CLK_LAT_FALL,
450 /* Emerging ET0350G0DH6 320 x 240 display.
451 * 70.08 mm x 52.56 mm display area.
457 .pixclock = KHZ2PICOS(6500),
458 .left_margin = 68 - 34,
461 .upper_margin = 18 - 3,
464 .sync = FB_SYNC_CLK_LAT_FALL,
467 /* Emerging ET0430G0DH6 480 x 272 display.
468 * 95.04 mm x 53.856 mm display area.
474 .pixclock = KHZ2PICOS(9000),
483 /* Emerging ET0500G0DH6 800 x 480 display.
484 * 109.6 mm x 66.4 mm display area.
490 .pixclock = KHZ2PICOS(33260),
491 .left_margin = 216 - 128,
493 .right_margin = 1056 - 800 - 216,
494 .upper_margin = 35 - 2,
496 .lower_margin = 525 - 480 - 35,
497 .sync = FB_SYNC_CLK_LAT_FALL,
500 /* Emerging ETQ570G0DH6 320 x 240 display.
501 * 115.2 mm x 86.4 mm display area.
507 .pixclock = KHZ2PICOS(6400),
511 .upper_margin = 16, /* 15 according to datasheet */
512 .vsync_len = 3, /* TVP -> 1>x>5 */
513 .lower_margin = 4, /* 4.5 according to datasheet */
514 .sync = FB_SYNC_CLK_LAT_FALL,
517 /* Emerging ET0700G0DH6 800 x 480 display.
518 * 152.4 mm x 91.44 mm display area.
524 .pixclock = KHZ2PICOS(33260),
525 .left_margin = 216 - 128,
527 .right_margin = 1056 - 800 - 216,
528 .upper_margin = 35 - 2,
530 .lower_margin = 525 - 480 - 35,
531 .sync = FB_SYNC_CLK_LAT_FALL,
534 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
542 .sync = FB_SYNC_CLK_LAT_FALL,
546 void *lcd_base; /* Start of framebuffer memory */
547 void *lcd_console_address; /* Start of console buffer */
555 static int lcd_enabled = 1;
556 static int lcd_bl_polarity;
558 static int lcd_backlight_polarity(void)
560 return lcd_bl_polarity;
563 void lcd_initcolregs(void)
567 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
571 void lcd_enable(void)
574 * global variable from common/lcd.c
575 * Set to 0 here to prevent messages from going to LCD
576 * rather than serial console
581 karo_load_splashimage(1);
583 debug("Switching LCD on\n");
584 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
586 gpio_set_value(TX48_LCD_RST_GPIO, 1);
588 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
589 lcd_backlight_polarity());
593 void lcd_disable(void)
596 printf("Disabling LCD\n");
602 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
603 struct fb_videomode *fb)
605 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
608 p->hbp = fb->left_margin;
609 p->hsw = fb->hsync_len;
610 p->hfp = fb->right_margin;
612 p->height = fb->yres;
613 p->vbp = fb->upper_margin;
614 p->vsw = fb->vsync_len;
615 p->vfp = fb->lower_margin;
617 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
620 void lcd_panel_disable(void)
623 debug("Switching LCD off\n");
624 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
625 !lcd_backlight_polarity());
626 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
627 gpio_set_value(TX48_LCD_RST_GPIO, 0);
631 void lcd_ctrl_init(void *lcdbase)
633 int color_depth = 24;
634 const char *video_mode = karo_get_vmode(getenv("video_mode"));
638 struct fb_videomode *p = &tx48_fb_modes[0];
639 struct fb_videomode fb_mode;
640 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
643 debug("LCD disabled\n");
647 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
648 debug("Disabling LCD\n");
650 setenv("splashimage", NULL);
655 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
657 if (video_mode == NULL) {
658 debug("Disabling LCD\n");
663 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
665 debug("Using video mode from FDT\n");
667 if (fb_mode.xres > panel_info.vl_col ||
668 fb_mode.yres > panel_info.vl_row) {
669 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
670 fb_mode.xres, fb_mode.yres,
671 panel_info.vl_col, panel_info.vl_row);
677 debug("Trying compiled-in video modes\n");
678 while (p->name != NULL) {
679 if (strcmp(p->name, vm) == 0) {
680 debug("Using video mode: '%s'\n", p->name);
687 debug("Trying to decode video_mode: '%s'\n", vm);
688 while (*vm != '\0') {
689 if (*vm >= '0' && *vm <= '9') {
692 val = simple_strtoul(vm, &end, 0);
695 if (val > panel_info.vl_col)
696 val = panel_info.vl_col;
698 panel_info.vl_col = val;
700 } else if (!yres_set) {
701 if (val > panel_info.vl_row)
702 val = panel_info.vl_row;
704 panel_info.vl_row = val;
706 } else if (!bpp_set) {
715 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
716 end - vm, vm, color_depth);
719 } else if (!refresh_set) {
746 if (p->xres == 0 || p->yres == 0) {
747 printf("Invalid video mode: %s\n", getenv("video_mode"));
749 printf("Supported video modes are:");
750 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
751 printf(" %s", p->name);
756 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
757 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
758 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
762 panel_info.vl_col = p->xres;
763 panel_info.vl_row = p->yres;
765 switch (color_depth) {
767 panel_info.vl_bpix = LCD_COLOR8;
770 panel_info.vl_bpix = LCD_COLOR16;
773 panel_info.vl_bpix = LCD_COLOR24;
776 p->pixclock = KHZ2PICOS(refresh *
777 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
778 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
780 debug("Pixel clock set to %lu.%03lu MHz\n",
781 PICOS2KHZ(p->pixclock) / 1000,
782 PICOS2KHZ(p->pixclock) % 1000);
787 debug("Creating new display-timing node from '%s'\n",
789 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
791 printf("Failed to create new display-timing node from '%s': %d\n",
795 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
796 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
798 if (karo_load_splashimage(0) == 0) {
799 struct da8xx_panel da8xx_panel = { };
801 debug("Initializing FB driver\n");
802 tx48_lcd_panel_setup(&da8xx_panel, p);
803 da8xx_video_init(&da8xx_panel, color_depth);
805 debug("Initializing LCD controller\n");
808 debug("Skipping initialization of LCD controller\n");
812 #define lcd_enabled 0
813 #endif /* CONFIG_LCD */
815 static void stk5_board_init(void)
817 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
818 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
821 static void stk5v3_board_init(void)
826 static void stk5v5_board_init(void)
830 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
831 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
834 /* called with default environment! */
839 /* mach type passed to kernel */
840 #ifdef CONFIG_OF_LIBFDT
841 gd->bd->bi_arch_number = -1;
843 /* address of boot parameters */
844 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
847 printf("CTRL-C detected\n");
849 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
850 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_pads));
852 for (i = 0; i < ARRAY_SIZE(tx48_gpios); i++) {
853 int gpio = tx48_gpios[i].gpio;
855 if (gpio_get_value(gpio) == 0)
856 gpio_direction_output(gpio, 1);
859 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_i2c_pads));
863 static void show_reset_cause(u32 prm_rstst)
865 const char *dlm = "";
867 printf("RESET cause: ");
868 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
869 printf("%sPOR", dlm);
872 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
876 if (prm_rstst & PRM_RSTST_WDT1_RST) {
877 printf("%sWATCHDOG", dlm);
880 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
881 printf("%sWARM", dlm);
884 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
885 printf("%sJTAG", dlm);
894 /* called with default environment! */
897 prm_rstst = readl(PRM_RSTST);
898 show_reset_cause(prm_rstst);
900 printf("Board: Ka-Ro TX48-7020\n");
906 static void tx48_set_cpu_clock(void)
908 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
909 unsigned long act_cpu_clk;
911 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
914 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
915 if (prm_rstst & PRM_RSTST_WDT1_RST) {
916 printf("Watchdog reset detected; skipping cpu clock change\n");
918 printf("<CTRL-C> detected; skipping cpu clock change\n");
923 mpu_pll_config_val(cpu_clk);
925 act_cpu_clk = mpu_clk_rate();
926 if (cpu_clk * 1000000 != act_cpu_clk) {
927 printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
928 cpu_clk, act_cpu_clk / 1000000,
929 act_cpu_clk / 1000 % 1000);
931 printf("CPU clock set to %lu.%03lu MHz\n",
932 act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
936 static void tx48_init_mac(void)
938 uint8_t mac_addr[ETH_ALEN];
939 uint32_t mac_hi, mac_lo;
941 /* try reading mac address from efuse */
942 mac_lo = __raw_readl(MAC_ID0_LO);
943 mac_hi = __raw_readl(MAC_ID0_HI);
945 mac_addr[0] = mac_hi & 0xFF;
946 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
947 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
948 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
949 mac_addr[4] = mac_lo & 0xFF;
950 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
952 if (!is_valid_ether_addr(mac_addr)) {
953 printf("No valid MAC address programmed\n");
956 printf("MAC addr from fuse: %pM\n", mac_addr);
957 eth_setenv_enetaddr("ethaddr", mac_addr);
960 /* called with environment from NAND or MMC */
961 int board_late_init(void)
964 const char *baseboard;
966 tx48_set_cpu_clock();
969 baseboard = getenv("baseboard");
973 if (strncmp(baseboard, "stk5", 4) == 0) {
974 printf("Baseboard: %s\n", baseboard);
975 if ((strlen(baseboard) == 4) ||
976 strcmp(baseboard, "stk5-v3") == 0) {
978 } else if (strcmp(baseboard, "stk5-v5") == 0) {
981 printf("WARNING: Unsupported STK5 board rev.: %s\n",
985 printf("WARNING: Unsupported baseboard: '%s'\n",
996 #ifdef CONFIG_DRIVER_TI_CPSW
997 static void tx48_phy_init(char *name, int addr)
999 debug("%s: Resetting ethernet PHY\n", __func__);
1001 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
1006 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
1008 /* Wait for PHY internal POR signal to deassert */
1012 static void cpsw_control(int enabled)
1014 /* nothing for now */
1015 /* TODO : VTP was here before */
1018 static struct cpsw_slave_data cpsw_slaves[] = {
1020 .slave_reg_ofs = 0x208,
1021 .sliver_reg_ofs = 0xd80,
1023 .phy_if = PHY_INTERFACE_MODE_RMII,
1029 /* Nothing to be done here */
1032 static struct cpsw_platform_data cpsw_data = {
1033 .mdio_base = CPSW_MDIO_BASE,
1034 .cpsw_base = CPSW_BASE,
1037 .cpdma_reg_ofs = 0x800,
1038 .slaves = ARRAY_SIZE(cpsw_slaves),
1039 .slave_data = cpsw_slaves,
1040 .ale_reg_ofs = 0xd00,
1041 .ale_entries = 1024,
1042 .host_port_reg_ofs = 0x108,
1043 .hw_stats_reg_ofs = 0x900,
1044 .mac_control = (1 << 5) /* MIIEN */,
1045 .control = cpsw_control,
1046 .phy_init = tx48_phy_init,
1049 .version = CPSW_CTRL_VERSION_2,
1052 int board_eth_init(bd_t *bis)
1054 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1055 __raw_writel(0x5D, GMII_SEL);
1056 return cpsw_register(&cpsw_data);
1058 #endif /* CONFIG_DRIVER_TI_CPSW */
1060 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
1061 int cpu_mmc_init(bd_t *bis)
1063 return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
1067 void tx48_disable_watchdog(void)
1069 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1071 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1073 writel(0xaaaa, &wdtimer->wdtwspr);
1074 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1076 writel(0x5555, &wdtimer->wdtwspr);
1080 LED_STATE_INIT = -1,
1085 void show_activity(int arg)
1087 static int led_state = LED_STATE_INIT;
1090 if (led_state == LED_STATE_INIT) {
1091 last = get_timer(0);
1092 gpio_set_value(TX48_LED_GPIO, 1);
1093 led_state = LED_STATE_ON;
1095 if (get_timer(last) > CONFIG_SYS_HZ) {
1096 last = get_timer(0);
1097 if (led_state == LED_STATE_ON) {
1098 gpio_set_value(TX48_LED_GPIO, 0);
1100 gpio_set_value(TX48_LED_GPIO, 1);
1102 led_state = 1 - led_state;
1107 #ifdef CONFIG_OF_BOARD_SETUP
1108 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1109 #include <jffs2/jffs2.h>
1110 #include <mtd_node.h>
1111 static struct node_info nodes[] = {
1112 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1113 { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
1117 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1118 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1120 static const char *tx48_touchpanels[] = {
1126 void ft_board_setup(void *blob, bd_t *bd)
1128 const char *baseboard = getenv("baseboard");
1129 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1130 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1133 ret = fdt_increase_size(blob, 4096);
1135 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1137 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1138 fdt_fixup_ethernet(blob);
1140 karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
1141 ARRAY_SIZE(tx48_touchpanels));
1142 karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
1143 karo_fdt_fixup_flexcan(blob, stk5_v5);
1145 karo_fdt_update_fb_mode(blob, video_mode);
1147 tx48_disable_watchdog();
1149 #endif /* CONFIG_OF_BOARD_SETUP */