board/ti/beagle_x15/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/dra7xx_iodelay.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sata.h>
  22 #include <asm/arch/gpio.h>
  23 #include <environment.h>
  24
  25 #include "mux_data.h"
  26
  27 #ifdef CONFIG_DRIVER_TI_CPSW
  28 #include <cpsw.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 const struct omap_sysinfo sysinfo = {
  34         "Board: BeagleBoard x15\n"
  35 };
  36
  37 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  38         .dmm_lisa_map_3 = 0x80740300,
  39         .is_ma_present  = 0x1
  40 };
  41
  42 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  43 {
  44         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  45 }
  46
  47 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  48         .sdram_config_init      = 0x61851b32,
  49         .sdram_config           = 0x61851b32,
  50         .sdram_config2          = 0x00000000,
  51         .ref_ctrl               = 0x000040F1,
  52         .ref_ctrl_final         = 0x00001035,
  53         .sdram_tim1             = 0xceef266b,
  54         .sdram_tim2             = 0x328f7fda,
  55         .sdram_tim3             = 0x027f88a8,
  56         .read_idle_ctrl         = 0x00050000,
  57         .zq_config              = 0x0007190b,
  58         .temp_alert_config      = 0x00000000,
  59         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  60         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  61         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  62         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  63         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  64         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  65         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  66         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  67         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  68         .emif_rd_wr_lvl_ctl     = 0x00000000,
  69         .emif_rd_wr_exec_thresh = 0x00000305
  70 };
  71
  72 /* Ext phy ctrl regs 1-35 */
  73 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  74         0x10040100,
  75         0x00740074,
  76         0x00780078,
  77         0x007c007c,
  78         0x007b007b,
  79         0x00800080,
  80         0x00360036,
  81         0x00340034,
  82         0x00360036,
  83         0x00350035,
  84         0x00350035,
  85
  86         0x01ff01ff,
  87         0x01ff01ff,
  88         0x01ff01ff,
  89         0x01ff01ff,
  90         0x01ff01ff,
  91
  92         0x00430043,
  93         0x003e003e,
  94         0x004a004a,
  95         0x00470047,
  96         0x00400040,
  97
  98         0x00000000,
  99         0x00600020,
 100         0x40011080,
 101         0x08102040,
 102
 103         0x00400040,
 104         0x00400040,
 105         0x00400040,
 106         0x00400040,
 107         0x00400040,
 108         0x0,
 109         0x0,
 110         0x0,
 111         0x0,
 112         0x0
 113 };
 114
 115 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 116         .sdram_config_init      = 0x61851b32,
 117         .sdram_config           = 0x61851b32,
 118         .sdram_config2          = 0x00000000,
 119         .ref_ctrl               = 0x000040F1,
 120         .ref_ctrl_final         = 0x00001035,
 121         .sdram_tim1             = 0xceef266b,
 122         .sdram_tim2             = 0x328f7fda,
 123         .sdram_tim3             = 0x027f88a8,
 124         .read_idle_ctrl         = 0x00050000,
 125         .zq_config              = 0x0007190b,
 126         .temp_alert_config      = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 128         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 129         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 130         .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
 131         .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
 132         .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
 133         .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
 134         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 136         .emif_rd_wr_lvl_ctl     = 0x00000000,
 137         .emif_rd_wr_exec_thresh = 0x00000305
 138 };
 139
 140 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 141         0x10040100,
 142         0x00820082,
 143         0x008b008b,
 144         0x00800080,
 145         0x007e007e,
 146         0x00800080,
 147         0x00370037,
 148         0x00390039,
 149         0x00360036,
 150         0x00370037,
 151         0x00350035,
 152         0x01ff01ff,
 153         0x01ff01ff,
 154         0x01ff01ff,
 155         0x01ff01ff,
 156         0x01ff01ff,
 157         0x00540054,
 158         0x00540054,
 159         0x004e004e,
 160         0x004c004c,
 161         0x00400040,
 162
 163         0x00000000,
 164         0x00600020,
 165         0x40011080,
 166         0x08102040,
 167
 168         0x00400040,
 169         0x00400040,
 170         0x00400040,
 171         0x00400040,
 172         0x00400040,
 173         0x0,
 174         0x0,
 175         0x0,
 176         0x0,
 177         0x0
 178 };
 179
 180 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 181 {
 182         switch (emif_nr) {
 183         case 1:
 184                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 185                 break;
 186         case 2:
 187                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 188                 break;
 189         }
 190 }
 191
 192 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 193 {
 194         switch (emif_nr) {
 195         case 1:
 196                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 197                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 198                 break;
 199         case 2:
 200                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 201                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 202                 break;
 203         }
 204 }
 205
 206 struct vcores_data beagle_x15_volts = {
 207         .mpu.value              = VDD_MPU_DRA752,
 208         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU_NOM,
 209         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 210         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 211         .mpu.pmic               = &tps659038,
 212
 213         .eve.value              = VDD_EVE_DRA752,
 214         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 215         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 216         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 217         .eve.pmic               = &tps659038,
 218
 219         .gpu.value              = VDD_GPU_DRA752,
 220         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU_NOM,
 221         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 222         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 223         .gpu.pmic               = &tps659038,
 224
 225         .core.value             = VDD_CORE_DRA752,
 226         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE_NOM,
 227         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 228         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 229         .core.pmic              = &tps659038,
 230
 231         .iva.value              = VDD_IVA_DRA752,
 232         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA_NOM,
 233         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 234         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 235         .iva.pmic               = &tps659038,
 236 };
 237
 238 void hw_data_init(void)
 239 {
 240         *prcm = &dra7xx_prcm;
 241         *dplls_data = &dra7xx_dplls;
 242         *omap_vcores = &beagle_x15_volts;
 243         *ctrl = &dra7xx_ctrl;
 244 }
 245
 246 int board_init(void)
 247 {
 248         gpmc_init();
 249         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 250
 251         return 0;
 252 }
 253
 254 int board_late_init(void)
 255 {
 256         init_sata(0);
 257         /*
 258          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 259          * This is the POWERHOLD-in-Low behavior.
 260          */
 261         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 262         return 0;
 263 }
 264
 265 void set_muxconf_regs_essential(void)
 266 {
 267         do_set_mux32((*ctrl)->control_padconf_core_base,
 268                      early_padconf, ARRAY_SIZE(early_padconf));
 269 }
 270
 271 #ifdef CONFIG_IODELAY_RECALIBRATION
 272 void recalibrate_iodelay(void)
 273 {
 274         __recalibrate_iodelay(core_padconf_array_essential,
 275                               ARRAY_SIZE(core_padconf_array_essential),
 276                               iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
 277 }
 278 #endif
 279
 280 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 281 int board_mmc_init(bd_t *bis)
 282 {
 283         omap_mmc_init(0, 0, 0, -1, -1);
 284         omap_mmc_init(1, 0, 0, -1, -1);
 285         return 0;
 286 }
 287 #endif
 288
 289 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 290 int spl_start_uboot(void)
 291 {
 292         /* break into full u-boot on 'c' */
 293         if (serial_tstc() && serial_getc() == 'c')
 294                 return 1;
 295
 296 #ifdef CONFIG_SPL_ENV_SUPPORT
 297         env_init();
 298         env_relocate_spec();
 299         if (getenv_yesno("boot_os") != 1)
 300                 return 1;
 301 #endif
 302
 303         return 0;
 304 }
 305 #endif
 306
 307 #ifdef CONFIG_DRIVER_TI_CPSW
 308
 309 /* Delay value to add to calibrated value */
 310 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 311 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 312 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 313 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 314 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 315 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 316 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 317 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 318 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 319 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 320
 321 static void cpsw_control(int enabled)
 322 {
 323         /* VTP can be added here */
 324 }
 325
 326 static struct cpsw_slave_data cpsw_slaves[] = {
 327         {
 328                 .slave_reg_ofs  = 0x208,
 329                 .sliver_reg_ofs = 0xd80,
 330                 .phy_addr       = 1,
 331         },
 332         {
 333                 .slave_reg_ofs  = 0x308,
 334                 .sliver_reg_ofs = 0xdc0,
 335                 .phy_addr       = 2,
 336         },
 337 };
 338
 339 static struct cpsw_platform_data cpsw_data = {
 340         .mdio_base              = CPSW_MDIO_BASE,
 341         .cpsw_base              = CPSW_BASE,
 342         .mdio_div               = 0xff,
 343         .channels               = 8,
 344         .cpdma_reg_ofs          = 0x800,
 345         .slaves                 = 1,
 346         .slave_data             = cpsw_slaves,
 347         .ale_reg_ofs            = 0xd00,
 348         .ale_entries            = 1024,
 349         .host_port_reg_ofs      = 0x108,
 350         .hw_stats_reg_ofs       = 0x900,
 351         .bd_ram_ofs             = 0x2000,
 352         .mac_control            = (1 << 5),
 353         .control                = cpsw_control,
 354         .host_port_num          = 0,
 355         .version                = CPSW_CTRL_VERSION_2,
 356 };
 357
 358 int board_eth_init(bd_t *bis)
 359 {
 360         int ret;
 361         uint8_t mac_addr[6];
 362         uint32_t mac_hi, mac_lo;
 363         uint32_t ctrl_val;
 364
 365         /* try reading mac address from efuse */
 366         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 367         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 368         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 369         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 370         mac_addr[2] = mac_hi & 0xFF;
 371         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 372         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 373         mac_addr[5] = mac_lo & 0xFF;
 374
 375         if (!getenv("ethaddr")) {
 376                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 377
 378                 if (is_valid_ethaddr(mac_addr))
 379                         eth_setenv_enetaddr("ethaddr", mac_addr);
 380         }
 381
 382         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 383         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 384         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 385         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 386         mac_addr[2] = mac_hi & 0xFF;
 387         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 388         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 389         mac_addr[5] = mac_lo & 0xFF;
 390
 391         if (!getenv("eth1addr")) {
 392                 if (is_valid_ethaddr(mac_addr))
 393                         eth_setenv_enetaddr("eth1addr", mac_addr);
 394         }
 395
 396         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 397         ctrl_val |= 0x22;
 398         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 399
 400         ret = cpsw_register(&cpsw_data);
 401         if (ret < 0)
 402                 printf("Error %d registering CPSW switch\n", ret);
 403
 404         return ret;
 405 }
 406 #endif