cpu/mpc8xx/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  *
  26  * Back ported to the 8xx platform (from the 8260 platform) by
  27  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  28  */
  29
  30 #include <common.h>
  31
  32 #ifdef CONFIG_HARD_I2C
  33
  34 #include <commproc.h>
  35 #include <i2c.h>
  36 #ifdef CONFIG_LWMON
  37 #include <watchdog.h>
  38 #endif
  39
  40 /* define to enable debug messages */
  41 #undef  DEBUG_I2C
  42
  43 /*-----------------------------------------------------------------------
  44  * Set default values
  45  */
  46 #ifndef CFG_I2C_SPEED
  47 #define CFG_I2C_SPEED   50000
  48 #endif
  49
  50 #ifndef CFG_I2C_SLAVE
  51 #define CFG_I2C_SLAVE   0xFE
  52 #endif
  53 /*-----------------------------------------------------------------------
  54  */
  55
  56 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
  57 #define TOUT_LOOP 1000000
  58
  59 #define NUM_RX_BDS 4
  60 #define NUM_TX_BDS 4
  61 #define MAX_TX_SPACE 256
  62 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
  63
  64 typedef struct I2C_BD
  65 {
  66   unsigned short status;
  67   unsigned short length;
  68   unsigned char *addr;
  69 } I2C_BD;
  70 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
  71
  72 #define BD_I2C_TX_CL    0x0001  /* collision error */
  73 #define BD_I2C_TX_UN    0x0002  /* underflow error */
  74 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
  75 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
  76
  77 #define BD_I2C_RX_ERR   BD_SC_OV
  78
  79 typedef void (*i2c_ecb_t)(int, int);    /* error callback function */
  80
  81 /* This structure keeps track of the bd and buffer space usage. */
  82 typedef struct i2c_state {
  83         int             rx_idx;         /* index   to next free Rx BD */
  84         int             tx_idx;         /* index   to next free Tx BD */
  85         void            *rxbd;          /* pointer to next free Rx BD */
  86         void            *txbd;          /* pointer to next free Tx BD */
  87         int             tx_space;       /* number  of Tx bytes left   */
  88         unsigned char   *tx_buf;        /* pointer to free Tx area    */
  89         i2c_ecb_t       err_cb;         /* error callback function    */
  90 } i2c_state_t;
  91
  92
  93 /* flags for i2c_send() and i2c_receive() */
  94 #define I2CF_ENABLE_SECONDARY   0x01    /* secondary_address is valid           */
  95 #define I2CF_START_COND         0x02    /* tx: generate start condition         */
  96 #define I2CF_STOP_COND          0x04    /* tx: generate stop  condition         */
  97
  98 /* return codes */
  99 #define I2CERR_NO_BUFFERS       0x01    /* no more BDs or buffer space          */
 100 #define I2CERR_MSG_TOO_LONG     0x02    /* tried to send/receive to much data   */
 101 #define I2CERR_TIMEOUT          0x03    /* timeout in i2c_doio()                */
 102 #define I2CERR_QUEUE_EMPTY      0x04    /* i2c_doio called without send/receive */
 103
 104 /* error callback flags */
 105 #define I2CECB_RX_ERR           0x10    /* this is a receive error              */
 106 #define     I2CECB_RX_ERR_OV    0x02    /* receive overrun error                */
 107 #define     I2CECB_RX_MASK      0x0f    /* mask for error bits                  */
 108 #define I2CECB_TX_ERR           0x20    /* this is a transmit error             */
 109 #define     I2CECB_TX_CL        0x01    /* transmit collision error             */
 110 #define     I2CECB_TX_UN        0x02    /* transmit underflow error             */
 111 #define     I2CECB_TX_NAK       0x04    /* transmit no ack error                */
 112 #define     I2CECB_TX_MASK      0x0f    /* mask for error bits                  */
 113 #define I2CECB_TIMEOUT          0x40    /* this is a timeout error              */
 114
 115 #ifdef DEBUG_I2C
 116 #define PRINTD(x) printf x
 117 #else
 118 #define PRINTD(x)
 119 #endif
 120
 121 /*
 122  * Returns the best value of I2BRG to meet desired clock speed of I2C with
 123  * input parameters (clock speed, filter, and predivider value).
 124  * It returns computer speed value and the difference between it and desired
 125  * speed.
 126  */
 127 static inline int
 128 i2c_roundrate(int hz, int speed, int filter, int modval,
 129                 int *brgval, int *totspeed)
 130 {
 131     int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
 132
 133     PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
 134         hz, speed, filter, modval));
 135
 136     div = moddiv * speed;
 137     brgdiv = (hz + div - 1) / div;
 138
 139     PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
 140
 141     *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
 142
 143     if ((*brgval < 0) || (*brgval > 255)) {
 144           PRINTD(("\t\trejected brgval=%d\n", *brgval));
 145           return -1;
 146     }
 147
 148     brgdiv = 2 * (*brgval + 3 + (2 * filter));
 149     div = moddiv * brgdiv ;
 150     *totspeed = hz / div;
 151
 152     PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
 153
 154     return  0;
 155 }
 156
 157 /*
 158  * Sets the I2C clock predivider and divider to meet required clock speed.
 159  */
 160 static int
 161 i2c_setrate (int hz, int speed)
 162 {
 163         immap_t         *immap = (immap_t *) CFG_IMMR;
 164         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
 165         int             brgval,
 166                         modval,         /* 0-3 */
 167                         bestspeed_diff = speed,
 168                         bestspeed_brgval = 0,
 169                         bestspeed_modval = 0,
 170                         bestspeed_filter = 0,
 171                         totspeed,
 172                         filter = 0;     /* Use this fixed value */
 173
 174         for (modval = 0; modval < 4; modval++) {
 175                 if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) {
 176                         int diff = speed - totspeed;
 177
 178                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 179                                 bestspeed_diff = diff;
 180                                 bestspeed_modval = modval;
 181                                 bestspeed_brgval = brgval;
 182                                 bestspeed_filter = filter;
 183                         }
 184                 }
 185         }
 186
 187         PRINTD (("[I2C] Best is:\n"));
 188         PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 189                 hz,
 190                 speed,
 191                 bestspeed_filter,
 192                 bestspeed_modval,
 193                 bestspeed_brgval,
 194                 bestspeed_diff));
 195
 196         i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 197         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 198
 199         PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
 200                          i2c->i2c_i2brg));
 201
 202         return 1;
 203 }
 204
 205 void
 206 i2c_init(int speed, int slaveaddr)
 207 {
 208         DECLARE_GLOBAL_DATA_PTR;
 209
 210         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
 211         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 212         volatile i2c8xx_t *i2c  = (i2c8xx_t *)&immap->im_i2c;
 213         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 214         ulong rbase, tbase;
 215         volatile I2C_BD *rxbd, *txbd;
 216         uint dpaddr;
 217
 218 #ifdef CFG_I2C_UCODE_PATCH
 219         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 220 #else
 221         /* Disable relocation */
 222         iip->iic_rpbase = 0;
 223 #endif
 224
 225 #ifdef CFG_ALLOC_DPRAM
 226         dpaddr = iip->iic_rbase;
 227         if (dpaddr == 0) {
 228             /* need to allocate dual port ram */
 229             dpaddr = dpram_alloc_align(
 230                 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
 231                 MAX_TX_SPACE, 8);
 232         }
 233 #else
 234         dpaddr = CPM_I2C_BASE;
 235 #endif
 236
 237         /*
 238          * initialise data in dual port ram:
 239          *
 240          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 241          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 242          *                  tx buffer     (MAX_TX_SPACE bytes)
 243          */
 244
 245         rbase = dpaddr;
 246         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 247
 248         /* Initialize Port B I2C pins. */
 249         cp->cp_pbpar |= 0x00000030;
 250         cp->cp_pbdir |= 0x00000030;
 251         cp->cp_pbodr |= 0x00000030;
 252
 253         /* Disable interrupts */
 254         i2c->i2c_i2mod = 0x00;
 255         i2c->i2c_i2cmr = 0x00;
 256         i2c->i2c_i2cer = 0xff;
 257         i2c->i2c_i2add = slaveaddr;
 258
 259         /*
 260          * Set the I2C BRG Clock division factor from desired i2c rate
 261          * and current CPU rate (we assume sccr dfbgr field is 0;
 262          * divide BRGCLK by 1)
 263          */
 264         PRINTD(("[I2C] Setting rate...\n"));
 265         i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
 266
 267         /* Set I2C controller in master mode */
 268         i2c->i2c_i2com = 0x01;
 269
 270         /* Set SDMA bus arbitration level to 5 (SDCR) */
 271         immap->im_siu_conf.sc_sdcr = 0x0001 ;
 272
 273         /* Initialize Tx/Rx parameters */
 274         iip->iic_rbase = rbase;
 275         iip->iic_tbase = tbase;
 276         rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
 277         txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
 278
 279         PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
 280         PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
 281         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
 282         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 283
 284         /* Set big endian byte order */
 285         iip->iic_tfcr = 0x10;
 286         iip->iic_rfcr = 0x10;
 287
 288         /* Set maximum receive size. */
 289         iip->iic_mrblr = I2C_RXTX_LEN;
 290
 291 #ifdef CFG_I2C_UCODE_PATCH
 292         /*
 293          *  Initialize required parameters if using microcode patch.
 294          */
 295         iip->iic_rbptr  = iip->iic_rbase;
 296         iip->iic_tbptr  = iip->iic_tbase;
 297         iip->iic_rstate = 0;
 298         iip->iic_tstate = 0;
 299 #else
 300         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 301         do {
 302                 __asm__ __volatile__ ("eieio");
 303         } while (cp->cp_cpcr & CPM_CR_FLG);
 304 #endif
 305
 306         /* Clear events and interrupts */
 307         i2c->i2c_i2cer = 0xff;
 308         i2c->i2c_i2cmr = 0x00;
 309 }
 310
 311 static void
 312 i2c_newio(i2c_state_t *state)
 313 {
 314         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
 315         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 316         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 317
 318         PRINTD(("[I2C] i2c_newio\n"));
 319
 320 #ifdef CFG_I2C_UCODE_PATCH
 321         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 322 #endif
 323         state->rx_idx = 0;
 324         state->tx_idx = 0;
 325         state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
 326         state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
 327         state->tx_space = MAX_TX_SPACE;
 328         state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 329         state->err_cb = NULL;
 330
 331         PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
 332         PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
 333         PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
 334
 335         /* clear the buffer memory */
 336         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 337 }
 338
 339 static int
 340 i2c_send(i2c_state_t *state,
 341          unsigned char address,
 342          unsigned char secondary_address,
 343          unsigned int flags,
 344          unsigned short size,
 345          unsigned char *dataout)
 346 {
 347         volatile I2C_BD *txbd;
 348         int i,j;
 349
 350         PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 351                         address, secondary_address, flags, size));
 352
 353         /* trying to send message larger than BD */
 354         if (size > I2C_RXTX_LEN)
 355           return I2CERR_MSG_TOO_LONG;
 356
 357         /* no more free bds */
 358         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 359           return I2CERR_NO_BUFFERS;
 360
 361         txbd = (I2C_BD *)state->txbd;
 362         txbd->addr = state->tx_buf;
 363
 364         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 365
 366         if (flags & I2CF_START_COND) {
 367                 PRINTD(("[I2C] Formatting addresses...\n"));
 368                 if (flags & I2CF_ENABLE_SECONDARY) {
 369                         txbd->length = size + 2;  /* Length of msg + dest addr */
 370                         txbd->addr[0] = address << 1;
 371                         txbd->addr[1] = secondary_address;
 372                         i = 2;
 373                 } else {
 374                         txbd->length = size + 1;  /* Length of msg + dest addr */
 375                         txbd->addr[0] = address << 1;  /* Write dest addr to BD */
 376                         i = 1;
 377                 }
 378         } else {
 379                 txbd->length = size;  /* Length of message */
 380                 i = 0;
 381         }
 382
 383         /* set up txbd */
 384         txbd->status = BD_SC_READY;
 385         if (flags & I2CF_START_COND)
 386           txbd->status |= BD_I2C_TX_START;
 387         if (flags & I2CF_STOP_COND)
 388           txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 389
 390         /* Copy data to send into buffer */
 391         PRINTD(("[I2C] copy data...\n"));
 392         for(j = 0; j < size; i++, j++)
 393           txbd->addr[i] = dataout[j];
 394
 395         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 396                    txbd->length,
 397                    txbd->status,
 398                    txbd->addr[0],
 399                    txbd->addr[1]));
 400
 401         /* advance state */
 402         state->tx_buf += txbd->length;
 403         state->tx_space -= txbd->length;
 404         state->tx_idx++;
 405         state->txbd = (void*)(txbd + 1);
 406
 407         return 0;
 408 }
 409
 410 static int
 411 i2c_receive(i2c_state_t *state,
 412             unsigned char address,
 413             unsigned char secondary_address,
 414             unsigned int flags,
 415             unsigned short size_to_expect,
 416             unsigned char *datain)
 417 {
 418         volatile I2C_BD *rxbd, *txbd;
 419
 420         PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
 421
 422         /* Expected to receive too much */
 423         if (size_to_expect > I2C_RXTX_LEN)
 424           return I2CERR_MSG_TOO_LONG;
 425
 426         /* no more free bds */
 427         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 428                  || state->tx_space < 2)
 429           return I2CERR_NO_BUFFERS;
 430
 431         rxbd = (I2C_BD *)state->rxbd;
 432         txbd = (I2C_BD *)state->txbd;
 433
 434         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
 435         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 436
 437         txbd->addr = state->tx_buf;
 438
 439         /* set up TXBD for destination address */
 440         if (flags & I2CF_ENABLE_SECONDARY) {
 441                 txbd->length = 2;
 442                 txbd->addr[0] = address << 1;   /* Write data */
 443                 txbd->addr[1] = secondary_address;  /* Internal address */
 444                 txbd->status = BD_SC_READY;
 445         } else {
 446                 txbd->length = 1 + size_to_expect;
 447                 txbd->addr[0] = (address << 1) | 0x01;
 448                 txbd->status = BD_SC_READY;
 449                 memset(&txbd->addr[1], 0, txbd->length);
 450         }
 451
 452         /* set up rxbd for reception */
 453         rxbd->status = BD_SC_EMPTY;
 454         rxbd->length = size_to_expect;
 455         rxbd->addr = datain;
 456
 457         txbd->status |= BD_I2C_TX_START;
 458         if (flags & I2CF_STOP_COND) {
 459                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 460                 rxbd->status |= BD_SC_WRAP;
 461         }
 462
 463         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 464                    txbd->length,
 465                    txbd->status,
 466                    txbd->addr[0],
 467                    txbd->addr[1]));
 468         PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 469                    rxbd->length,
 470                    rxbd->status,
 471                    rxbd->addr[0],
 472                    rxbd->addr[1]));
 473
 474         /* advance state */
 475         state->tx_buf += txbd->length;
 476         state->tx_space -= txbd->length;
 477         state->tx_idx++;
 478         state->txbd = (void*)(txbd + 1);
 479         state->rx_idx++;
 480         state->rxbd = (void*)(rxbd + 1);
 481
 482         return 0;
 483 }
 484
 485
 486 static int i2c_doio(i2c_state_t *state)
 487 {
 488         volatile immap_t *immap = (immap_t *)CFG_IMMR ;
 489         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 490         volatile i2c8xx_t *i2c  = (i2c8xx_t *)&immap->im_i2c;
 491         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 492         volatile I2C_BD *txbd, *rxbd;
 493         volatile int j = 0;
 494
 495         PRINTD(("[I2C] i2c_doio\n"));
 496
 497 #ifdef CFG_I2C_UCODE_PATCH
 498         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 499 #endif
 500
 501         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 502                 PRINTD(("[I2C] No I/O is queued\n"));
 503                 return I2CERR_QUEUE_EMPTY;
 504         }
 505
 506         iip->iic_rbptr = iip->iic_rbase;
 507         iip->iic_tbptr = iip->iic_tbase;
 508
 509         /* Enable I2C */
 510         PRINTD(("[I2C] Enabling I2C...\n"));
 511         i2c->i2c_i2mod |= 0x01;
 512
 513         /* Begin transmission */
 514         i2c->i2c_i2com |= 0x80;
 515
 516         /* Loop until transmit & receive completed */
 517
 518         if (state->tx_idx > 0) {
 519                 txbd = ((I2C_BD*)state->txbd) - 1;
 520                 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
 521                 while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
 522                         if (ctrlc()) {
 523                                 return (-1);
 524                         }
 525                         __asm__ __volatile__ ("eieio");
 526                 }
 527         }
 528
 529         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
 530                 rxbd = ((I2C_BD*)state->rxbd) - 1;
 531                 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
 532                 while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
 533                         if (ctrlc()) {
 534                                 return (-1);
 535                         }
 536                         __asm__ __volatile__ ("eieio");
 537                 }
 538         }
 539
 540         /* Turn off I2C */
 541         i2c->i2c_i2mod &= ~0x01;
 542
 543         if (state->err_cb != NULL) {
 544                 int n, i, b;
 545
 546                 /*
 547                  * if we have an error callback function, look at the
 548                  * error bits in the bd status and pass them back
 549                  */
 550
 551                 if ((n = state->tx_idx) > 0) {
 552                         for (i = 0; i < n; i++) {
 553                                 txbd = ((I2C_BD*)state->txbd) - (n - i);
 554                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
 555                                         (*state->err_cb)(I2CECB_TX_ERR|b, i);
 556                         }
 557                 }
 558
 559                 if ((n = state->rx_idx) > 0) {
 560                         for (i = 0; i < n; i++) {
 561                                 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
 562                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
 563                                         (*state->err_cb)(I2CECB_RX_ERR|b, i);
 564                         }
 565                 }
 566
 567                 if (j >= TOUT_LOOP)
 568                         (*state->err_cb)(I2CECB_TIMEOUT, 0);
 569         }
 570
 571         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
 572 }
 573
 574 static int had_tx_nak;
 575
 576 static void
 577 i2c_test_callback(int flags, int xnum)
 578 {
 579         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
 580                 had_tx_nak = 1;
 581 }
 582
 583 int i2c_probe(uchar chip)
 584 {
 585         i2c_state_t state;
 586         int rc;
 587         uchar buf[1];
 588
 589         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 590
 591         i2c_newio(&state);
 592
 593         state.err_cb = i2c_test_callback;
 594         had_tx_nak = 0;
 595
 596         rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
 597
 598         if (rc != 0)
 599                 return (rc);
 600
 601         rc = i2c_doio(&state);
 602
 603         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
 604                 return (rc);
 605
 606         return (had_tx_nak);
 607 }
 608
 609 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 610 {
 611         DECLARE_GLOBAL_DATA_PTR;
 612
 613         i2c_state_t state;
 614         uchar xaddr[4];
 615         int rc;
 616
 617 #ifdef CONFIG_LWMON
 618         WATCHDOG_RESET();
 619 #endif
 620
 621         xaddr[0] = (addr >> 24) & 0xFF;
 622         xaddr[1] = (addr >> 16) & 0xFF;
 623         xaddr[2] = (addr >>  8) & 0xFF;
 624         xaddr[3] =  addr        & 0xFF;
 625
 626 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 627         /*
 628          * EEPROM chips that implement "address overflow" are ones like
 629          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 630          * extra bits end up in the "chip address" bit slots.  This makes
 631          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 632          *
 633          * Note that we consider the length of the address field to still
 634          * be one byte because the extra address bits are hidden in the
 635          * chip address.
 636          */
 637          chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 638 #endif
 639
 640         i2c_newio(&state);
 641
 642         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
 643         if (rc != 0) {
 644                 if (gd->have_console)
 645                         printf("i2c_read: i2c_send failed (%d)\n", rc);
 646                 return 1;
 647         }
 648
 649         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 650         if (rc != 0) {
 651                 if (gd->have_console)
 652                         printf("i2c_read: i2c_receive failed (%d)\n", rc);
 653                 return 1;
 654         }
 655
 656         rc = i2c_doio(&state);
 657         if (rc != 0) {
 658                 if (gd->have_console)
 659                         printf("i2c_read: i2c_doio failed (%d)\n", rc);
 660                 return 1;
 661         }
 662         return 0;
 663 }
 664
 665 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 666 {
 667         DECLARE_GLOBAL_DATA_PTR;
 668
 669         i2c_state_t state;
 670         uchar xaddr[4];
 671         int rc;
 672
 673         xaddr[0] = (addr >> 24) & 0xFF;
 674         xaddr[1] = (addr >> 16) & 0xFF;
 675         xaddr[2] = (addr >>  8) & 0xFF;
 676         xaddr[3] =  addr        & 0xFF;
 677
 678 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 679         /*
 680          * EEPROM chips that implement "address overflow" are ones like
 681          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 682          * extra bits end up in the "chip address" bit slots.  This makes
 683          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 684          *
 685          * Note that we consider the length of the address field to still
 686          * be one byte because the extra address bits are hidden in the
 687          * chip address.
 688          */
 689          chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 690 #endif
 691
 692         i2c_newio(&state);
 693
 694         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
 695         if (rc != 0) {
 696                 if (gd->have_console)
 697                         printf("i2c_write: first i2c_send failed (%d)\n", rc);
 698                 return 1;
 699         }
 700
 701         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 702         if (rc != 0) {
 703                 if (gd->have_console)
 704                         printf("i2c_write: second i2c_send failed (%d)\n", rc);
 705                 return 1;
 706         }
 707
 708         rc = i2c_doio(&state);
 709         if (rc != 0) {
 710                 if (gd->have_console)
 711                         printf("i2c_write: i2c_doio failed (%d)\n", rc);
 712                 return 1;
 713         }
 714         return 0;
 715 }
 716
 717 uchar
 718 i2c_reg_read(uchar i2c_addr, uchar reg)
 719 {
 720         char buf;
 721
 722         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 723
 724         i2c_read(i2c_addr, reg, 1, &buf, 1);
 725
 726         return (buf);
 727 }
 728
 729 void
 730 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 731 {
 732         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 733
 734         i2c_write(i2c_addr, reg, 1, &val, 1);
 735 }
 736
 737 #endif  /* CONFIG_HARD_I2C */