cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  54
  55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  56         do {                                                            \
  57                 u32 data;                                               \
  58                 mfsdram(SDRAM_##mnemonic, data);                        \
  59                 printf("%20s[%02x] = 0x%08X\n",                         \
  60                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  61         } while (0)
  62
  63 #if defined(CONFIG_440)
  64 /*
  65  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  66  * memory region. Right now the cache should still be disabled in U-Boot
  67  * because of the EMAC driver, that need its buffer descriptor to be located
  68  * in non cached memory.
  69  *
  70  * If at some time this restriction doesn't apply anymore, just define
  71  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  72  * everything correctly.
  73  */
  74 #ifdef CONFIG_4xx_DCACHE
  75 /* enable caching on SDRAM */
  76 #define MY_TLB_WORD2_I_ENABLE           0
  77 #else
  78 /* disable caching on SDRAM */
  79 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
  80 #endif /* CONFIG_4xx_DCACHE */
  81 #endif /* CONFIG_440 */
  82
  83 #if defined(CONFIG_SPD_EEPROM)
  84
  85 /*-----------------------------------------------------------------------------+
  86  * Defines
  87  *-----------------------------------------------------------------------------*/
  88 #ifndef TRUE
  89 #define TRUE            1
  90 #endif
  91 #ifndef FALSE
  92 #define FALSE           0
  93 #endif
  94
  95 #define SDRAM_DDR1      1
  96 #define SDRAM_DDR2      2
  97 #define SDRAM_NONE      0
  98
  99 #define MAXDIMMS        2
 100 #define MAXRANKS        4
 101 #define MAXBXCF         4
 102 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 103
 104 #define ONE_BILLION     1000000000
 105
 106 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 107
 108 #define CMD_NOP         (7 << 19)
 109 #define CMD_PRECHARGE   (2 << 19)
 110 #define CMD_REFRESH     (1 << 19)
 111 #define CMD_EMR         (0 << 19)
 112 #define CMD_READ        (5 << 19)
 113 #define CMD_WRITE       (4 << 19)
 114
 115 #define SELECT_MR       (0 << 16)
 116 #define SELECT_EMR      (1 << 16)
 117 #define SELECT_EMR2     (2 << 16)
 118 #define SELECT_EMR3     (3 << 16)
 119
 120 /* MR */
 121 #define DLL_RESET       0x00000100
 122
 123 #define WRITE_RECOV_2   (1 << 9)
 124 #define WRITE_RECOV_3   (2 << 9)
 125 #define WRITE_RECOV_4   (3 << 9)
 126 #define WRITE_RECOV_5   (4 << 9)
 127 #define WRITE_RECOV_6   (5 << 9)
 128
 129 #define BURST_LEN_4     0x00000002
 130
 131 /* EMR */
 132 #define ODT_0_OHM       0x00000000
 133 #define ODT_50_OHM      0x00000044
 134 #define ODT_75_OHM      0x00000004
 135 #define ODT_150_OHM     0x00000040
 136
 137 #define ODS_FULL        0x00000000
 138 #define ODS_REDUCED     0x00000002
 139 #define OCD_CALIB_DEF   0x00000380
 140
 141 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 142 #define ODT_EB0R        (0x80000000 >> 8)
 143 #define ODT_EB0W        (0x80000000 >> 7)
 144 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 145 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 146 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 147
 148 /* Defines for the Read Cycle Delay test */
 149 #define NUMMEMTESTS     8
 150 #define NUMMEMWORDS     8
 151 #define NUMLOOPS        64              /* memory test loops */
 152
 153 /*
 154  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 155  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 156  * need some free virtual address space for the remaining peripherals like, SoC
 157  * devices, FLASH etc.
 158  *
 159  * Note that ECC is currently not supported on configurations with more than 2GB
 160  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 161  * the ECC parity byte of the remaining area can't be written.
 162  */
 163
 164 /*
 165  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 166  */
 167 void __spd_ddr_init_hang (void)
 168 {
 169         hang ();
 170 }
 171 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 172
 173 /*
 174  * To provide an interface for board specific config values in this common
 175  * DDR setup code, we implement he "weak" default functions here. They return
 176  * the default value back to the caller.
 177  *
 178  * Please see include/configs/yucca.h for an example fora board specific
 179  * implementation.
 180  */
 181 u32 __ddr_wrdtr(u32 default_val)
 182 {
 183         return default_val;
 184 }
 185 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 186
 187 u32 __ddr_clktr(u32 default_val)
 188 {
 189         return default_val;
 190 }
 191 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 192
 193
 194 /* Private Structure Definitions */
 195
 196 /* enum only to ease code for cas latency setting */
 197 typedef enum ddr_cas_id {
 198         DDR_CAS_2      = 20,
 199         DDR_CAS_2_5    = 25,
 200         DDR_CAS_3      = 30,
 201         DDR_CAS_4      = 40,
 202         DDR_CAS_5      = 50
 203 } ddr_cas_id_t;
 204
 205 /*-----------------------------------------------------------------------------+
 206  * Prototypes
 207  *-----------------------------------------------------------------------------*/
 208 static phys_size_t sdram_memsize(void);
 209 static void get_spd_info(unsigned long *dimm_populated,
 210                          unsigned char *iic0_dimm_addr,
 211                          unsigned long num_dimm_banks);
 212 static void check_mem_type(unsigned long *dimm_populated,
 213                            unsigned char *iic0_dimm_addr,
 214                            unsigned long num_dimm_banks);
 215 static void check_frequency(unsigned long *dimm_populated,
 216                             unsigned char *iic0_dimm_addr,
 217                             unsigned long num_dimm_banks);
 218 static void check_rank_number(unsigned long *dimm_populated,
 219                               unsigned char *iic0_dimm_addr,
 220                               unsigned long num_dimm_banks);
 221 static void check_voltage_type(unsigned long *dimm_populated,
 222                                unsigned char *iic0_dimm_addr,
 223                                unsigned long num_dimm_banks);
 224 static void program_memory_queue(unsigned long *dimm_populated,
 225                                  unsigned char *iic0_dimm_addr,
 226                                  unsigned long num_dimm_banks);
 227 static void program_codt(unsigned long *dimm_populated,
 228                          unsigned char *iic0_dimm_addr,
 229                          unsigned long num_dimm_banks);
 230 static void program_mode(unsigned long *dimm_populated,
 231                          unsigned char *iic0_dimm_addr,
 232                          unsigned long num_dimm_banks,
 233                          ddr_cas_id_t *selected_cas,
 234                          int *write_recovery);
 235 static void program_tr(unsigned long *dimm_populated,
 236                        unsigned char *iic0_dimm_addr,
 237                        unsigned long num_dimm_banks);
 238 static void program_rtr(unsigned long *dimm_populated,
 239                         unsigned char *iic0_dimm_addr,
 240                         unsigned long num_dimm_banks);
 241 static void program_bxcf(unsigned long *dimm_populated,
 242                          unsigned char *iic0_dimm_addr,
 243                          unsigned long num_dimm_banks);
 244 static void program_copt1(unsigned long *dimm_populated,
 245                           unsigned char *iic0_dimm_addr,
 246                           unsigned long num_dimm_banks);
 247 static void program_initplr(unsigned long *dimm_populated,
 248                             unsigned char *iic0_dimm_addr,
 249                             unsigned long num_dimm_banks,
 250                             ddr_cas_id_t selected_cas,
 251                             int write_recovery);
 252 static unsigned long is_ecc_enabled(void);
 253 #ifdef CONFIG_DDR_ECC
 254 static void program_ecc(unsigned long *dimm_populated,
 255                         unsigned char *iic0_dimm_addr,
 256                         unsigned long num_dimm_banks,
 257                         unsigned long tlb_word2_i_value);
 258 static void program_ecc_addr(unsigned long start_address,
 259                              unsigned long num_bytes,
 260                              unsigned long tlb_word2_i_value);
 261 #endif
 262 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 263 static void program_DQS_calibration(unsigned long *dimm_populated,
 264                                 unsigned char *iic0_dimm_addr,
 265                                 unsigned long num_dimm_banks);
 266 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 267 static void     test(void);
 268 #else
 269 static void     DQS_calibration_process(void);
 270 #endif
 271 #endif
 272 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 273 void dcbz_area(u32 start_address, u32 num_bytes);
 274
 275 static unsigned char spd_read(uchar chip, uint addr)
 276 {
 277         unsigned char data[2];
 278
 279         if (i2c_probe(chip) == 0)
 280                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 281                         return data[0];
 282
 283         return 0;
 284 }
 285
 286 /*-----------------------------------------------------------------------------+
 287  * sdram_memsize
 288  *-----------------------------------------------------------------------------*/
 289 static phys_size_t sdram_memsize(void)
 290 {
 291         phys_size_t mem_size;
 292         unsigned long mcopt2;
 293         unsigned long mcstat;
 294         unsigned long mb0cf;
 295         unsigned long sdsz;
 296         unsigned long i;
 297
 298         mem_size = 0;
 299
 300         mfsdram(SDRAM_MCOPT2, mcopt2);
 301         mfsdram(SDRAM_MCSTAT, mcstat);
 302
 303         /* DDR controller must be enabled and not in self-refresh. */
 304         /* Otherwise memsize is zero. */
 305         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 306             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 307             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 308                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 309                 for (i = 0; i < MAXBXCF; i++) {
 310                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 311                         /* Banks enabled */
 312                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 313                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 314
 315                                 switch(sdsz) {
 316                                 case SDRAM_RXBAS_SDSZ_8:
 317                                         mem_size+=8;
 318                                         break;
 319                                 case SDRAM_RXBAS_SDSZ_16:
 320                                         mem_size+=16;
 321                                         break;
 322                                 case SDRAM_RXBAS_SDSZ_32:
 323                                         mem_size+=32;
 324                                         break;
 325                                 case SDRAM_RXBAS_SDSZ_64:
 326                                         mem_size+=64;
 327                                         break;
 328                                 case SDRAM_RXBAS_SDSZ_128:
 329                                         mem_size+=128;
 330                                         break;
 331                                 case SDRAM_RXBAS_SDSZ_256:
 332                                         mem_size+=256;
 333                                         break;
 334                                 case SDRAM_RXBAS_SDSZ_512:
 335                                         mem_size+=512;
 336                                         break;
 337                                 case SDRAM_RXBAS_SDSZ_1024:
 338                                         mem_size+=1024;
 339                                         break;
 340                                 case SDRAM_RXBAS_SDSZ_2048:
 341                                         mem_size+=2048;
 342                                         break;
 343                                 case SDRAM_RXBAS_SDSZ_4096:
 344                                         mem_size+=4096;
 345                                         break;
 346                                 default:
 347                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 348                                                , sdsz);
 349                                         mem_size=0;
 350                                         break;
 351                                 }
 352                         }
 353                 }
 354         }
 355
 356         return mem_size << 20;
 357 }
 358
 359 /*-----------------------------------------------------------------------------+
 360  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 361  * Note: This routine runs from flash with a stack set up in the chip's
 362  * sram space.  It is important that the routine does not require .sbss, .bss or
 363  * .data sections.  It also cannot call routines that require these sections.
 364  *-----------------------------------------------------------------------------*/
 365 /*-----------------------------------------------------------------------------
 366  * Function:     initdram
 367  * Description:  Configures SDRAM memory banks for DDR operation.
 368  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 369  *               via the IIC bus and then configures the DDR SDRAM memory
 370  *               banks appropriately. If Auto Memory Configuration is
 371  *               not used, it is assumed that no DIMM is plugged
 372  *-----------------------------------------------------------------------------*/
 373 phys_size_t initdram(int board_type)
 374 {
 375         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 376         unsigned char spd0[MAX_SPD_BYTES];
 377         unsigned char spd1[MAX_SPD_BYTES];
 378         unsigned char *dimm_spd[MAXDIMMS];
 379         unsigned long dimm_populated[MAXDIMMS];
 380         unsigned long num_dimm_banks;           /* on board dimm banks */
 381         unsigned long val;
 382         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 383         int write_recovery;
 384         phys_size_t dram_size = 0;
 385
 386         num_dimm_banks = sizeof(iic0_dimm_addr);
 387
 388         /*------------------------------------------------------------------
 389          * Set up an array of SPD matrixes.
 390          *-----------------------------------------------------------------*/
 391         dimm_spd[0] = spd0;
 392         dimm_spd[1] = spd1;
 393
 394         /*------------------------------------------------------------------
 395          * Reset the DDR-SDRAM controller.
 396          *-----------------------------------------------------------------*/
 397         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 398         mtsdr(SDR0_SRST, 0x00000000);
 399
 400         /*
 401          * Make sure I2C controller is initialized
 402          * before continuing.
 403          */
 404
 405         /* switch to correct I2C bus */
 406         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 407         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 408
 409         /*------------------------------------------------------------------
 410          * Clear out the serial presence detect buffers.
 411          * Perform IIC reads from the dimm.  Fill in the spds.
 412          * Check to see if the dimm slots are populated
 413          *-----------------------------------------------------------------*/
 414         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 415
 416         /*------------------------------------------------------------------
 417          * Check the memory type for the dimms plugged.
 418          *-----------------------------------------------------------------*/
 419         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 420
 421         /*------------------------------------------------------------------
 422          * Check the frequency supported for the dimms plugged.
 423          *-----------------------------------------------------------------*/
 424         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 425
 426         /*------------------------------------------------------------------
 427          * Check the total rank number.
 428          *-----------------------------------------------------------------*/
 429         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 430
 431         /*------------------------------------------------------------------
 432          * Check the voltage type for the dimms plugged.
 433          *-----------------------------------------------------------------*/
 434         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 435
 436         /*------------------------------------------------------------------
 437          * Program SDRAM controller options 2 register
 438          * Except Enabling of the memory controller.
 439          *-----------------------------------------------------------------*/
 440         mfsdram(SDRAM_MCOPT2, val);
 441         mtsdram(SDRAM_MCOPT2,
 442                 (val &
 443                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 444                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 445                    SDRAM_MCOPT2_ISIE_MASK))
 446                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 447                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 448                    SDRAM_MCOPT2_ISIE_ENABLE));
 449
 450         /*------------------------------------------------------------------
 451          * Program SDRAM controller options 1 register
 452          * Note: Does not enable the memory controller.
 453          *-----------------------------------------------------------------*/
 454         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 455
 456         /*------------------------------------------------------------------
 457          * Set the SDRAM Controller On Die Termination Register
 458          *-----------------------------------------------------------------*/
 459         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 460
 461         /*------------------------------------------------------------------
 462          * Program SDRAM refresh register.
 463          *-----------------------------------------------------------------*/
 464         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 465
 466         /*------------------------------------------------------------------
 467          * Program SDRAM mode register.
 468          *-----------------------------------------------------------------*/
 469         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 470                      &selected_cas, &write_recovery);
 471
 472         /*------------------------------------------------------------------
 473          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 474          *-----------------------------------------------------------------*/
 475         mfsdram(SDRAM_WRDTR, val);
 476         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 477                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 478
 479         /*------------------------------------------------------------------
 480          * Set the SDRAM Clock Timing Register
 481          *-----------------------------------------------------------------*/
 482         mfsdram(SDRAM_CLKTR, val);
 483         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 484                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 485
 486         /*------------------------------------------------------------------
 487          * Program the BxCF registers.
 488          *-----------------------------------------------------------------*/
 489         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 490
 491         /*------------------------------------------------------------------
 492          * Program SDRAM timing registers.
 493          *-----------------------------------------------------------------*/
 494         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 495
 496         /*------------------------------------------------------------------
 497          * Set the Extended Mode register
 498          *-----------------------------------------------------------------*/
 499         mfsdram(SDRAM_MEMODE, val);
 500         mtsdram(SDRAM_MEMODE,
 501                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 502                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 503                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 504                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 505
 506         /*------------------------------------------------------------------
 507          * Program Initialization preload registers.
 508          *-----------------------------------------------------------------*/
 509         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 510                         selected_cas, write_recovery);
 511
 512         /*------------------------------------------------------------------
 513          * Delay to ensure 200usec have elapsed since reset.
 514          *-----------------------------------------------------------------*/
 515         udelay(400);
 516
 517         /*------------------------------------------------------------------
 518          * Set the memory queue core base addr.
 519          *-----------------------------------------------------------------*/
 520         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 521
 522         /*------------------------------------------------------------------
 523          * Program SDRAM controller options 2 register
 524          * Enable the memory controller.
 525          *-----------------------------------------------------------------*/
 526         mfsdram(SDRAM_MCOPT2, val);
 527         mtsdram(SDRAM_MCOPT2,
 528                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 529                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 530                          SDRAM_MCOPT2_IPTR_EXECUTE);
 531
 532         /*------------------------------------------------------------------
 533          * Wait for IPTR_EXECUTE init sequence to complete.
 534          *-----------------------------------------------------------------*/
 535         do {
 536                 mfsdram(SDRAM_MCSTAT, val);
 537         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 538
 539         /* enable the controller only after init sequence completes */
 540         mfsdram(SDRAM_MCOPT2, val);
 541         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 542
 543         /* Make sure delay-line calibration is done before proceeding */
 544         do {
 545                 mfsdram(SDRAM_DLCR, val);
 546         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 547
 548         /* get installed memory size */
 549         dram_size = sdram_memsize();
 550
 551         /*
 552          * Limit size to 2GB
 553          */
 554         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 555                 dram_size = CONFIG_MAX_MEM_MAPPED;
 556
 557         /* and program tlb entries for this size (dynamic) */
 558
 559         /*
 560          * Program TLB entries with caches enabled, for best performace
 561          * while auto-calibrating and ECC generation
 562          */
 563         program_tlb(0, 0, dram_size, 0);
 564
 565         /*------------------------------------------------------------------
 566          * DQS calibration.
 567          *-----------------------------------------------------------------*/
 568 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 569         DQS_autocalibration();
 570 #else
 571         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 572 #endif
 573
 574 #ifdef CONFIG_DDR_ECC
 575         /*------------------------------------------------------------------
 576          * If ecc is enabled, initialize the parity bits.
 577          *-----------------------------------------------------------------*/
 578         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 579 #endif
 580
 581         /*
 582          * Now after initialization (auto-calibration and ECC generation)
 583          * remove the TLB entries with caches enabled and program again with
 584          * desired cache functionality
 585          */
 586         remove_tlb(0, dram_size);
 587         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 588
 589         ppc4xx_ibm_ddr2_register_dump();
 590
 591         /*
 592          * Clear potential errors resulting from auto-calibration.
 593          * If not done, then we could get an interrupt later on when
 594          * exceptions are enabled.
 595          */
 596         set_mcsr(get_mcsr());
 597
 598         return sdram_memsize();
 599 }
 600
 601 static void get_spd_info(unsigned long *dimm_populated,
 602                          unsigned char *iic0_dimm_addr,
 603                          unsigned long num_dimm_banks)
 604 {
 605         unsigned long dimm_num;
 606         unsigned long dimm_found;
 607         unsigned char num_of_bytes;
 608         unsigned char total_size;
 609
 610         dimm_found = FALSE;
 611         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 612                 num_of_bytes = 0;
 613                 total_size = 0;
 614
 615                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 616                 debug("\nspd_read(0x%x) returned %d\n",
 617                       iic0_dimm_addr[dimm_num], num_of_bytes);
 618                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 619                 debug("spd_read(0x%x) returned %d\n",
 620                       iic0_dimm_addr[dimm_num], total_size);
 621
 622                 if ((num_of_bytes != 0) && (total_size != 0)) {
 623                         dimm_populated[dimm_num] = TRUE;
 624                         dimm_found = TRUE;
 625                         debug("DIMM slot %lu: populated\n", dimm_num);
 626                 } else {
 627                         dimm_populated[dimm_num] = FALSE;
 628                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 629                 }
 630         }
 631
 632         if (dimm_found == FALSE) {
 633                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 634                 spd_ddr_init_hang ();
 635         }
 636 }
 637
 638 void board_add_ram_info(int use_default)
 639 {
 640         PPC4xx_SYS_INFO board_cfg;
 641         u32 val;
 642
 643         if (is_ecc_enabled())
 644                 puts(" (ECC");
 645         else
 646                 puts(" (ECC not");
 647
 648         get_sys_info(&board_cfg);
 649
 650         mfsdr(SDR0_DDR0, val);
 651         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 652         printf(" enabled, %d MHz", (val * 2) / 1000000);
 653
 654         mfsdram(SDRAM_MMODE, val);
 655         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 656         printf(", CL%d)", val);
 657 }
 658
 659 /*------------------------------------------------------------------
 660  * For the memory DIMMs installed, this routine verifies that they
 661  * really are DDR specific DIMMs.
 662  *-----------------------------------------------------------------*/
 663 static void check_mem_type(unsigned long *dimm_populated,
 664                            unsigned char *iic0_dimm_addr,
 665                            unsigned long num_dimm_banks)
 666 {
 667         unsigned long dimm_num;
 668         unsigned long dimm_type;
 669
 670         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 671                 if (dimm_populated[dimm_num] == TRUE) {
 672                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 673                         switch (dimm_type) {
 674                         case 1:
 675                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 676                                        "slot %d.\n", (unsigned int)dimm_num);
 677                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 678                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 679                                 spd_ddr_init_hang ();
 680                                 break;
 681                         case 2:
 682                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 683                                        (unsigned int)dimm_num);
 684                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 685                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 686                                 spd_ddr_init_hang ();
 687                                 break;
 688                         case 3:
 689                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 690                                        (unsigned int)dimm_num);
 691                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 692                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 693                                 spd_ddr_init_hang ();
 694                                 break;
 695                         case 4:
 696                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 697                                        (unsigned int)dimm_num);
 698                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 699                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 700                                 spd_ddr_init_hang ();
 701                                 break;
 702                         case 5:
 703                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 704                                        (unsigned int)dimm_num);
 705                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 706                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 707                                 spd_ddr_init_hang ();
 708                                 break;
 709                         case 6:
 710                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 711                                        (unsigned int)dimm_num);
 712                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 713                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 714                                 spd_ddr_init_hang ();
 715                                 break;
 716                         case 7:
 717                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 718                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 719                                 break;
 720                         case 8:
 721                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 722                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 723                                 break;
 724                         default:
 725                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 726                                        (unsigned int)dimm_num);
 727                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 728                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 729                                 spd_ddr_init_hang ();
 730                                 break;
 731                         }
 732                 }
 733         }
 734         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 735                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 736                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 737                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 738                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 739                         spd_ddr_init_hang ();
 740                 }
 741         }
 742 }
 743
 744 /*------------------------------------------------------------------
 745  * For the memory DIMMs installed, this routine verifies that
 746  * frequency previously calculated is supported.
 747  *-----------------------------------------------------------------*/
 748 static void check_frequency(unsigned long *dimm_populated,
 749                             unsigned char *iic0_dimm_addr,
 750                             unsigned long num_dimm_banks)
 751 {
 752         unsigned long dimm_num;
 753         unsigned long tcyc_reg;
 754         unsigned long cycle_time;
 755         unsigned long calc_cycle_time;
 756         unsigned long sdram_freq;
 757         unsigned long sdr_ddrpll;
 758         PPC4xx_SYS_INFO board_cfg;
 759
 760         /*------------------------------------------------------------------
 761          * Get the board configuration info.
 762          *-----------------------------------------------------------------*/
 763         get_sys_info(&board_cfg);
 764
 765         mfsdr(SDR0_DDR0, sdr_ddrpll);
 766         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 767
 768         /*
 769          * calc_cycle_time is calculated from DDR frequency set by board/chip
 770          * and is expressed in multiple of 10 picoseconds
 771          * to match the way DIMM cycle time is calculated below.
 772          */
 773         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 774
 775         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 776                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 777                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 778                         /*
 779                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 780                          * the higher order nibble (bits 4-7) designates the cycle time
 781                          * to a granularity of 1ns;
 782                          * the value presented by the lower order nibble (bits 0-3)
 783                          * has a granularity of .1ns and is added to the value designated
 784                          * by the higher nibble. In addition, four lines of the lower order
 785                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 786                          */
 787                          /* Convert from hex to decimal */
 788                         if ((tcyc_reg & 0x0F) == 0x0D)
 789                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 790                         else if ((tcyc_reg & 0x0F) == 0x0C)
 791                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 792                         else if ((tcyc_reg & 0x0F) == 0x0B)
 793                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 794                         else if ((tcyc_reg & 0x0F) == 0x0A)
 795                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 796                         else
 797                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 798                                         ((tcyc_reg & 0x0F)*10);
 799                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 800
 801                         if  (cycle_time > (calc_cycle_time + 10)) {
 802                                 /*
 803                                  * the provided sdram cycle_time is too small
 804                                  * for the available DIMM cycle_time.
 805                                  * The additionnal 100ps is here to accept a small incertainty.
 806                                  */
 807                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 808                                        "slot %d \n while calculated cycle time is %d ps.\n",
 809                                        (unsigned int)(cycle_time*10),
 810                                        (unsigned int)dimm_num,
 811                                        (unsigned int)(calc_cycle_time*10));
 812                                 printf("Replace the DIMM, or change DDR frequency via "
 813                                        "strapping bits.\n\n");
 814                                 spd_ddr_init_hang ();
 815                         }
 816                 }
 817         }
 818 }
 819
 820 /*------------------------------------------------------------------
 821  * For the memory DIMMs installed, this routine verifies two
 822  * ranks/banks maximum are availables.
 823  *-----------------------------------------------------------------*/
 824 static void check_rank_number(unsigned long *dimm_populated,
 825                               unsigned char *iic0_dimm_addr,
 826                               unsigned long num_dimm_banks)
 827 {
 828         unsigned long dimm_num;
 829         unsigned long dimm_rank;
 830         unsigned long total_rank = 0;
 831
 832         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 833                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 834                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 835                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 836                                 dimm_rank = (dimm_rank & 0x0F) +1;
 837                         else
 838                                 dimm_rank = dimm_rank & 0x0F;
 839
 840
 841                         if (dimm_rank > MAXRANKS) {
 842                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 843                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 844                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 845                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 846                                 spd_ddr_init_hang ();
 847                         } else
 848                                 total_rank += dimm_rank;
 849                 }
 850                 if (total_rank > MAXRANKS) {
 851                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 852                                "for all slots.\n", (unsigned int)total_rank);
 853                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 854                         printf("Remove one of the DIMM modules.\n\n");
 855                         spd_ddr_init_hang ();
 856                 }
 857         }
 858 }
 859
 860 /*------------------------------------------------------------------
 861  * only support 2.5V modules.
 862  * This routine verifies this.
 863  *-----------------------------------------------------------------*/
 864 static void check_voltage_type(unsigned long *dimm_populated,
 865                                unsigned char *iic0_dimm_addr,
 866                                unsigned long num_dimm_banks)
 867 {
 868         unsigned long dimm_num;
 869         unsigned long voltage_type;
 870
 871         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 872                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 873                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 874                         switch (voltage_type) {
 875                         case 0x00:
 876                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 877                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 878                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 879                                        (unsigned int)dimm_num);
 880                                 spd_ddr_init_hang ();
 881                                 break;
 882                         case 0x01:
 883                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 884                                 printf("This DIMM is LVTTL.\n");
 885                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 886                                        (unsigned int)dimm_num);
 887                                 spd_ddr_init_hang ();
 888                                 break;
 889                         case 0x02:
 890                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 891                                 printf("This DIMM is 1.5 Volt.\n");
 892                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 893                                        (unsigned int)dimm_num);
 894                                 spd_ddr_init_hang ();
 895                                 break;
 896                         case 0x03:
 897                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 898                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 899                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 900                                        (unsigned int)dimm_num);
 901                                 spd_ddr_init_hang ();
 902                                 break;
 903                         case 0x04:
 904                                 /* 2.5 Voltage only for DDR1 */
 905                                 break;
 906                         case 0x05:
 907                                 /* 1.8 Voltage only for DDR2 */
 908                                 break;
 909                         default:
 910                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 911                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 912                                        (unsigned int)dimm_num);
 913                                 spd_ddr_init_hang ();
 914                                 break;
 915                         }
 916                 }
 917         }
 918 }
 919
 920 /*-----------------------------------------------------------------------------+
 921  * program_copt1.
 922  *-----------------------------------------------------------------------------*/
 923 static void program_copt1(unsigned long *dimm_populated,
 924                           unsigned char *iic0_dimm_addr,
 925                           unsigned long num_dimm_banks)
 926 {
 927         unsigned long dimm_num;
 928         unsigned long mcopt1;
 929         unsigned long ecc_enabled;
 930         unsigned long ecc = 0;
 931         unsigned long data_width = 0;
 932         unsigned long dimm_32bit;
 933         unsigned long dimm_64bit;
 934         unsigned long registered = 0;
 935         unsigned long attribute = 0;
 936         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 937         unsigned long bankcount;
 938         unsigned long ddrtype;
 939         unsigned long val;
 940
 941 #ifdef CONFIG_DDR_ECC
 942         ecc_enabled = TRUE;
 943 #else
 944         ecc_enabled = FALSE;
 945 #endif
 946         dimm_32bit = FALSE;
 947         dimm_64bit = FALSE;
 948         buf0 = FALSE;
 949         buf1 = FALSE;
 950
 951         /*------------------------------------------------------------------
 952          * Set memory controller options reg 1, SDRAM_MCOPT1.
 953          *-----------------------------------------------------------------*/
 954         mfsdram(SDRAM_MCOPT1, val);
 955         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 956                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 957                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 958                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 959                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 960                          SDRAM_MCOPT1_DREF_MASK);
 961
 962         mcopt1 |= SDRAM_MCOPT1_QDEP;
 963         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 964         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 965         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 966         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 967         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 968
 969         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 970                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 971                         /* test ecc support */
 972                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 973                         if (ecc != 0x02) /* ecc not supported */
 974                                 ecc_enabled = FALSE;
 975
 976                         /* test bank count */
 977                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 978                         if (bankcount == 0x04) /* bank count = 4 */
 979                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 980                         else /* bank count = 8 */
 981                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 982
 983                         /* test DDR type */
 984                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 985                         /* test for buffered/unbuffered, registered, differential clocks */
 986                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 987                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 988
 989                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 990                         if (dimm_num == 0) {
 991                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 992                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 993                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 994                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 995                                 if (registered == 1) { /* DDR2 always buffered */
 996                                         /* TODO: what about above  comments ? */
 997                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 998                                         buf0 = TRUE;
 999                                 } else {
1000                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1001                                         if ((attribute & 0x02) == 0x00) {
1002                                                 /* buffered not supported */
1003                                                 buf0 = FALSE;
1004                                         } else {
1005                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1006                                                 buf0 = TRUE;
1007                                         }
1008                                 }
1009                         }
1010                         else if (dimm_num == 1) {
1011                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1012                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1013                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1014                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1015                                 if (registered == 1) {
1016                                         /* DDR2 always buffered */
1017                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1018                                         buf1 = TRUE;
1019                                 } else {
1020                                         if ((attribute & 0x02) == 0x00) {
1021                                                 /* buffered not supported */
1022                                                 buf1 = FALSE;
1023                                         } else {
1024                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1025                                                 buf1 = TRUE;
1026                                         }
1027                                 }
1028                         }
1029
1030                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1031                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1032                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1033
1034                         switch (data_width) {
1035                         case 72:
1036                         case 64:
1037                                 dimm_64bit = TRUE;
1038                                 break;
1039                         case 40:
1040                         case 32:
1041                                 dimm_32bit = TRUE;
1042                                 break;
1043                         default:
1044                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1045                                        data_width);
1046                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1047                                 break;
1048                         }
1049                 }
1050         }
1051
1052         /* verify matching properties */
1053         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1054                 if (buf0 != buf1) {
1055                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1056                         spd_ddr_init_hang ();
1057                 }
1058         }
1059
1060         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1061                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1062                 spd_ddr_init_hang ();
1063         }
1064         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1065                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1066         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1067                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1068         } else {
1069                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1070                 spd_ddr_init_hang ();
1071         }
1072
1073         if (ecc_enabled == TRUE)
1074                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1075         else
1076                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1077
1078         mtsdram(SDRAM_MCOPT1, mcopt1);
1079 }
1080
1081 /*-----------------------------------------------------------------------------+
1082  * program_codt.
1083  *-----------------------------------------------------------------------------*/
1084 static void program_codt(unsigned long *dimm_populated,
1085                          unsigned char *iic0_dimm_addr,
1086                          unsigned long num_dimm_banks)
1087 {
1088         unsigned long codt;
1089         unsigned long modt0 = 0;
1090         unsigned long modt1 = 0;
1091         unsigned long modt2 = 0;
1092         unsigned long modt3 = 0;
1093         unsigned char dimm_num;
1094         unsigned char dimm_rank;
1095         unsigned char total_rank = 0;
1096         unsigned char total_dimm = 0;
1097         unsigned char dimm_type = 0;
1098         unsigned char firstSlot = 0;
1099
1100         /*------------------------------------------------------------------
1101          * Set the SDRAM Controller On Die Termination Register
1102          *-----------------------------------------------------------------*/
1103         mfsdram(SDRAM_CODT, codt);
1104         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1105         codt |= SDRAM_CODT_IO_NMODE;
1106
1107         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1108                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1109                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1110                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1111                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1112                                 dimm_type = SDRAM_DDR2;
1113                         } else {
1114                                 dimm_rank = dimm_rank & 0x0F;
1115                                 dimm_type = SDRAM_DDR1;
1116                         }
1117
1118                         total_rank += dimm_rank;
1119                         total_dimm++;
1120                         if ((dimm_num == 0) && (total_dimm == 1))
1121                                 firstSlot = TRUE;
1122                         else
1123                                 firstSlot = FALSE;
1124                 }
1125         }
1126         if (dimm_type == SDRAM_DDR2) {
1127                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1128                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1129                         if (total_rank == 1) {  /* PUUU */
1130                                 codt |= CALC_ODT_R(0);
1131                                 modt0 = CALC_ODT_W(0);
1132                                 modt1 = 0x00000000;
1133                                 modt2 = 0x00000000;
1134                                 modt3 = 0x00000000;
1135                         }
1136                         if (total_rank == 2) {  /* PPUU */
1137                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1138                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1139                                 modt1 = 0x00000000;
1140                                 modt2 = 0x00000000;
1141                                 modt3 = 0x00000000;
1142                         }
1143                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1144                         if (total_rank == 1) {  /* UUPU */
1145                                 codt |= CALC_ODT_R(2);
1146                                 modt0 = 0x00000000;
1147                                 modt1 = 0x00000000;
1148                                 modt2 = CALC_ODT_W(2);
1149                                 modt3 = 0x00000000;
1150                         }
1151                         if (total_rank == 2) {  /* UUPP */
1152                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1153                                 modt0 = 0x00000000;
1154                                 modt1 = 0x00000000;
1155                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1156                                 modt3 = 0x00000000;
1157                         }
1158                 }
1159                 if (total_dimm == 2) {
1160                         if (total_rank == 2) {  /* PUPU */
1161                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1162                                 modt0 = CALC_ODT_RW(2);
1163                                 modt1 = 0x00000000;
1164                                 modt2 = CALC_ODT_RW(0);
1165                                 modt3 = 0x00000000;
1166                         }
1167                         if (total_rank == 4) {  /* PPPP */
1168                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1169                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1170                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1171                                 modt1 = 0x00000000;
1172                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1173                                 modt3 = 0x00000000;
1174                         }
1175                 }
1176         } else {
1177                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1178                 modt0 = 0x00000000;
1179                 modt1 = 0x00000000;
1180                 modt2 = 0x00000000;
1181                 modt3 = 0x00000000;
1182
1183                 if (total_dimm == 1) {
1184                         if (total_rank == 1)
1185                                 codt |= 0x00800000;
1186                         if (total_rank == 2)
1187                                 codt |= 0x02800000;
1188                 }
1189                 if (total_dimm == 2) {
1190                         if (total_rank == 2)
1191                                 codt |= 0x08800000;
1192                         if (total_rank == 4)
1193                                 codt |= 0x2a800000;
1194                 }
1195         }
1196
1197         debug("nb of dimm %d\n", total_dimm);
1198         debug("nb of rank %d\n", total_rank);
1199         if (total_dimm == 1)
1200                 debug("dimm in slot %d\n", firstSlot);
1201
1202         mtsdram(SDRAM_CODT, codt);
1203         mtsdram(SDRAM_MODT0, modt0);
1204         mtsdram(SDRAM_MODT1, modt1);
1205         mtsdram(SDRAM_MODT2, modt2);
1206         mtsdram(SDRAM_MODT3, modt3);
1207 }
1208
1209 /*-----------------------------------------------------------------------------+
1210  * program_initplr.
1211  *-----------------------------------------------------------------------------*/
1212 static void program_initplr(unsigned long *dimm_populated,
1213                             unsigned char *iic0_dimm_addr,
1214                             unsigned long num_dimm_banks,
1215                             ddr_cas_id_t selected_cas,
1216                             int write_recovery)
1217 {
1218         u32 cas = 0;
1219         u32 odt = 0;
1220         u32 ods = 0;
1221         u32 mr;
1222         u32 wr;
1223         u32 emr;
1224         u32 emr2;
1225         u32 emr3;
1226         int dimm_num;
1227         int total_dimm = 0;
1228
1229         /******************************************************
1230          ** Assumption: if more than one DIMM, all DIMMs are the same
1231          **             as already checked in check_memory_type
1232          ******************************************************/
1233
1234         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1235                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1236                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1237                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1238                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1239                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1240                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1241                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1242                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1243         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1244                 switch (selected_cas) {
1245                 case DDR_CAS_3:
1246                         cas = 3 << 4;
1247                         break;
1248                 case DDR_CAS_4:
1249                         cas = 4 << 4;
1250                         break;
1251                 case DDR_CAS_5:
1252                         cas = 5 << 4;
1253                         break;
1254                 default:
1255                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1256                         spd_ddr_init_hang ();
1257                         break;
1258                 }
1259
1260 #if 0
1261                 /*
1262                  * ToDo - Still a problem with the write recovery:
1263                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1264                  * in the INITPLR reg to the value calculated in program_mode()
1265                  * results in not correctly working DDR2 memory (crash after
1266                  * relocation).
1267                  *
1268                  * So for now, set the write recovery to 3. This seems to work
1269                  * on the Corair module too.
1270                  *
1271                  * 2007-03-01, sr
1272                  */
1273                 switch (write_recovery) {
1274                 case 3:
1275                         wr = WRITE_RECOV_3;
1276                         break;
1277                 case 4:
1278                         wr = WRITE_RECOV_4;
1279                         break;
1280                 case 5:
1281                         wr = WRITE_RECOV_5;
1282                         break;
1283                 case 6:
1284                         wr = WRITE_RECOV_6;
1285                         break;
1286                 default:
1287                         printf("ERROR: write recovery not support (%d)", write_recovery);
1288                         spd_ddr_init_hang ();
1289                         break;
1290                 }
1291 #else
1292                 wr = WRITE_RECOV_3; /* test-only, see description above */
1293 #endif
1294
1295                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1296                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1297                                 total_dimm++;
1298                 if (total_dimm == 1) {
1299                         odt = ODT_150_OHM;
1300                         ods = ODS_FULL;
1301                 } else if (total_dimm == 2) {
1302                         odt = ODT_75_OHM;
1303                         ods = ODS_REDUCED;
1304                 } else {
1305                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1306                         spd_ddr_init_hang ();
1307                 }
1308
1309                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1310                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1311                 emr2 = CMD_EMR | SELECT_EMR2;
1312                 emr3 = CMD_EMR | SELECT_EMR3;
1313                 /* NOP - Wait 106 MemClk cycles */
1314                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1315                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1316                 udelay(1000);
1317                 /* precharge 4 MemClk cycles */
1318                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1319                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1320                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1321                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1322                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1323                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1324                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1325                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1326                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1327                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1328                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1329                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1330                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1331                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1332                 udelay(1000);
1333                 /* precharge 4 MemClk cycles */
1334                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1335                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1336                 /* Refresh 25 MemClk cycles */
1337                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1338                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1339                 /* Refresh 25 MemClk cycles */
1340                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1341                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1342                 /* Refresh 25 MemClk cycles */
1343                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1344                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1345                 /* Refresh 25 MemClk cycles */
1346                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1347                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1348                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1349                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1350                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1351                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1352                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1353                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1354                 /* EMR OCD Exit */
1355                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1356                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1357         } else {
1358                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1359                 spd_ddr_init_hang ();
1360         }
1361 }
1362
1363 /*------------------------------------------------------------------
1364  * This routine programs the SDRAM_MMODE register.
1365  * the selected_cas is an output parameter, that will be passed
1366  * by caller to call the above program_initplr( )
1367  *-----------------------------------------------------------------*/
1368 static void program_mode(unsigned long *dimm_populated,
1369                          unsigned char *iic0_dimm_addr,
1370                          unsigned long num_dimm_banks,
1371                          ddr_cas_id_t *selected_cas,
1372                          int *write_recovery)
1373 {
1374         unsigned long dimm_num;
1375         unsigned long sdram_ddr1;
1376         unsigned long t_wr_ns;
1377         unsigned long t_wr_clk;
1378         unsigned long cas_bit;
1379         unsigned long cas_index;
1380         unsigned long sdram_freq;
1381         unsigned long ddr_check;
1382         unsigned long mmode;
1383         unsigned long tcyc_reg;
1384         unsigned long cycle_2_0_clk;
1385         unsigned long cycle_2_5_clk;
1386         unsigned long cycle_3_0_clk;
1387         unsigned long cycle_4_0_clk;
1388         unsigned long cycle_5_0_clk;
1389         unsigned long max_2_0_tcyc_ns_x_100;
1390         unsigned long max_2_5_tcyc_ns_x_100;
1391         unsigned long max_3_0_tcyc_ns_x_100;
1392         unsigned long max_4_0_tcyc_ns_x_100;
1393         unsigned long max_5_0_tcyc_ns_x_100;
1394         unsigned long cycle_time_ns_x_100[3];
1395         PPC4xx_SYS_INFO board_cfg;
1396         unsigned char cas_2_0_available;
1397         unsigned char cas_2_5_available;
1398         unsigned char cas_3_0_available;
1399         unsigned char cas_4_0_available;
1400         unsigned char cas_5_0_available;
1401         unsigned long sdr_ddrpll;
1402
1403         /*------------------------------------------------------------------
1404          * Get the board configuration info.
1405          *-----------------------------------------------------------------*/
1406         get_sys_info(&board_cfg);
1407
1408         mfsdr(SDR0_DDR0, sdr_ddrpll);
1409         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1410         debug("sdram_freq=%d\n", sdram_freq);
1411
1412         /*------------------------------------------------------------------
1413          * Handle the timing.  We need to find the worst case timing of all
1414          * the dimm modules installed.
1415          *-----------------------------------------------------------------*/
1416         t_wr_ns = 0;
1417         cas_2_0_available = TRUE;
1418         cas_2_5_available = TRUE;
1419         cas_3_0_available = TRUE;
1420         cas_4_0_available = TRUE;
1421         cas_5_0_available = TRUE;
1422         max_2_0_tcyc_ns_x_100 = 10;
1423         max_2_5_tcyc_ns_x_100 = 10;
1424         max_3_0_tcyc_ns_x_100 = 10;
1425         max_4_0_tcyc_ns_x_100 = 10;
1426         max_5_0_tcyc_ns_x_100 = 10;
1427         sdram_ddr1 = TRUE;
1428
1429         /* loop through all the DIMM slots on the board */
1430         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1431                 /* If a dimm is installed in a particular slot ... */
1432                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1433                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1434                                 sdram_ddr1 = TRUE;
1435                         else
1436                                 sdram_ddr1 = FALSE;
1437
1438                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1439                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1440                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1441
1442                         /* For a particular DIMM, grab the three CAS values it supports */
1443                         for (cas_index = 0; cas_index < 3; cas_index++) {
1444                                 switch (cas_index) {
1445                                 case 0:
1446                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1447                                         break;
1448                                 case 1:
1449                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1450                                         break;
1451                                 default:
1452                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1453                                         break;
1454                                 }
1455
1456                                 if ((tcyc_reg & 0x0F) >= 10) {
1457                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1458                                                 /* Convert from hex to decimal */
1459                                                 cycle_time_ns_x_100[cas_index] =
1460                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1461                                         } else {
1462                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1463                                                        "in slot %d\n", (unsigned int)dimm_num);
1464                                                 spd_ddr_init_hang ();
1465                                         }
1466                                 } else {
1467                                         /* Convert from hex to decimal */
1468                                         cycle_time_ns_x_100[cas_index] =
1469                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1470                                                 ((tcyc_reg & 0x0F)*10);
1471                                 }
1472                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1473                                       cycle_time_ns_x_100[cas_index]);
1474                         }
1475
1476                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1477                         /* supported for a particular DIMM. */
1478                         cas_index = 0;
1479
1480                         if (sdram_ddr1) {
1481                                 /*
1482                                  * DDR devices use the following bitmask for CAS latency:
1483                                  *  Bit   7    6    5    4    3    2    1    0
1484                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1485                                  */
1486                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1487                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1488                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1489                                                                     cycle_time_ns_x_100[cas_index]);
1490                                         cas_index++;
1491                                 } else {
1492                                         if (cas_index != 0)
1493                                                 cas_index++;
1494                                         cas_4_0_available = FALSE;
1495                                 }
1496
1497                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1498                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1499                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1500                                                                     cycle_time_ns_x_100[cas_index]);
1501                                         cas_index++;
1502                                 } else {
1503                                         if (cas_index != 0)
1504                                                 cas_index++;
1505                                         cas_3_0_available = FALSE;
1506                                 }
1507
1508                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1509                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1510                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1511                                                                     cycle_time_ns_x_100[cas_index]);
1512                                         cas_index++;
1513                                 } else {
1514                                         if (cas_index != 0)
1515                                                 cas_index++;
1516                                         cas_2_5_available = FALSE;
1517                                 }
1518
1519                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1520                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1521                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1522                                                                     cycle_time_ns_x_100[cas_index]);
1523                                         cas_index++;
1524                                 } else {
1525                                         if (cas_index != 0)
1526                                                 cas_index++;
1527                                         cas_2_0_available = FALSE;
1528                                 }
1529                         } else {
1530                                 /*
1531                                  * DDR2 devices use the following bitmask for CAS latency:
1532                                  *  Bit   7    6    5    4    3    2    1    0
1533                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1534                                  */
1535                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1536                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1537                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1538                                                                     cycle_time_ns_x_100[cas_index]);
1539                                         cas_index++;
1540                                 } else {
1541                                         if (cas_index != 0)
1542                                                 cas_index++;
1543                                         cas_5_0_available = FALSE;
1544                                 }
1545
1546                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1547                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1548                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1549                                                                     cycle_time_ns_x_100[cas_index]);
1550                                         cas_index++;
1551                                 } else {
1552                                         if (cas_index != 0)
1553                                                 cas_index++;
1554                                         cas_4_0_available = FALSE;
1555                                 }
1556
1557                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1558                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1559                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1560                                                                     cycle_time_ns_x_100[cas_index]);
1561                                         cas_index++;
1562                                 } else {
1563                                         if (cas_index != 0)
1564                                                 cas_index++;
1565                                         cas_3_0_available = FALSE;
1566                                 }
1567                         }
1568                 }
1569         }
1570
1571         /*------------------------------------------------------------------
1572          * Set the SDRAM mode, SDRAM_MMODE
1573          *-----------------------------------------------------------------*/
1574         mfsdram(SDRAM_MMODE, mmode);
1575         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1576
1577         /* add 10 here because of rounding problems */
1578         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1579         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1580         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1581         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1582         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1583         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1584         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1585         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1586
1587         if (sdram_ddr1 == TRUE) { /* DDR1 */
1588                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1589                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1590                         *selected_cas = DDR_CAS_2;
1591                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1592                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1593                         *selected_cas = DDR_CAS_2_5;
1594                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1595                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1596                         *selected_cas = DDR_CAS_3;
1597                 } else {
1598                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1599                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1600                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1601                         spd_ddr_init_hang ();
1602                 }
1603         } else { /* DDR2 */
1604                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1605                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1606                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1607                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1608                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1609                         *selected_cas = DDR_CAS_3;
1610                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1611                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1612                         *selected_cas = DDR_CAS_4;
1613                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1614                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1615                         *selected_cas = DDR_CAS_5;
1616                 } else {
1617                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1618                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1619                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1620                         printf("cas3=%d cas4=%d cas5=%d\n",
1621                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1622                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1623                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1624                         spd_ddr_init_hang ();
1625                 }
1626         }
1627
1628         if (sdram_ddr1 == TRUE)
1629                 mmode |= SDRAM_MMODE_WR_DDR1;
1630         else {
1631
1632                 /* loop through all the DIMM slots on the board */
1633                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1634                         /* If a dimm is installed in a particular slot ... */
1635                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1636                                 t_wr_ns = max(t_wr_ns,
1637                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1638                 }
1639
1640                 /*
1641                  * convert from nanoseconds to ddr clocks
1642                  * round up if necessary
1643                  */
1644                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1645                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1646                 if (sdram_freq != ddr_check)
1647                         t_wr_clk++;
1648
1649                 switch (t_wr_clk) {
1650                 case 0:
1651                 case 1:
1652                 case 2:
1653                 case 3:
1654                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1655                         break;
1656                 case 4:
1657                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1658                         break;
1659                 case 5:
1660                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1661                         break;
1662                 default:
1663                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1664                         break;
1665                 }
1666                 *write_recovery = t_wr_clk;
1667         }
1668
1669         debug("CAS latency = %d\n", *selected_cas);
1670         debug("Write recovery = %d\n", *write_recovery);
1671
1672         mtsdram(SDRAM_MMODE, mmode);
1673 }
1674
1675 /*-----------------------------------------------------------------------------+
1676  * program_rtr.
1677  *-----------------------------------------------------------------------------*/
1678 static void program_rtr(unsigned long *dimm_populated,
1679                         unsigned char *iic0_dimm_addr,
1680                         unsigned long num_dimm_banks)
1681 {
1682         PPC4xx_SYS_INFO board_cfg;
1683         unsigned long max_refresh_rate;
1684         unsigned long dimm_num;
1685         unsigned long refresh_rate_type;
1686         unsigned long refresh_rate;
1687         unsigned long rint;
1688         unsigned long sdram_freq;
1689         unsigned long sdr_ddrpll;
1690         unsigned long val;
1691
1692         /*------------------------------------------------------------------
1693          * Get the board configuration info.
1694          *-----------------------------------------------------------------*/
1695         get_sys_info(&board_cfg);
1696
1697         /*------------------------------------------------------------------
1698          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1699          *-----------------------------------------------------------------*/
1700         mfsdr(SDR0_DDR0, sdr_ddrpll);
1701         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1702
1703         max_refresh_rate = 0;
1704         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1705                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1706
1707                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1708                         refresh_rate_type &= 0x7F;
1709                         switch (refresh_rate_type) {
1710                         case 0:
1711                                 refresh_rate =  15625;
1712                                 break;
1713                         case 1:
1714                                 refresh_rate =   3906;
1715                                 break;
1716                         case 2:
1717                                 refresh_rate =   7812;
1718                                 break;
1719                         case 3:
1720                                 refresh_rate =  31250;
1721                                 break;
1722                         case 4:
1723                                 refresh_rate =  62500;
1724                                 break;
1725                         case 5:
1726                                 refresh_rate = 125000;
1727                                 break;
1728                         default:
1729                                 refresh_rate = 0;
1730                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1731                                        (unsigned int)dimm_num);
1732                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1733                                 spd_ddr_init_hang ();
1734                                 break;
1735                         }
1736
1737                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1738                 }
1739         }
1740
1741         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1742         mfsdram(SDRAM_RTR, val);
1743         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1744                 (SDRAM_RTR_RINT_ENCODE(rint)));
1745 }
1746
1747 /*------------------------------------------------------------------
1748  * This routine programs the SDRAM_TRx registers.
1749  *-----------------------------------------------------------------*/
1750 static void program_tr(unsigned long *dimm_populated,
1751                        unsigned char *iic0_dimm_addr,
1752                        unsigned long num_dimm_banks)
1753 {
1754         unsigned long dimm_num;
1755         unsigned long sdram_ddr1;
1756         unsigned long t_rp_ns;
1757         unsigned long t_rcd_ns;
1758         unsigned long t_rrd_ns;
1759         unsigned long t_ras_ns;
1760         unsigned long t_rc_ns;
1761         unsigned long t_rfc_ns;
1762         unsigned long t_wpc_ns;
1763         unsigned long t_wtr_ns;
1764         unsigned long t_rpc_ns;
1765         unsigned long t_rp_clk;
1766         unsigned long t_rcd_clk;
1767         unsigned long t_rrd_clk;
1768         unsigned long t_ras_clk;
1769         unsigned long t_rc_clk;
1770         unsigned long t_rfc_clk;
1771         unsigned long t_wpc_clk;
1772         unsigned long t_wtr_clk;
1773         unsigned long t_rpc_clk;
1774         unsigned long sdtr1, sdtr2, sdtr3;
1775         unsigned long ddr_check;
1776         unsigned long sdram_freq;
1777         unsigned long sdr_ddrpll;
1778
1779         PPC4xx_SYS_INFO board_cfg;
1780
1781         /*------------------------------------------------------------------
1782          * Get the board configuration info.
1783          *-----------------------------------------------------------------*/
1784         get_sys_info(&board_cfg);
1785
1786         mfsdr(SDR0_DDR0, sdr_ddrpll);
1787         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1788
1789         /*------------------------------------------------------------------
1790          * Handle the timing.  We need to find the worst case timing of all
1791          * the dimm modules installed.
1792          *-----------------------------------------------------------------*/
1793         t_rp_ns = 0;
1794         t_rrd_ns = 0;
1795         t_rcd_ns = 0;
1796         t_ras_ns = 0;
1797         t_rc_ns = 0;
1798         t_rfc_ns = 0;
1799         t_wpc_ns = 0;
1800         t_wtr_ns = 0;
1801         t_rpc_ns = 0;
1802         sdram_ddr1 = TRUE;
1803
1804         /* loop through all the DIMM slots on the board */
1805         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1806                 /* If a dimm is installed in a particular slot ... */
1807                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1808                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1809                                 sdram_ddr1 = TRUE;
1810                         else
1811                                 sdram_ddr1 = FALSE;
1812
1813                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1814                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1815                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1816                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1817                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1818                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1819                 }
1820         }
1821
1822         /*------------------------------------------------------------------
1823          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1824          *-----------------------------------------------------------------*/
1825         mfsdram(SDRAM_SDTR1, sdtr1);
1826         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1827                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1828
1829         /* default values */
1830         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1831         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1832
1833         /* normal operations */
1834         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1835         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1836
1837         mtsdram(SDRAM_SDTR1, sdtr1);
1838
1839         /*------------------------------------------------------------------
1840          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1841          *-----------------------------------------------------------------*/
1842         mfsdram(SDRAM_SDTR2, sdtr2);
1843         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1844                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1845                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1846                    SDRAM_SDTR2_RRD_MASK);
1847
1848         /*
1849          * convert t_rcd from nanoseconds to ddr clocks
1850          * round up if necessary
1851          */
1852         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1853         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1854         if (sdram_freq != ddr_check)
1855                 t_rcd_clk++;
1856
1857         switch (t_rcd_clk) {
1858         case 0:
1859         case 1:
1860                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1861                 break;
1862         case 2:
1863                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1864                 break;
1865         case 3:
1866                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1867                 break;
1868         case 4:
1869                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1870                 break;
1871         default:
1872                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1873                 break;
1874         }
1875
1876         if (sdram_ddr1 == TRUE) { /* DDR1 */
1877                 if (sdram_freq < 200000000) {
1878                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1879                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1880                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1881                 } else {
1882                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1883                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1884                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1885                 }
1886         } else { /* DDR2 */
1887                 /* loop through all the DIMM slots on the board */
1888                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1889                         /* If a dimm is installed in a particular slot ... */
1890                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1891                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1892                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1893                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1894                         }
1895                 }
1896
1897                 /*
1898                  * convert from nanoseconds to ddr clocks
1899                  * round up if necessary
1900                  */
1901                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1902                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1903                 if (sdram_freq != ddr_check)
1904                         t_wpc_clk++;
1905
1906                 switch (t_wpc_clk) {
1907                 case 0:
1908                 case 1:
1909                 case 2:
1910                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1911                         break;
1912                 case 3:
1913                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1914                         break;
1915                 case 4:
1916                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1917                         break;
1918                 case 5:
1919                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1920                         break;
1921                 default:
1922                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1923                         break;
1924                 }
1925
1926                 /*
1927                  * convert from nanoseconds to ddr clocks
1928                  * round up if necessary
1929                  */
1930                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1931                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1932                 if (sdram_freq != ddr_check)
1933                         t_wtr_clk++;
1934
1935                 switch (t_wtr_clk) {
1936                 case 0:
1937                 case 1:
1938                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1939                         break;
1940                 case 2:
1941                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1942                         break;
1943                 case 3:
1944                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1945                         break;
1946                 default:
1947                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1948                         break;
1949                 }
1950
1951                 /*
1952                  * convert from nanoseconds to ddr clocks
1953                  * round up if necessary
1954                  */
1955                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1956                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1957                 if (sdram_freq != ddr_check)
1958                         t_rpc_clk++;
1959
1960                 switch (t_rpc_clk) {
1961                 case 0:
1962                 case 1:
1963                 case 2:
1964                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1965                         break;
1966                 case 3:
1967                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1968                         break;
1969                 default:
1970                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1971                         break;
1972                 }
1973         }
1974
1975         /* default value */
1976         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1977
1978         /*
1979          * convert t_rrd from nanoseconds to ddr clocks
1980          * round up if necessary
1981          */
1982         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1983         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1984         if (sdram_freq != ddr_check)
1985                 t_rrd_clk++;
1986
1987         if (t_rrd_clk == 3)
1988                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1989         else
1990                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1991
1992         /*
1993          * convert t_rp from nanoseconds to ddr clocks
1994          * round up if necessary
1995          */
1996         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1997         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1998         if (sdram_freq != ddr_check)
1999                 t_rp_clk++;
2000
2001         switch (t_rp_clk) {
2002         case 0:
2003         case 1:
2004         case 2:
2005         case 3:
2006                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2007                 break;
2008         case 4:
2009                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2010                 break;
2011         case 5:
2012                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2013                 break;
2014         case 6:
2015                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2016                 break;
2017         default:
2018                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2019                 break;
2020         }
2021
2022         mtsdram(SDRAM_SDTR2, sdtr2);
2023
2024         /*------------------------------------------------------------------
2025          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2026          *-----------------------------------------------------------------*/
2027         mfsdram(SDRAM_SDTR3, sdtr3);
2028         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2029                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2030
2031         /*
2032          * convert t_ras from nanoseconds to ddr clocks
2033          * round up if necessary
2034          */
2035         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2036         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2037         if (sdram_freq != ddr_check)
2038                 t_ras_clk++;
2039
2040         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2041
2042         /*
2043          * convert t_rc from nanoseconds to ddr clocks
2044          * round up if necessary
2045          */
2046         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2047         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2048         if (sdram_freq != ddr_check)
2049                 t_rc_clk++;
2050
2051         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2052
2053         /* default xcs value */
2054         sdtr3 |= SDRAM_SDTR3_XCS;
2055
2056         /*
2057          * convert t_rfc from nanoseconds to ddr clocks
2058          * round up if necessary
2059          */
2060         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2061         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2062         if (sdram_freq != ddr_check)
2063                 t_rfc_clk++;
2064
2065         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2066
2067         mtsdram(SDRAM_SDTR3, sdtr3);
2068 }
2069
2070 /*-----------------------------------------------------------------------------+
2071  * program_bxcf.
2072  *-----------------------------------------------------------------------------*/
2073 static void program_bxcf(unsigned long *dimm_populated,
2074                          unsigned char *iic0_dimm_addr,
2075                          unsigned long num_dimm_banks)
2076 {
2077         unsigned long dimm_num;
2078         unsigned long num_col_addr;
2079         unsigned long num_ranks;
2080         unsigned long num_banks;
2081         unsigned long mode;
2082         unsigned long ind_rank;
2083         unsigned long ind;
2084         unsigned long ind_bank;
2085         unsigned long bank_0_populated;
2086
2087         /*------------------------------------------------------------------
2088          * Set the BxCF regs.  First, wipe out the bank config registers.
2089          *-----------------------------------------------------------------*/
2090         mtsdram(SDRAM_MB0CF, 0x00000000);
2091         mtsdram(SDRAM_MB1CF, 0x00000000);
2092         mtsdram(SDRAM_MB2CF, 0x00000000);
2093         mtsdram(SDRAM_MB3CF, 0x00000000);
2094
2095         mode = SDRAM_BXCF_M_BE_ENABLE;
2096
2097         bank_0_populated = 0;
2098
2099         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2100                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2101                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2102                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2103                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2104                                 num_ranks = (num_ranks & 0x0F) +1;
2105                         else
2106                                 num_ranks = num_ranks & 0x0F;
2107
2108                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2109
2110                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2111                                 if (num_banks == 4)
2112                                         ind = 0;
2113                                 else
2114                                         ind = 5 << 8;
2115                                 switch (num_col_addr) {
2116                                 case 0x08:
2117                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2118                                         break;
2119                                 case 0x09:
2120                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2121                                         break;
2122                                 case 0x0A:
2123                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2124                                         break;
2125                                 case 0x0B:
2126                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2127                                         break;
2128                                 case 0x0C:
2129                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2130                                         break;
2131                                 default:
2132                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2133                                                (unsigned int)dimm_num);
2134                                         printf("ERROR: Unsupported value for number of "
2135                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2136                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2137                                         spd_ddr_init_hang ();
2138                                 }
2139                         }
2140
2141                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2142                                 bank_0_populated = 1;
2143
2144                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2145                                 mtsdram(SDRAM_MB0CF +
2146                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2147                                         mode);
2148                         }
2149                 }
2150         }
2151 }
2152
2153 /*------------------------------------------------------------------
2154  * program memory queue.
2155  *-----------------------------------------------------------------*/
2156 static void program_memory_queue(unsigned long *dimm_populated,
2157                                  unsigned char *iic0_dimm_addr,
2158                                  unsigned long num_dimm_banks)
2159 {
2160         unsigned long dimm_num;
2161         phys_size_t rank_base_addr;
2162         unsigned long rank_reg;
2163         phys_size_t rank_size_bytes;
2164         unsigned long rank_size_id;
2165         unsigned long num_ranks;
2166         unsigned long baseadd_size;
2167         unsigned long i;
2168         unsigned long bank_0_populated = 0;
2169         phys_size_t total_size = 0;
2170
2171         /*------------------------------------------------------------------
2172          * Reset the rank_base_address.
2173          *-----------------------------------------------------------------*/
2174         rank_reg   = SDRAM_R0BAS;
2175
2176         rank_base_addr = 0x00000000;
2177
2178         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2179                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2180                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2181                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2182                                 num_ranks = (num_ranks & 0x0F) + 1;
2183                         else
2184                                 num_ranks = num_ranks & 0x0F;
2185
2186                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2187
2188                         /*------------------------------------------------------------------
2189                          * Set the sizes
2190                          *-----------------------------------------------------------------*/
2191                         baseadd_size = 0;
2192                         switch (rank_size_id) {
2193                         case 0x01:
2194                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2195                                 total_size = 1024;
2196                                 break;
2197                         case 0x02:
2198                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2199                                 total_size = 2048;
2200                                 break;
2201                         case 0x04:
2202                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2203                                 total_size = 4096;
2204                                 break;
2205                         case 0x08:
2206                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2207                                 total_size = 32;
2208                                 break;
2209                         case 0x10:
2210                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2211                                 total_size = 64;
2212                                 break;
2213                         case 0x20:
2214                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2215                                 total_size = 128;
2216                                 break;
2217                         case 0x40:
2218                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2219                                 total_size = 256;
2220                                 break;
2221                         case 0x80:
2222                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2223                                 total_size = 512;
2224                                 break;
2225                         default:
2226                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2227                                        (unsigned int)dimm_num);
2228                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2229                                        (unsigned int)rank_size_id);
2230                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2231                                 spd_ddr_init_hang ();
2232                         }
2233                         rank_size_bytes = total_size << 20;
2234
2235                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2236                                 bank_0_populated = 1;
2237
2238                         for (i = 0; i < num_ranks; i++) {
2239                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2240                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2241                                            baseadd_size));
2242                                 rank_base_addr += rank_size_bytes;
2243                         }
2244                 }
2245         }
2246
2247 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2248     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2249     defined(CONFIG_460SX)
2250         /*
2251          * Enable high bandwidth access
2252          * This is currently not used, but with this setup
2253          * it is possible to use it later on in e.g. the Linux
2254          * EMAC driver for performance gain.
2255          */
2256         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2257         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2258
2259         /*
2260          * Set optimal value for Memory Queue HB/LL Configuration registers
2261          */
2262         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2263               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2264               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2265         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2266               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2267               SDRAM_CONF1LL_RPLM);
2268         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2269 #endif
2270 }
2271
2272 /*-----------------------------------------------------------------------------+
2273  * is_ecc_enabled.
2274  *-----------------------------------------------------------------------------*/
2275 static unsigned long is_ecc_enabled(void)
2276 {
2277         unsigned long dimm_num;
2278         unsigned long ecc;
2279         unsigned long val;
2280
2281         ecc = 0;
2282         /* loop through all the DIMM slots on the board */
2283         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2284                 mfsdram(SDRAM_MCOPT1, val);
2285                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2286         }
2287
2288         return ecc;
2289 }
2290
2291 #ifdef CONFIG_DDR_ECC
2292 /*-----------------------------------------------------------------------------+
2293  * program_ecc.
2294  *-----------------------------------------------------------------------------*/
2295 static void program_ecc(unsigned long *dimm_populated,
2296                         unsigned char *iic0_dimm_addr,
2297                         unsigned long num_dimm_banks,
2298                         unsigned long tlb_word2_i_value)
2299 {
2300         unsigned long mcopt1;
2301         unsigned long mcopt2;
2302         unsigned long mcstat;
2303         unsigned long dimm_num;
2304         unsigned long ecc;
2305
2306         ecc = 0;
2307         /* loop through all the DIMM slots on the board */
2308         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2309                 /* If a dimm is installed in a particular slot ... */
2310                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2311                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2312         }
2313         if (ecc == 0)
2314                 return;
2315
2316         if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2317                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2318                 return;
2319         }
2320
2321         mfsdram(SDRAM_MCOPT1, mcopt1);
2322         mfsdram(SDRAM_MCOPT2, mcopt2);
2323
2324         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2325                 /* DDR controller must be enabled and not in self-refresh. */
2326                 mfsdram(SDRAM_MCSTAT, mcstat);
2327                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2328                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2329                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2330                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2331
2332                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2333                 }
2334         }
2335
2336         return;
2337 }
2338
2339 static void wait_ddr_idle(void)
2340 {
2341         u32 val;
2342
2343         do {
2344                 mfsdram(SDRAM_MCSTAT, val);
2345         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2346 }
2347
2348 /*-----------------------------------------------------------------------------+
2349  * program_ecc_addr.
2350  *-----------------------------------------------------------------------------*/
2351 static void program_ecc_addr(unsigned long start_address,
2352                              unsigned long num_bytes,
2353                              unsigned long tlb_word2_i_value)
2354 {
2355         unsigned long current_address;
2356         unsigned long end_address;
2357         unsigned long address_increment;
2358         unsigned long mcopt1;
2359         char str[] = "ECC generation -";
2360         char slash[] = "\\|/-\\|/-";
2361         int loop = 0;
2362         int loopi = 0;
2363
2364         current_address = start_address;
2365         mfsdram(SDRAM_MCOPT1, mcopt1);
2366         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2367                 mtsdram(SDRAM_MCOPT1,
2368                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2369                 sync();
2370                 eieio();
2371                 wait_ddr_idle();
2372
2373                 puts(str);
2374                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2375                         /* ECC bit set method for non-cached memory */
2376                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2377                                 address_increment = 4;
2378                         else
2379                                 address_increment = 8;
2380                         end_address = current_address + num_bytes;
2381
2382                         while (current_address < end_address) {
2383                                 *((unsigned long *)current_address) = 0x00000000;
2384                                 current_address += address_increment;
2385
2386                                 if ((loop++ % (2 << 20)) == 0) {
2387                                         putc('\b');
2388                                         putc(slash[loopi++ % 8]);
2389                                 }
2390                         }
2391
2392                 } else {
2393                         /* ECC bit set method for cached memory */
2394                         dcbz_area(start_address, num_bytes);
2395                         /* Write modified dcache lines back to memory */
2396                         clean_dcache_range(start_address, start_address + num_bytes);
2397                 }
2398
2399                 blank_string(strlen(str));
2400
2401                 sync();
2402                 eieio();
2403                 wait_ddr_idle();
2404
2405                 /* clear ECC error repoting registers */
2406                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2407                 mtdcr(0x4c, 0xffffffff);
2408
2409                 mtsdram(SDRAM_MCOPT1,
2410                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2411                 sync();
2412                 eieio();
2413                 wait_ddr_idle();
2414         }
2415 }
2416 #endif
2417
2418 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2419 /*-----------------------------------------------------------------------------+
2420  * program_DQS_calibration.
2421  *-----------------------------------------------------------------------------*/
2422 static void program_DQS_calibration(unsigned long *dimm_populated,
2423                                     unsigned char *iic0_dimm_addr,
2424                                     unsigned long num_dimm_banks)
2425 {
2426         unsigned long val;
2427
2428 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2429         mtsdram(SDRAM_RQDC, 0x80000037);
2430         mtsdram(SDRAM_RDCC, 0x40000000);
2431         mtsdram(SDRAM_RFDC, 0x000001DF);
2432
2433         test();
2434 #else
2435         /*------------------------------------------------------------------
2436          * Program RDCC register
2437          * Read sample cycle auto-update enable
2438          *-----------------------------------------------------------------*/
2439
2440         mfsdram(SDRAM_RDCC, val);
2441         mtsdram(SDRAM_RDCC,
2442                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2443                 | SDRAM_RDCC_RSAE_ENABLE);
2444
2445         /*------------------------------------------------------------------
2446          * Program RQDC register
2447          * Internal DQS delay mechanism enable
2448          *-----------------------------------------------------------------*/
2449         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2450
2451         /*------------------------------------------------------------------
2452          * Program RFDC register
2453          * Set Feedback Fractional Oversample
2454          * Auto-detect read sample cycle enable
2455          * Set RFOS to 1/4 of memclk cycle (0x3f)
2456          *-----------------------------------------------------------------*/
2457         mfsdram(SDRAM_RFDC, val);
2458         mtsdram(SDRAM_RFDC,
2459                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2460                          SDRAM_RFDC_RFFD_MASK))
2461                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2462                    SDRAM_RFDC_RFFD_ENCODE(0)));
2463
2464         DQS_calibration_process();
2465 #endif
2466 }
2467
2468 static int short_mem_test(void)
2469 {
2470         u32 *membase;
2471         u32 bxcr_num;
2472         u32 bxcf;
2473         int i;
2474         int j;
2475         phys_size_t base_addr;
2476         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2477                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2478                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2479                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2480                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2481                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2482                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2483                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2484                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2485                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2486                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2487                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2488                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2489                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2490                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2491                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2492                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2493         int l;
2494
2495         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2496                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2497
2498                 /* Banks enabled */
2499                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2500                         /* Bank is enabled */
2501
2502                         /*
2503                          * Only run test on accessable memory (below 2GB)
2504                          */
2505                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2506                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2507                                 continue;
2508
2509                         /*------------------------------------------------------------------
2510                          * Run the short memory test.
2511                          *-----------------------------------------------------------------*/
2512                         membase = (u32 *)(u32)base_addr;
2513
2514                         for (i = 0; i < NUMMEMTESTS; i++) {
2515                                 for (j = 0; j < NUMMEMWORDS; j++) {
2516                                         membase[j] = test[i][j];
2517                                         ppcDcbf((u32)&(membase[j]));
2518                                 }
2519                                 sync();
2520                                 for (l=0; l<NUMLOOPS; l++) {
2521                                         for (j = 0; j < NUMMEMWORDS; j++) {
2522                                                 if (membase[j] != test[i][j]) {
2523                                                         ppcDcbf((u32)&(membase[j]));
2524                                                         return 0;
2525                                                 }
2526                                                 ppcDcbf((u32)&(membase[j]));
2527                                         }
2528                                         sync();
2529                                 }
2530                         }
2531                 }       /* if bank enabled */
2532         }               /* for bxcf_num */
2533
2534         return 1;
2535 }
2536
2537 #ifndef HARD_CODED_DQS
2538 /*-----------------------------------------------------------------------------+
2539  * DQS_calibration_process.
2540  *-----------------------------------------------------------------------------*/
2541 static void DQS_calibration_process(void)
2542 {
2543         unsigned long rfdc_reg;
2544         unsigned long rffd;
2545         unsigned long val;
2546         long rffd_average;
2547         long max_start;
2548         long min_end;
2549         unsigned long begin_rqfd[MAXRANKS];
2550         unsigned long begin_rffd[MAXRANKS];
2551         unsigned long end_rqfd[MAXRANKS];
2552         unsigned long end_rffd[MAXRANKS];
2553         char window_found;
2554         unsigned long dlycal;
2555         unsigned long dly_val;
2556         unsigned long max_pass_length;
2557         unsigned long current_pass_length;
2558         unsigned long current_fail_length;
2559         unsigned long current_start;
2560         long max_end;
2561         unsigned char fail_found;
2562         unsigned char pass_found;
2563 #if !defined(CONFIG_DDR_RQDC_FIXED)
2564         u32 rqdc_reg;
2565         u32 rqfd;
2566         u32 rqfd_start;
2567         u32 rqfd_average;
2568         int loopi = 0;
2569         char str[] = "Auto calibration -";
2570         char slash[] = "\\|/-\\|/-";
2571
2572         /*------------------------------------------------------------------
2573          * Test to determine the best read clock delay tuning bits.
2574          *
2575          * Before the DDR controller can be used, the read clock delay needs to be
2576          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2577          * This value cannot be hardcoded into the program because it changes
2578          * depending on the board's setup and environment.
2579          * To do this, all delay values are tested to see if they
2580          * work or not.  By doing this, you get groups of fails with groups of
2581          * passing values.  The idea is to find the start and end of a passing
2582          * window and take the center of it to use as the read clock delay.
2583          *
2584          * A failure has to be seen first so that when we hit a pass, we know
2585          * that it is truely the start of the window.  If we get passing values
2586          * to start off with, we don't know if we are at the start of the window.
2587          *
2588          * The code assumes that a failure will always be found.
2589          * If a failure is not found, there is no easy way to get the middle
2590          * of the passing window.  I guess we can pretty much pick any value
2591          * but some values will be better than others.  Since the lowest speed
2592          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2593          * from experimentation it is safe to say you will always have a failure.
2594          *-----------------------------------------------------------------*/
2595
2596         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2597         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2598
2599         puts(str);
2600
2601 calibration_loop:
2602         mfsdram(SDRAM_RQDC, rqdc_reg);
2603         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2604                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2605 #else /* CONFIG_DDR_RQDC_FIXED */
2606         /*
2607          * On Katmai the complete auto-calibration somehow doesn't seem to
2608          * produce the best results, meaning optimal values for RQFD/RFFD.
2609          * This was discovered by GDA using a high bandwidth scope,
2610          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2611          * so now on Katmai "only" RFFD is auto-calibrated.
2612          */
2613         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2614 #endif /* CONFIG_DDR_RQDC_FIXED */
2615
2616         max_start = 0;
2617         min_end = 0;
2618         begin_rqfd[0] = 0;
2619         begin_rffd[0] = 0;
2620         begin_rqfd[1] = 0;
2621         begin_rffd[1] = 0;
2622         end_rqfd[0] = 0;
2623         end_rffd[0] = 0;
2624         end_rqfd[1] = 0;
2625         end_rffd[1] = 0;
2626         window_found = FALSE;
2627
2628         max_pass_length = 0;
2629         max_start = 0;
2630         max_end = 0;
2631         current_pass_length = 0;
2632         current_fail_length = 0;
2633         current_start = 0;
2634         window_found = FALSE;
2635         fail_found = FALSE;
2636         pass_found = FALSE;
2637
2638         /*
2639          * get the delay line calibration register value
2640          */
2641         mfsdram(SDRAM_DLCR, dlycal);
2642         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2643
2644         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2645                 mfsdram(SDRAM_RFDC, rfdc_reg);
2646                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2647
2648                 /*------------------------------------------------------------------
2649                  * Set the timing reg for the test.
2650                  *-----------------------------------------------------------------*/
2651                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2652
2653                 /*------------------------------------------------------------------
2654                  * See if the rffd value passed.
2655                  *-----------------------------------------------------------------*/
2656                 if (short_mem_test()) {
2657                         if (fail_found == TRUE) {
2658                                 pass_found = TRUE;
2659                                 if (current_pass_length == 0)
2660                                         current_start = rffd;
2661
2662                                 current_fail_length = 0;
2663                                 current_pass_length++;
2664
2665                                 if (current_pass_length > max_pass_length) {
2666                                         max_pass_length = current_pass_length;
2667                                         max_start = current_start;
2668                                         max_end = rffd;
2669                                 }
2670                         }
2671                 } else {
2672                         current_pass_length = 0;
2673                         current_fail_length++;
2674
2675                         if (current_fail_length >= (dly_val >> 2)) {
2676                                 if (fail_found == FALSE) {
2677                                         fail_found = TRUE;
2678                                 } else if (pass_found == TRUE) {
2679                                         window_found = TRUE;
2680                                         break;
2681                                 }
2682                         }
2683                 }
2684         }               /* for rffd */
2685
2686         /*------------------------------------------------------------------
2687          * Set the average RFFD value
2688          *-----------------------------------------------------------------*/
2689         rffd_average = ((max_start + max_end) >> 1);
2690
2691         if (rffd_average < 0)
2692                 rffd_average = 0;
2693
2694         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2695                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2696         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2697         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2698
2699 #if !defined(CONFIG_DDR_RQDC_FIXED)
2700         max_pass_length = 0;
2701         max_start = 0;
2702         max_end = 0;
2703         current_pass_length = 0;
2704         current_fail_length = 0;
2705         current_start = 0;
2706         window_found = FALSE;
2707         fail_found = FALSE;
2708         pass_found = FALSE;
2709
2710         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2711                 mfsdram(SDRAM_RQDC, rqdc_reg);
2712                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2713
2714                 /*------------------------------------------------------------------
2715                  * Set the timing reg for the test.
2716                  *-----------------------------------------------------------------*/
2717                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2718
2719                 /*------------------------------------------------------------------
2720                  * See if the rffd value passed.
2721                  *-----------------------------------------------------------------*/
2722                 if (short_mem_test()) {
2723                         if (fail_found == TRUE) {
2724                                 pass_found = TRUE;
2725                                 if (current_pass_length == 0)
2726                                         current_start = rqfd;
2727
2728                                 current_fail_length = 0;
2729                                 current_pass_length++;
2730
2731                                 if (current_pass_length > max_pass_length) {
2732                                         max_pass_length = current_pass_length;
2733                                         max_start = current_start;
2734                                         max_end = rqfd;
2735                                 }
2736                         }
2737                 } else {
2738                         current_pass_length = 0;
2739                         current_fail_length++;
2740
2741                         if (fail_found == FALSE) {
2742                                 fail_found = TRUE;
2743                         } else if (pass_found == TRUE) {
2744                                 window_found = TRUE;
2745                                 break;
2746                         }
2747                 }
2748         }
2749
2750         rqfd_average = ((max_start + max_end) >> 1);
2751
2752         /*------------------------------------------------------------------
2753          * Make sure we found the valid read passing window.  Halt if not
2754          *-----------------------------------------------------------------*/
2755         if (window_found == FALSE) {
2756                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2757                         putc('\b');
2758                         putc(slash[loopi++ % 8]);
2759
2760                         /* try again from with a different RQFD start value */
2761                         rqfd_start++;
2762                         goto calibration_loop;
2763                 }
2764
2765                 printf("\nERROR: Cannot determine a common read delay for the "
2766                        "DIMM(s) installed.\n");
2767                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2768                 ppc4xx_ibm_ddr2_register_dump();
2769                 spd_ddr_init_hang ();
2770         }
2771
2772         if (rqfd_average < 0)
2773                 rqfd_average = 0;
2774
2775         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2776                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2777
2778         mtsdram(SDRAM_RQDC,
2779                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2780                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2781
2782         blank_string(strlen(str));
2783 #endif /* CONFIG_DDR_RQDC_FIXED */
2784
2785         /*
2786          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2787          * PowerPC440SP/SPe DDR2 application note:
2788          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2789          */
2790         mfsdram(SDRAM_RTSR, val);
2791         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2792                 mfsdram(SDRAM_RDCC, val);
2793                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2794                         val += 0x40000000;
2795                         mtsdram(SDRAM_RDCC, val);
2796                 }
2797         }
2798
2799         mfsdram(SDRAM_DLCR, val);
2800         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2801         mfsdram(SDRAM_RQDC, val);
2802         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2803         mfsdram(SDRAM_RFDC, val);
2804         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2805         mfsdram(SDRAM_RDCC, val);
2806         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2807 }
2808 #else /* calibration test with hardvalues */
2809 /*-----------------------------------------------------------------------------+
2810  * DQS_calibration_process.
2811  *-----------------------------------------------------------------------------*/
2812 static void test(void)
2813 {
2814         unsigned long dimm_num;
2815         unsigned long ecc_temp;
2816         unsigned long i, j;
2817         unsigned long *membase;
2818         unsigned long bxcf[MAXRANKS];
2819         unsigned long val;
2820         char window_found;
2821         char begin_found[MAXDIMMS];
2822         char end_found[MAXDIMMS];
2823         char search_end[MAXDIMMS];
2824         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2825                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2826                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2827                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2828                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2829                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2830                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2831                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2832                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2833                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2834                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2835                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2836                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2837                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2838                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2839                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2840                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2841
2842         /*------------------------------------------------------------------
2843          * Test to determine the best read clock delay tuning bits.
2844          *
2845          * Before the DDR controller can be used, the read clock delay needs to be
2846          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2847          * This value cannot be hardcoded into the program because it changes
2848          * depending on the board's setup and environment.
2849          * To do this, all delay values are tested to see if they
2850          * work or not.  By doing this, you get groups of fails with groups of
2851          * passing values.  The idea is to find the start and end of a passing
2852          * window and take the center of it to use as the read clock delay.
2853          *
2854          * A failure has to be seen first so that when we hit a pass, we know
2855          * that it is truely the start of the window.  If we get passing values
2856          * to start off with, we don't know if we are at the start of the window.
2857          *
2858          * The code assumes that a failure will always be found.
2859          * If a failure is not found, there is no easy way to get the middle
2860          * of the passing window.  I guess we can pretty much pick any value
2861          * but some values will be better than others.  Since the lowest speed
2862          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2863          * from experimentation it is safe to say you will always have a failure.
2864          *-----------------------------------------------------------------*/
2865         mfsdram(SDRAM_MCOPT1, ecc_temp);
2866         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2867         mfsdram(SDRAM_MCOPT1, val);
2868         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2869                 SDRAM_MCOPT1_MCHK_NON);
2870
2871         window_found = FALSE;
2872         begin_found[0] = FALSE;
2873         end_found[0] = FALSE;
2874         search_end[0] = FALSE;
2875         begin_found[1] = FALSE;
2876         end_found[1] = FALSE;
2877         search_end[1] = FALSE;
2878
2879         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2880                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2881
2882                 /* Banks enabled */
2883                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2884
2885                         /* Bank is enabled */
2886                         membase =
2887                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2888
2889                         /*------------------------------------------------------------------
2890                          * Run the short memory test.
2891                          *-----------------------------------------------------------------*/
2892                         for (i = 0; i < NUMMEMTESTS; i++) {
2893                                 for (j = 0; j < NUMMEMWORDS; j++) {
2894                                         membase[j] = test[i][j];
2895                                         ppcDcbf((u32)&(membase[j]));
2896                                 }
2897                                 sync();
2898                                 for (j = 0; j < NUMMEMWORDS; j++) {
2899                                         if (membase[j] != test[i][j]) {
2900                                                 ppcDcbf((u32)&(membase[j]));
2901                                                 break;
2902                                         }
2903                                         ppcDcbf((u32)&(membase[j]));
2904                                 }
2905                                 sync();
2906                                 if (j < NUMMEMWORDS)
2907                                         break;
2908                         }
2909
2910                         /*------------------------------------------------------------------
2911                          * See if the rffd value passed.
2912                          *-----------------------------------------------------------------*/
2913                         if (i < NUMMEMTESTS) {
2914                                 if ((end_found[dimm_num] == FALSE) &&
2915                                     (search_end[dimm_num] == TRUE)) {
2916                                         end_found[dimm_num] = TRUE;
2917                                 }
2918                                 if ((end_found[0] == TRUE) &&
2919                                     (end_found[1] == TRUE))
2920                                         break;
2921                         } else {
2922                                 if (begin_found[dimm_num] == FALSE) {
2923                                         begin_found[dimm_num] = TRUE;
2924                                         search_end[dimm_num] = TRUE;
2925                                 }
2926                         }
2927                 } else {
2928                         begin_found[dimm_num] = TRUE;
2929                         end_found[dimm_num] = TRUE;
2930                 }
2931         }
2932
2933         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2934                 window_found = TRUE;
2935
2936         /*------------------------------------------------------------------
2937          * Make sure we found the valid read passing window.  Halt if not
2938          *-----------------------------------------------------------------*/
2939         if (window_found == FALSE) {
2940                 printf("ERROR: Cannot determine a common read delay for the "
2941                        "DIMM(s) installed.\n");
2942                 spd_ddr_init_hang ();
2943         }
2944
2945         /*------------------------------------------------------------------
2946          * Restore the ECC variable to what it originally was
2947          *-----------------------------------------------------------------*/
2948         mtsdram(SDRAM_MCOPT1,
2949                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2950                 | ecc_temp);
2951 }
2952 #endif /* !HARD_CODED_DQS */
2953 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2954
2955 #else /* CONFIG_SPD_EEPROM */
2956
2957 /*-----------------------------------------------------------------------------
2958  * Function:    initdram
2959  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2960  *              The configuration is performed using static, compile-
2961  *              time parameters.
2962  *              Configures the PPC405EX(r) and PPC460EX/GT
2963  *---------------------------------------------------------------------------*/
2964 phys_size_t initdram(int board_type)
2965 {
2966         /*
2967          * Only run this SDRAM init code once. For NAND booting
2968          * targets like Kilauea, we call initdram() early from the
2969          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2970          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2971          * which calls initdram() again. This time the controller
2972          * mustn't be reconfigured again since we're already running
2973          * from SDRAM.
2974          */
2975 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2976         unsigned long val;
2977
2978 #if defined(CONFIG_440)
2979         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2980         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2981         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2982         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2983         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2984         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2985         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2986         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2987         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2988 #endif
2989
2990         /* Set Memory Bank Configuration Registers */
2991
2992         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2993         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2994         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2995         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2996
2997         /* Set Memory Clock Timing Register */
2998
2999         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3000
3001         /* Set Refresh Time Register */
3002
3003         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3004
3005         /* Set SDRAM Timing Registers */
3006
3007         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3008         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3009         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3010
3011         /* Set Mode and Extended Mode Registers */
3012
3013         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3014         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3015
3016         /* Set Memory Controller Options 1 Register */
3017
3018         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3019
3020         /* Set Manual Initialization Control Registers */
3021
3022         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3023         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3024         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3025         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3026         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3027         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3028         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3029         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3030         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3031         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3032         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3033         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3034         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3035         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3036         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3037         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3038
3039         /* Set On-Die Termination Registers */
3040
3041         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3042         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3043         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3044
3045         /* Set Write Timing Register */
3046
3047         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3048
3049         /*
3050          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3051          * SDRAM0_MCOPT2[IPTR] = 1
3052          */
3053
3054         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3055                                SDRAM_MCOPT2_IPTR_EXECUTE));
3056
3057         /*
3058          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3059          * completion of initialization.
3060          */
3061
3062         do {
3063                 mfsdram(SDRAM_MCSTAT, val);
3064         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3065
3066         /* Set Delay Control Registers */
3067
3068         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3069
3070 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3071         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3072         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3073         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3074 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3075
3076         /*
3077          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3078          */
3079
3080         mfsdram(SDRAM_MCOPT2, val);
3081         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3082
3083 #if defined(CONFIG_440)
3084         /*
3085          * Program TLB entries with caches enabled, for best performace
3086          * while auto-calibrating and ECC generation
3087          */
3088         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3089 #endif
3090
3091 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3092 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3093         /*------------------------------------------------------------------
3094          | DQS calibration.
3095          +-----------------------------------------------------------------*/
3096         DQS_autocalibration();
3097 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3098 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3099
3100 #if defined(CONFIG_DDR_ECC)
3101         ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
3102 #endif /* defined(CONFIG_DDR_ECC) */
3103
3104 #if defined(CONFIG_440)
3105         /*
3106          * Now after initialization (auto-calibration and ECC generation)
3107          * remove the TLB entries with caches enabled and program again with
3108          * desired cache functionality
3109          */
3110         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3111         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3112 #endif
3113
3114         ppc4xx_ibm_ddr2_register_dump();
3115
3116 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3117         /*
3118          * Clear potential errors resulting from auto-calibration.
3119          * If not done, then we could get an interrupt later on when
3120          * exceptions are enabled.
3121          */
3122         set_mcsr(get_mcsr());
3123 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3124
3125 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3126
3127         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3128 }
3129 #endif /* CONFIG_SPD_EEPROM */
3130
3131 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3132 #if defined(CONFIG_440)
3133 u32 mfdcr_any(u32 dcr)
3134 {
3135         u32 val;
3136
3137         switch (dcr) {
3138         case SDRAM_R0BAS + 0:
3139                 val = mfdcr(SDRAM_R0BAS + 0);
3140                 break;
3141         case SDRAM_R0BAS + 1:
3142                 val = mfdcr(SDRAM_R0BAS + 1);
3143                 break;
3144         case SDRAM_R0BAS + 2:
3145                 val = mfdcr(SDRAM_R0BAS + 2);
3146                 break;
3147         case SDRAM_R0BAS + 3:
3148                 val = mfdcr(SDRAM_R0BAS + 3);
3149                 break;
3150         default:
3151                 printf("DCR %d not defined in case statement!!!\n", dcr);
3152                 val = 0; /* just to satisfy the compiler */
3153         }
3154
3155         return val;
3156 }
3157
3158 void mtdcr_any(u32 dcr, u32 val)
3159 {
3160         switch (dcr) {
3161         case SDRAM_R0BAS + 0:
3162                 mtdcr(SDRAM_R0BAS + 0, val);
3163                 break;
3164         case SDRAM_R0BAS + 1:
3165                 mtdcr(SDRAM_R0BAS + 1, val);
3166                 break;
3167         case SDRAM_R0BAS + 2:
3168                 mtdcr(SDRAM_R0BAS + 2, val);
3169                 break;
3170         case SDRAM_R0BAS + 3:
3171                 mtdcr(SDRAM_R0BAS + 3, val);
3172                 break;
3173         default:
3174                 printf("DCR %d not defined in case statement!!!\n", dcr);
3175         }
3176 }
3177 #endif /* defined(CONFIG_440) */
3178
3179 void blank_string(int size)
3180 {
3181         int i;
3182
3183         for (i = 0; i < size; i++)
3184                 putc('\b');
3185         for (i = 0; i < size; i++)
3186                 putc(' ');
3187         for (i = 0; i < size; i++)
3188                 putc('\b');
3189 }
3190 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3191
3192 inline void ppc4xx_ibm_ddr2_register_dump(void)
3193 {
3194 #if defined(DEBUG)
3195         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3196
3197 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3198      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3199         PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3200         PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3201         PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3202         PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3203 #endif /* (defined(CONFIG_440SP) || ... */
3204 #if defined(CONFIG_405EX)
3205         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3206         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3207         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3208         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3209         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3210         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3211 #endif /* defined(CONFIG_405EX) */
3212         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3213         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3214         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3215         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3216         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3217         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3218         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3219         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3220         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3221         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3222         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3223         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3224 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3225      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3226         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3227         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3228         /*
3229          * OPART is only used as a trigger register.
3230          *
3231          * No data is contained in this register, and reading or writing
3232          * to is can cause bad things to happen (hangs). Just skip it and
3233          * report "N/A".
3234          */
3235         printf("%20s = N/A\n", "SDRAM_OPART");
3236 #endif /* defined(CONFIG_440SP) || ... */
3237         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3238         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3239         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3240         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3241         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3242         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3243         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3244         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3245         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3246         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3247         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3248         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3249         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3250         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3251         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3252         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3253         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3254         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3255         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3256         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3257         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3258         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3259         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3260         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3261         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3262         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3263         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3264         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3265         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3266 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3267      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3268         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3269 #endif /* defined(CONFIG_440SP) || ... */
3270         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3271         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3272         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3273 #endif /* defined(DEBUG) */
3274 }
3275
3276 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */