2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/types.h>
34 #include <asm/errno.h>
36 #include <asm/arch/clock.h>
37 #include <asm/arch/imx-regs.h>
38 #include <asm/arch/regs-bch.h>
39 #include <asm/arch/regs-gpmi.h>
40 #include <asm/arch/sys_proto.h>
41 #include <asm/arch/dma.h>
43 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
46 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
48 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE (512 / 4)
51 #define MXS_NAND_METADATA_SIZE 10
53 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
55 /* BCH timeout in microseconds */
56 #define MXS_NAND_BCH_TIMEOUT 10000
58 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
59 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
60 struct mxs_nand_info {
63 uint32_t cmd_queue_len;
64 uint32_t data_buf_size;
70 uint8_t marking_block_bad;
73 /* Functions with altered behaviour */
74 int (*hooked_read_oob)(struct mtd_info *mtd,
75 loff_t from, struct mtd_oob_ops *ops);
76 int (*hooked_write_oob)(struct mtd_info *mtd,
77 loff_t to, struct mtd_oob_ops *ops);
78 int (*hooked_block_markbad)(struct mtd_info *mtd,
82 struct mxs_dma_desc **desc;
87 #define dump_reg(b, r) __dump_reg(&b->r, #r)
88 static inline void __dump_reg(void *addr, const char *name)
90 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
93 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
94 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
95 static inline void dump_regs(void)
99 dump_bch_reg(status0);
101 dump_bch_reg(debug0);
102 dump_bch_reg(dbgkesread);
103 dump_bch_reg(dbgcsferead);
104 dump_bch_reg(dbgsyndegread);
105 dump_bch_reg(dbgahbmread);
106 dump_bch_reg(blockname);
107 dump_bch_reg(version);
110 dump_gpmi_reg(ctrl0);
111 dump_gpmi_reg(eccctrl);
112 dump_gpmi_reg(ecccount);
113 dump_gpmi_reg(payload);
114 dump_gpmi_reg(auxiliary);
115 dump_gpmi_reg(ctrl1);
118 dump_gpmi_reg(debug);
119 dump_gpmi_reg(version);
120 dump_gpmi_reg(debug2);
121 dump_gpmi_reg(debug3);
124 static inline int dbg_addr(void *addr)
126 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
131 static inline u32 mxs_readl(void *addr,
132 const char *fn, int ln)
134 u32 val = readl(addr);
135 static void *last_addr;
141 if (addr != last_addr || last_val != val) {
142 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
149 static inline void mxs_writel(u32 val, void *addr,
150 const char *fn, int ln)
153 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
156 printf(" result: %08x\n", readl(addr));
160 #define readl(a) mxs_readl(a, __func__, __LINE__)
163 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
164 static inline void memdump(const void *addr, size_t len)
166 const char *buf = addr;
169 for (i = 0; i < len; i++) {
173 printf("%p:", &buf[i]);
175 printf(" %02x", buf[i]);
180 static inline void memdump(void *addr, size_t len)
184 static inline void dump_regs(void)
189 struct nand_ecclayout fake_ecc_layout;
192 * Cache management functions
194 #ifndef CONFIG_SYS_DCACHE_OFF
195 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
197 uint32_t addr = (uint32_t)info->data_buf;
199 flush_dcache_range(addr, addr + info->data_buf_size);
202 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
204 uint32_t addr = (uint32_t)info->data_buf;
206 invalidate_dcache_range(addr, addr + info->data_buf_size);
209 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
211 uint32_t addr = (uint32_t)info->cmd_buf;
213 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
216 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
217 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
218 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
221 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
223 struct mxs_dma_desc *desc;
225 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
226 printf("MXS NAND: Too many DMA descriptors requested\n");
230 desc = info->desc[info->desc_index];
236 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
239 struct mxs_dma_desc *desc;
241 for (i = 0; i < info->desc_index; i++) {
242 desc = info->desc[i];
243 memset(desc, 0, sizeof(struct mxs_dma_desc));
244 desc->address = (dma_addr_t)desc;
247 info->desc_index = 0;
250 static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
252 struct nand_chip *nand = mtd->priv;
253 return mtd->writesize / nand->ecc.size;
256 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
258 return ecc_strength * 13;
261 static uint32_t mxs_nand_aux_status_offset(void)
263 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
266 static int mxs_nand_gpmi_init(void)
270 /* Reset the GPMI block. */
271 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
276 * Choose NAND mode, set IRQ polarity, disable write protection and
279 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
280 GPMI_CTRL1_GPMI_MODE,
281 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
282 GPMI_CTRL1_BCH_MODE);
283 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
287 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
288 uint32_t page_oob_size)
290 if (page_data_size == 2048)
293 if (page_data_size == 4096) {
294 if (page_oob_size == 128)
297 if (page_oob_size == 218)
304 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
305 uint32_t ecc_strength)
307 uint32_t chunk_data_size_in_bits;
308 uint32_t chunk_ecc_size_in_bits;
309 uint32_t chunk_total_size_in_bits;
310 uint32_t block_mark_chunk_number;
311 uint32_t block_mark_chunk_bit_offset;
312 uint32_t block_mark_bit_offset;
314 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
315 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
317 chunk_total_size_in_bits =
318 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
320 /* Compute the bit offset of the block mark within the physical page. */
321 block_mark_bit_offset = page_data_size * 8;
323 /* Subtract the metadata bits. */
324 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
327 * Compute the chunk number (starting at zero) in which the block mark
330 block_mark_chunk_number =
331 block_mark_bit_offset / chunk_total_size_in_bits;
334 * Compute the bit offset of the block mark within its chunk, and
337 block_mark_chunk_bit_offset = block_mark_bit_offset -
338 (block_mark_chunk_number * chunk_total_size_in_bits);
340 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
344 * Now that we know the chunk number in which the block mark appears,
345 * we can subtract all the ECC bits that appear before it.
347 block_mark_bit_offset -=
348 block_mark_chunk_number * chunk_ecc_size_in_bits;
350 return block_mark_bit_offset;
353 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
355 uint32_t ecc_strength;
356 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
357 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
360 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
362 uint32_t ecc_strength;
363 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
364 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
368 * Wait for BCH complete IRQ and clear the IRQ
370 static int mxs_nand_wait_for_bch_complete(void)
372 int timeout = MXS_NAND_BCH_TIMEOUT;
375 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
376 BCH_CTRL_COMPLETE_IRQ, timeout);
378 debug("%s@%d: %d\n", __func__, __LINE__, ret);
379 mxs_nand_gpmi_init();
382 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
388 * This is the function that we install in the cmd_ctrl function pointer of the
389 * owning struct nand_chip. The only functions in the reference implementation
390 * that use these functions pointers are cmdfunc and select_chip.
392 * In this driver, we implement our own select_chip, so this function will only
393 * be called by the reference implementation's cmdfunc. For this reason, we can
394 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
397 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
399 struct nand_chip *nand = mtd->priv;
400 struct mxs_nand_info *nand_info = nand->priv;
401 struct mxs_dma_desc *d;
402 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
406 * If this condition is true, something is _VERY_ wrong in MTD
409 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
410 printf("MXS NAND: Command queue too long\n");
415 * Every operation begins with a command byte and a series of zero or
416 * more address bytes. These are distinguished by either the Address
417 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
418 * asserted. When MTD is ready to execute the command, it will
419 * deasert both latch enables.
421 * Rather than run a separate DMA operation for every single byte, we
422 * queue them up and run a single DMA operation for the entire series
423 * of command and data bytes.
425 if (ctrl & (NAND_ALE | NAND_CLE)) {
426 if (data != NAND_CMD_NONE)
427 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
432 * If control arrives here, MTD has deasserted both the ALE and CLE,
433 * which means it's ready to run an operation. Check if we have any
436 if (nand_info->cmd_queue_len == 0)
439 /* Compile the DMA descriptor -- a descriptor that sends command. */
440 d = mxs_nand_get_dma_desc(nand_info);
442 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
443 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
444 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
445 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
447 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
449 d->cmd.pio_words[0] =
450 GPMI_CTRL0_COMMAND_MODE_WRITE |
451 GPMI_CTRL0_WORD_LENGTH |
452 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
453 GPMI_CTRL0_ADDRESS_NAND_CLE |
454 GPMI_CTRL0_ADDRESS_INCREMENT |
455 nand_info->cmd_queue_len;
457 mxs_dma_desc_append(channel, d);
460 mxs_nand_flush_cmd_buf(nand_info);
462 /* Execute the DMA chain. */
463 ret = mxs_dma_go(channel);
467 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
468 for (i = 0; i < nand_info->cmd_queue_len; i++) {
469 printf("%02x ", nand_info->cmd_buf[i]);
474 mxs_nand_return_dma_descs(nand_info);
476 /* Reset the command queue. */
477 nand_info->cmd_queue_len = 0;
481 * Test if the NAND flash is ready.
483 static int mxs_nand_device_ready(struct mtd_info *mtd)
485 struct nand_chip *chip = mtd->priv;
486 struct mxs_nand_info *nand_info = chip->priv;
489 tmp = readl(&gpmi_regs->hw_gpmi_stat);
490 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
496 * Select the NAND chip.
498 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
500 struct nand_chip *nand = mtd->priv;
501 struct mxs_nand_info *nand_info = nand->priv;
503 nand_info->cur_chip = chip;
507 * Handle block mark swapping.
509 * Note that, when this function is called, it doesn't know whether it's
510 * swapping the block mark, or swapping it *back* -- but it doesn't matter
511 * because the the operation is the same.
513 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
514 uint8_t *data_buf, uint8_t *oob_buf)
522 bit_offset = mxs_nand_mark_bit_offset(mtd);
523 buf_offset = mxs_nand_mark_byte_offset(mtd);
526 * Get the byte from the data area that overlays the block mark. Since
527 * the ECC engine applies its own view to the bits in the page, the
528 * physical block mark won't (in general) appear on a byte boundary in
531 src = data_buf[buf_offset] >> bit_offset;
532 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
536 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
537 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
541 data_buf[buf_offset] &= ~(0xff << bit_offset);
542 data_buf[buf_offset + 1] &= 0xff << bit_offset;
544 data_buf[buf_offset] |= dst << bit_offset;
545 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
549 * Read data from NAND.
551 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
553 struct nand_chip *nand = mtd->priv;
554 struct mxs_nand_info *nand_info = nand->priv;
555 struct mxs_dma_desc *d;
556 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
559 if (length > NAND_MAX_PAGESIZE) {
560 printf("MXS NAND: DMA buffer too big\n");
565 printf("MXS NAND: DMA buffer is NULL\n");
569 memset(buf, 0xee, length);
571 /* Compile the DMA descriptor - a descriptor that reads data. */
572 d = mxs_nand_get_dma_desc(nand_info);
574 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
575 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
576 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
577 (length << MXS_DMA_DESC_BYTES_OFFSET);
579 d->cmd.address = (dma_addr_t)nand_info->data_buf;
581 d->cmd.pio_words[0] =
582 GPMI_CTRL0_COMMAND_MODE_READ |
583 GPMI_CTRL0_WORD_LENGTH |
584 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
585 GPMI_CTRL0_ADDRESS_NAND_DATA |
588 mxs_dma_desc_append(channel, d);
591 * A DMA descriptor that waits for the command to end and the chip to
594 * I think we actually should *not* be waiting for the chip to become
595 * ready because, after all, we don't care. I think the original code
596 * did that and no one has re-thought it yet.
598 d = mxs_nand_get_dma_desc(nand_info);
600 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
601 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
602 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
606 d->cmd.pio_words[0] =
607 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
608 GPMI_CTRL0_WORD_LENGTH |
609 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
610 GPMI_CTRL0_ADDRESS_NAND_DATA;
612 mxs_dma_desc_append(channel, d);
614 /* Execute the DMA chain. */
615 ret = mxs_dma_go(channel);
617 printf("%s: DMA read error\n", __func__);
621 /* Invalidate caches */
622 mxs_nand_inval_data_buf(nand_info);
624 memcpy(buf, nand_info->data_buf, length);
627 mxs_nand_return_dma_descs(nand_info);
631 * Write data to NAND.
633 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
636 struct nand_chip *nand = mtd->priv;
637 struct mxs_nand_info *nand_info = nand->priv;
638 struct mxs_dma_desc *d;
639 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
642 if (length > NAND_MAX_PAGESIZE) {
643 printf("MXS NAND: DMA buffer too big\n");
648 printf("MXS NAND: DMA buffer is NULL\n");
652 memcpy(nand_info->data_buf, buf, length);
654 /* Compile the DMA descriptor - a descriptor that writes data. */
655 d = mxs_nand_get_dma_desc(nand_info);
657 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
658 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
659 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
660 (length << MXS_DMA_DESC_BYTES_OFFSET);
662 d->cmd.address = (dma_addr_t)nand_info->data_buf;
664 d->cmd.pio_words[0] =
665 GPMI_CTRL0_COMMAND_MODE_WRITE |
666 GPMI_CTRL0_WORD_LENGTH |
667 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
668 GPMI_CTRL0_ADDRESS_NAND_DATA |
671 mxs_dma_desc_append(channel, d);
674 mxs_nand_flush_data_buf(nand_info);
676 /* Execute the DMA chain. */
677 ret = mxs_dma_go(channel);
679 printf("%s: DMA write error\n", __func__);
681 mxs_nand_return_dma_descs(nand_info);
685 * Read a single byte from NAND.
687 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
690 mxs_nand_read_buf(mtd, &buf, 1);
694 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
696 flush_dcache_range((unsigned long)nand_info->data_buf,
697 (unsigned long)nand_info->data_buf +
699 flush_dcache_range((unsigned long)nand_info->oob_buf,
700 (unsigned long)nand_info->oob_buf +
705 * Read a page from NAND.
707 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
708 uint8_t *buf, int page)
710 struct mxs_nand_info *nand_info = nand->priv;
711 struct mxs_dma_desc *d;
712 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
713 uint32_t corrected = 0, failed = 0;
717 /* Compile the DMA descriptor - wait for ready. */
718 d = mxs_nand_get_dma_desc(nand_info);
720 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
721 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
722 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
726 d->cmd.pio_words[0] =
727 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
728 GPMI_CTRL0_WORD_LENGTH |
729 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
730 GPMI_CTRL0_ADDRESS_NAND_DATA;
732 mxs_dma_desc_append(channel, d);
734 /* Compile the DMA descriptor - enable the BCH block and read. */
735 d = mxs_nand_get_dma_desc(nand_info);
737 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
738 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
742 d->cmd.pio_words[0] =
743 GPMI_CTRL0_COMMAND_MODE_READ |
744 GPMI_CTRL0_WORD_LENGTH |
745 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
746 GPMI_CTRL0_ADDRESS_NAND_DATA |
747 (mtd->writesize + mtd->oobsize);
748 d->cmd.pio_words[1] = 0;
749 d->cmd.pio_words[2] =
750 GPMI_ECCCTRL_ENABLE_ECC |
751 GPMI_ECCCTRL_ECC_CMD_DECODE |
752 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
753 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
754 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
755 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
757 flush_buffers(mtd, nand_info);
759 mxs_dma_desc_append(channel, d);
761 /* Compile the DMA descriptor - disable the BCH block. */
762 d = mxs_nand_get_dma_desc(nand_info);
764 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
765 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
766 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
770 d->cmd.pio_words[0] =
771 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
772 GPMI_CTRL0_WORD_LENGTH |
773 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
774 GPMI_CTRL0_ADDRESS_NAND_DATA |
775 (mtd->writesize + mtd->oobsize);
776 d->cmd.pio_words[1] = 0;
777 d->cmd.pio_words[2] = 0;
779 mxs_dma_desc_append(channel, d);
781 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
782 d = mxs_nand_get_dma_desc(nand_info);
784 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
785 MXS_DMA_DESC_DEC_SEM;
789 mxs_dma_desc_append(channel, d);
791 /* Execute the DMA chain. */
792 ret = mxs_dma_go(channel);
794 printf("%s: DMA read error\n", __func__);
798 ret = mxs_nand_wait_for_bch_complete();
800 printf("MXS NAND: BCH read timeout\n");
804 /* Invalidate caches */
805 mxs_nand_inval_data_buf(nand_info);
807 /* Read DMA completed, now do the mark swapping. */
808 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
810 /* Loop over status bytes, accumulating ECC status. */
811 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
812 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
813 if (status[i] == 0x00)
816 if (status[i] == 0xff)
819 if (status[i] == 0xfe) {
824 corrected += status[i];
827 /* Propagate ECC status to the owning MTD. */
828 mtd->ecc_stats.failed += failed;
829 mtd->ecc_stats.corrected += corrected;
832 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
833 * details about our policy for delivering the OOB.
835 * We fill the caller's buffer with set bits, and then copy the block
836 * mark to the caller's buffer. Note that, if block mark swapping was
837 * necessary, it has already been done, so we can rely on the first
838 * byte of the auxiliary buffer to contain the block mark.
840 memset(nand->oob_poi, 0xff, mtd->oobsize);
842 nand->oob_poi[0] = nand_info->oob_buf[0];
844 memcpy(buf, nand_info->data_buf, mtd->writesize);
847 mxs_nand_return_dma_descs(nand_info);
853 * Write a page to NAND.
855 static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
856 struct nand_chip *nand, const uint8_t *buf)
858 struct mxs_nand_info *nand_info = nand->priv;
859 struct mxs_dma_desc *d;
860 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
863 memcpy(nand_info->data_buf, buf, mtd->writesize);
864 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
866 /* Handle block mark swapping. */
867 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
869 /* Compile the DMA descriptor - write data. */
870 d = mxs_nand_get_dma_desc(nand_info);
872 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
873 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
874 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
878 d->cmd.pio_words[0] =
879 GPMI_CTRL0_COMMAND_MODE_WRITE |
880 GPMI_CTRL0_WORD_LENGTH |
881 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
882 GPMI_CTRL0_ADDRESS_NAND_DATA;
883 d->cmd.pio_words[1] = 0;
884 d->cmd.pio_words[2] =
885 GPMI_ECCCTRL_ENABLE_ECC |
886 GPMI_ECCCTRL_ECC_CMD_ENCODE |
887 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
888 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
889 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
890 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
892 flush_buffers(mtd, nand_info);
894 mxs_dma_desc_append(channel, d);
897 mxs_nand_flush_data_buf(nand_info);
899 /* Execute the DMA chain. */
900 ret = mxs_dma_go(channel);
902 printf("%s: DMA write error\n", __func__);
906 ret = mxs_nand_wait_for_bch_complete();
908 printf("%s: BCH write timeout\n", __func__);
913 mxs_nand_return_dma_descs(nand_info);
917 * Read OOB from NAND.
919 * This function is a veneer that replaces the function originally installed by
920 * the NAND Flash MTD code.
922 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
923 struct mtd_oob_ops *ops)
925 struct nand_chip *chip = mtd->priv;
926 struct mxs_nand_info *nand_info = chip->priv;
929 if (ops->mode == MTD_OOB_RAW)
930 nand_info->raw_oob_mode = 1;
932 nand_info->raw_oob_mode = 0;
934 ret = nand_info->hooked_read_oob(mtd, from, ops);
936 nand_info->raw_oob_mode = 0;
944 * This function is a veneer that replaces the function originally installed by
945 * the NAND Flash MTD code.
947 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
948 struct mtd_oob_ops *ops)
950 struct nand_chip *chip = mtd->priv;
951 struct mxs_nand_info *nand_info = chip->priv;
954 if (ops->mode == MTD_OOB_RAW)
955 nand_info->raw_oob_mode = 1;
957 nand_info->raw_oob_mode = 0;
959 ret = nand_info->hooked_write_oob(mtd, to, ops);
961 nand_info->raw_oob_mode = 0;
967 * Mark a block bad in NAND.
969 * This function is a veneer that replaces the function originally installed by
970 * the NAND Flash MTD code.
972 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
974 struct nand_chip *chip = mtd->priv;
975 struct mxs_nand_info *nand_info = chip->priv;
978 nand_info->marking_block_bad = 1;
980 ret = nand_info->hooked_block_markbad(mtd, ofs);
982 nand_info->marking_block_bad = 0;
988 * There are several places in this driver where we have to handle the OOB and
989 * block marks. This is the function where things are the most complicated, so
990 * this is where we try to explain it all. All the other places refer back to
993 * These are the rules, in order of decreasing importance:
995 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
996 * write operations take measures to protect it.
998 * 2) In read operations, the first byte of the OOB we return must reflect the
999 * true state of the block mark, no matter where that block mark appears in
1000 * the physical page.
1002 * 3) ECC-based read operations return an OOB full of set bits (since we never
1003 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1006 * 4) "Raw" read operations return a direct view of the physical bytes in the
1007 * page, using the conventional definition of which bytes are data and which
1008 * are OOB. This gives the caller a way to see the actual, physical bytes
1009 * in the page, without the distortions applied by our ECC engine.
1011 * What we do for this specific read operation depends on whether we're doing
1012 * "raw" read, or an ECC-based read.
1014 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1015 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1016 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1017 * ECC-based or raw view of the page is implicit in which function it calls
1018 * (there is a similar pair of ECC-based/raw functions for writing).
1020 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1021 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1022 * caller wants an ECC-based or raw view of the page is not propagated down to
1025 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1026 * ecc.read_oob and ecc.write_oob function pointers in the owning
1027 * struct mtd_info with our own functions. These hook functions set the
1028 * raw_oob_mode field so that, when control finally arrives here, we'll know
1031 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1034 struct mxs_nand_info *nand_info = nand->priv;
1037 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1038 * get the bytes from the physical page. If we're not doing a raw read,
1039 * we need to fill the buffer with set bits.
1041 if (nand_info->raw_oob_mode) {
1043 * If control arrives here, we're doing a "raw" read. Send the
1044 * command to read the conventional OOB and read it.
1046 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1047 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1050 * If control arrives here, we're not doing a "raw" read. Fill
1051 * the OOB buffer with set bits and correct the block mark.
1053 memset(nand->oob_poi, 0xff, mtd->oobsize);
1055 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1056 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1064 * Write OOB data to NAND.
1066 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1069 struct mxs_nand_info *nand_info = nand->priv;
1070 uint8_t block_mark = 0;
1073 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1074 * the NAND Flash MTD model that make it essentially impossible to write
1075 * the out-of-band bytes.
1077 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1078 * mark a block bad, we can do that.
1081 if (!nand_info->marking_block_bad) {
1082 printf("NXS NAND: Writing OOB isn't supported\n");
1086 /* Write the block mark. */
1087 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1088 nand->write_buf(mtd, &block_mark, 1);
1089 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1091 /* Check if it worked. */
1092 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1099 * Claims all blocks are good.
1101 * In principle, this function is *only* called when the NAND Flash MTD system
1102 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1103 * the driver for bad block information.
1105 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1106 * this function is *only* called when we take it away.
1108 * Thus, this function is only called when we want *all* blocks to look good,
1109 * so it *always* return success.
1111 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1117 * Nominally, the purpose of this function is to look for or create the bad
1118 * block table. In fact, since the we call this function at the very end of
1119 * the initialization process started by nand_scan(), and we don't have a
1120 * more formal mechanism, we "hook" this function to continue init process.
1122 * At this point, the physical NAND Flash chips have been identified and
1123 * counted, so we know the physical geometry. This enables us to make some
1124 * important configuration decisions.
1126 * The return value of this function propogates directly back to this driver's
1127 * call to nand_scan(). Anything other than zero will cause this driver to
1128 * tear everything down and declare failure.
1130 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1132 struct nand_chip *nand = mtd->priv;
1133 struct mxs_nand_info *nand_info = nand->priv;
1136 /* Configure BCH and set NFC geometry */
1137 if (readl(&bch_regs->hw_bch_ctrl_reg) &
1138 (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
1139 /* When booting from NAND the BCH engine will already
1140 * be operational and obviously does not like being reset here.
1141 * There will be occasional read errors upon boot when this
1144 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1145 readl(&bch_regs->hw_bch_ctrl_reg);
1147 debug("mtd->writesize=%d\n", mtd->writesize);
1148 debug("mtd->oobsize=%d\n", mtd->oobsize);
1149 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1151 /* Configure layout 0 */
1152 tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
1153 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1154 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1155 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1156 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1157 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
1158 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1160 tmp = (mtd->writesize + mtd->oobsize)
1161 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1162 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1163 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1164 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
1165 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1167 /* Set *all* chip selects to use layout 0 */
1168 writel(0, &bch_regs->hw_bch_layoutselect);
1170 /* Enable BCH complete interrupt */
1171 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1173 /* Hook some operations at the MTD level. */
1174 if (mtd->read_oob != mxs_nand_hook_read_oob) {
1175 nand_info->hooked_read_oob = mtd->read_oob;
1176 mtd->read_oob = mxs_nand_hook_read_oob;
1179 if (mtd->write_oob != mxs_nand_hook_write_oob) {
1180 nand_info->hooked_write_oob = mtd->write_oob;
1181 mtd->write_oob = mxs_nand_hook_write_oob;
1184 if (mtd->block_markbad != mxs_nand_hook_block_markbad) {
1185 nand_info->hooked_block_markbad = mtd->block_markbad;
1186 mtd->block_markbad = mxs_nand_hook_block_markbad;
1189 /* We use the reference implementation for bad block management. */
1190 return nand_default_bbt(mtd);
1194 * Allocate DMA buffers
1196 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1199 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1201 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1204 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1206 printf("%s: Error allocating DMA buffers\n", __func__);
1210 memset(buf, 0, nand_info->data_buf_size);
1212 nand_info->data_buf = buf;
1213 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1214 /* Command buffers */
1215 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1216 MXS_NAND_COMMAND_BUFFER_SIZE);
1217 if (!nand_info->cmd_buf) {
1219 printf("MXS NAND: Error allocating command buffers\n");
1222 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1223 nand_info->cmd_queue_len = 0;
1229 * Initializes the NFC hardware.
1231 int mxs_nand_init(struct mxs_nand_info *info)
1236 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1237 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1239 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1246 /* Allocate the DMA descriptors. */
1247 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1248 info->desc[i] = mxs_dma_desc_alloc();
1249 if (!info->desc[i]) {
1250 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1256 /* Init the DMA controller. */
1257 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1258 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1260 ret = mxs_dma_init_channel(chan);
1262 printf("Failed to initialize DMA channel %d\n", chan);
1267 ret = mxs_nand_gpmi_init();
1274 for (--i; i >= 0; i--)
1275 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1276 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1279 for (--i; i >= 0; i--)
1280 mxs_dma_desc_free(info->desc[i]);
1286 * This function is called during the driver binding process.
1288 * @param pdev the device structure used to store device specific
1289 * information that is used by the suspend, resume and
1292 * @return The function always returns 0.
1294 int board_nand_init(struct nand_chip *nand)
1296 struct mxs_nand_info *nand_info;
1299 nand_info = malloc(sizeof(struct mxs_nand_info));
1301 printf("MXS NAND: Failed to allocate private data\n");
1304 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1306 err = mxs_nand_alloc_buffers(nand_info);
1310 err = mxs_nand_init(nand_info);
1314 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1316 nand->priv = nand_info;
1317 nand->options |= NAND_NO_SUBPAGE_WRITE;
1318 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1319 nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
1321 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1323 nand->dev_ready = mxs_nand_device_ready;
1324 nand->select_chip = mxs_nand_select_chip;
1325 nand->block_bad = mxs_nand_block_bad;
1326 nand->scan_bbt = mxs_nand_scan_bbt;
1328 nand->read_byte = mxs_nand_read_byte;
1330 nand->read_buf = mxs_nand_read_buf;
1331 nand->write_buf = mxs_nand_write_buf;
1333 nand->ecc.read_page = mxs_nand_ecc_read_page;
1334 nand->ecc.write_page = mxs_nand_ecc_write_page;
1335 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1336 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1338 nand->ecc.layout = &fake_ecc_layout;
1339 nand->ecc.mode = NAND_ECC_HW;
1340 nand->ecc.bytes = 9;
1341 nand->ecc.size = 512;
1346 free(nand_info->data_buf);
1347 free(nand_info->cmd_buf);