drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12  * SPDX-License-Identifier:     GPL-2.0+
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include "e1000.h"
  33
  34 #define TOUT_LOOP   100000
  35
  36 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  37 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  38
  39 #define E1000_DEFAULT_PCI_PBA   0x00000030
  40 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  41
  42 /* NIC specific static variables go here */
  43
  44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  45 #define E1000_BUFFER_ALIGN      128
  46
  47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  50
  51 static int tx_tail;
  52 static int rx_tail, rx_last;
  53
  54 static struct pci_device_id e1000_supported[] = {
  55         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  56         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  57         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  58         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  59         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  60         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  61         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  62         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  63         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  64         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  65         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  66         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  67         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  68         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  69         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  72         /* E1000 PCIe card */
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
  87         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
 103
 104         {}
 105 };
 106
 107 /* Function forward declarations */
 108 static int e1000_setup_link(struct eth_device *nic);
 109 static int e1000_setup_fiber_link(struct eth_device *nic);
 110 static int e1000_setup_copper_link(struct eth_device *nic);
 111 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 112 static void e1000_config_collision_dist(struct e1000_hw *hw);
 113 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 114 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 115 static int e1000_check_for_link(struct eth_device *nic);
 116 static int e1000_wait_autoneg(struct e1000_hw *hw);
 117 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 118                                        uint16_t * duplex);
 119 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 120                               uint16_t * phy_data);
 121 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 122                                uint16_t phy_data);
 123 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 124 static int e1000_phy_reset(struct e1000_hw *hw);
 125 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 126 static void e1000_set_media_type(struct e1000_hw *hw);
 127
 128 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 129 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 130 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 131
 132 #ifndef CONFIG_E1000_NO_NVM
 133 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 134 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 135                 uint16_t words,
 136                 uint16_t *data);
 137 /******************************************************************************
 138  * Raises the EEPROM's clock input.
 139  *
 140  * hw - Struct containing variables accessed by shared code
 141  * eecd - EECD's current value
 142  *****************************************************************************/
 143 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 144 {
 145         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 146          * wait 50 microseconds.
 147          */
 148         *eecd = *eecd | E1000_EECD_SK;
 149         E1000_WRITE_REG(hw, EECD, *eecd);
 150         E1000_WRITE_FLUSH(hw);
 151         udelay(50);
 152 }
 153
 154 /******************************************************************************
 155  * Lowers the EEPROM's clock input.
 156  *
 157  * hw - Struct containing variables accessed by shared code
 158  * eecd - EECD's current value
 159  *****************************************************************************/
 160 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 161 {
 162         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 163          * wait 50 microseconds.
 164          */
 165         *eecd = *eecd & ~E1000_EECD_SK;
 166         E1000_WRITE_REG(hw, EECD, *eecd);
 167         E1000_WRITE_FLUSH(hw);
 168         udelay(50);
 169 }
 170
 171 /******************************************************************************
 172  * Shift data bits out to the EEPROM.
 173  *
 174  * hw - Struct containing variables accessed by shared code
 175  * data - data to send to the EEPROM
 176  * count - number of bits to shift out
 177  *****************************************************************************/
 178 static void
 179 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 180 {
 181         uint32_t eecd;
 182         uint32_t mask;
 183
 184         /* We need to shift "count" bits out to the EEPROM. So, value in the
 185          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 186          * In order to do this, "data" must be broken down into bits.
 187          */
 188         mask = 0x01 << (count - 1);
 189         eecd = E1000_READ_REG(hw, EECD);
 190         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 191         do {
 192                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 193                  * and then raising and then lowering the clock (the SK bit controls
 194                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 195                  * by setting "DI" to "0" and then raising and then lowering the clock.
 196                  */
 197                 eecd &= ~E1000_EECD_DI;
 198
 199                 if (data & mask)
 200                         eecd |= E1000_EECD_DI;
 201
 202                 E1000_WRITE_REG(hw, EECD, eecd);
 203                 E1000_WRITE_FLUSH(hw);
 204
 205                 udelay(50);
 206
 207                 e1000_raise_ee_clk(hw, &eecd);
 208                 e1000_lower_ee_clk(hw, &eecd);
 209
 210                 mask = mask >> 1;
 211
 212         } while (mask);
 213
 214         /* We leave the "DI" bit set to "0" when we leave this routine. */
 215         eecd &= ~E1000_EECD_DI;
 216         E1000_WRITE_REG(hw, EECD, eecd);
 217 }
 218
 219 /******************************************************************************
 220  * Shift data bits in from the EEPROM
 221  *
 222  * hw - Struct containing variables accessed by shared code
 223  *****************************************************************************/
 224 static uint16_t
 225 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 226 {
 227         uint32_t eecd;
 228         uint32_t i;
 229         uint16_t data;
 230
 231         /* In order to read a register from the EEPROM, we need to shift 'count'
 232          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 233          * input to the EEPROM (setting the SK bit), and then reading the
 234          * value of the "DO" bit.  During this "shifting in" process the
 235          * "DI" bit should always be clear.
 236          */
 237
 238         eecd = E1000_READ_REG(hw, EECD);
 239
 240         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 241         data = 0;
 242
 243         for (i = 0; i < count; i++) {
 244                 data = data << 1;
 245                 e1000_raise_ee_clk(hw, &eecd);
 246
 247                 eecd = E1000_READ_REG(hw, EECD);
 248
 249                 eecd &= ~(E1000_EECD_DI);
 250                 if (eecd & E1000_EECD_DO)
 251                         data |= 1;
 252
 253                 e1000_lower_ee_clk(hw, &eecd);
 254         }
 255
 256         return data;
 257 }
 258
 259 /******************************************************************************
 260  * Returns EEPROM to a "standby" state
 261  *
 262  * hw - Struct containing variables accessed by shared code
 263  *****************************************************************************/
 264 void e1000_standby_eeprom(struct e1000_hw *hw)
 265 {
 266         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 267         uint32_t eecd;
 268
 269         eecd = E1000_READ_REG(hw, EECD);
 270
 271         if (eeprom->type == e1000_eeprom_microwire) {
 272                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 273                 E1000_WRITE_REG(hw, EECD, eecd);
 274                 E1000_WRITE_FLUSH(hw);
 275                 udelay(eeprom->delay_usec);
 276
 277                 /* Clock high */
 278                 eecd |= E1000_EECD_SK;
 279                 E1000_WRITE_REG(hw, EECD, eecd);
 280                 E1000_WRITE_FLUSH(hw);
 281                 udelay(eeprom->delay_usec);
 282
 283                 /* Select EEPROM */
 284                 eecd |= E1000_EECD_CS;
 285                 E1000_WRITE_REG(hw, EECD, eecd);
 286                 E1000_WRITE_FLUSH(hw);
 287                 udelay(eeprom->delay_usec);
 288
 289                 /* Clock low */
 290                 eecd &= ~E1000_EECD_SK;
 291                 E1000_WRITE_REG(hw, EECD, eecd);
 292                 E1000_WRITE_FLUSH(hw);
 293                 udelay(eeprom->delay_usec);
 294         } else if (eeprom->type == e1000_eeprom_spi) {
 295                 /* Toggle CS to flush commands */
 296                 eecd |= E1000_EECD_CS;
 297                 E1000_WRITE_REG(hw, EECD, eecd);
 298                 E1000_WRITE_FLUSH(hw);
 299                 udelay(eeprom->delay_usec);
 300                 eecd &= ~E1000_EECD_CS;
 301                 E1000_WRITE_REG(hw, EECD, eecd);
 302                 E1000_WRITE_FLUSH(hw);
 303                 udelay(eeprom->delay_usec);
 304         }
 305 }
 306
 307 /***************************************************************************
 308 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 309 *
 310 * hw - Struct containing variables accessed by shared code
 311 ****************************************************************************/
 312 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 313 {
 314         uint32_t eecd = 0;
 315
 316         DEBUGFUNC();
 317
 318         if (hw->mac_type == e1000_ich8lan)
 319                 return false;
 320
 321         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 322                 eecd = E1000_READ_REG(hw, EECD);
 323
 324                 /* Isolate bits 15 & 16 */
 325                 eecd = ((eecd >> 15) & 0x03);
 326
 327                 /* If both bits are set, device is Flash type */
 328                 if (eecd == 0x03)
 329                         return false;
 330         }
 331         return true;
 332 }
 333
 334 /******************************************************************************
 335  * Prepares EEPROM for access
 336  *
 337  * hw - Struct containing variables accessed by shared code
 338  *
 339  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 340  * function should be called before issuing a command to the EEPROM.
 341  *****************************************************************************/
 342 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 343 {
 344         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 345         uint32_t eecd, i = 0;
 346
 347         DEBUGFUNC();
 348
 349         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 350                 return -E1000_ERR_SWFW_SYNC;
 351         eecd = E1000_READ_REG(hw, EECD);
 352
 353         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 354                 /* Request EEPROM Access */
 355                 if (hw->mac_type > e1000_82544) {
 356                         eecd |= E1000_EECD_REQ;
 357                         E1000_WRITE_REG(hw, EECD, eecd);
 358                         eecd = E1000_READ_REG(hw, EECD);
 359                         while ((!(eecd & E1000_EECD_GNT)) &&
 360                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 361                                 i++;
 362                                 udelay(5);
 363                                 eecd = E1000_READ_REG(hw, EECD);
 364                         }
 365                         if (!(eecd & E1000_EECD_GNT)) {
 366                                 eecd &= ~E1000_EECD_REQ;
 367                                 E1000_WRITE_REG(hw, EECD, eecd);
 368                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 369                                 return -E1000_ERR_EEPROM;
 370                         }
 371                 }
 372         }
 373
 374         /* Setup EEPROM for Read/Write */
 375
 376         if (eeprom->type == e1000_eeprom_microwire) {
 377                 /* Clear SK and DI */
 378                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 379                 E1000_WRITE_REG(hw, EECD, eecd);
 380
 381                 /* Set CS */
 382                 eecd |= E1000_EECD_CS;
 383                 E1000_WRITE_REG(hw, EECD, eecd);
 384         } else if (eeprom->type == e1000_eeprom_spi) {
 385                 /* Clear SK and CS */
 386                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 387                 E1000_WRITE_REG(hw, EECD, eecd);
 388                 udelay(1);
 389         }
 390
 391         return E1000_SUCCESS;
 392 }
 393
 394 /******************************************************************************
 395  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 396  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 397  * registers must be mapped, or this will crash.
 398  *
 399  * hw - Struct containing variables accessed by shared code
 400  *****************************************************************************/
 401 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 402 {
 403         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 404         uint32_t eecd;
 405         int32_t ret_val = E1000_SUCCESS;
 406         uint16_t eeprom_size;
 407
 408         if (hw->mac_type == e1000_igb)
 409                 eecd = E1000_READ_REG(hw, I210_EECD);
 410         else
 411                 eecd = E1000_READ_REG(hw, EECD);
 412
 413         DEBUGFUNC();
 414
 415         switch (hw->mac_type) {
 416         case e1000_82542_rev2_0:
 417         case e1000_82542_rev2_1:
 418         case e1000_82543:
 419         case e1000_82544:
 420                 eeprom->type = e1000_eeprom_microwire;
 421                 eeprom->word_size = 64;
 422                 eeprom->opcode_bits = 3;
 423                 eeprom->address_bits = 6;
 424                 eeprom->delay_usec = 50;
 425                 eeprom->use_eerd = false;
 426                 eeprom->use_eewr = false;
 427         break;
 428         case e1000_82540:
 429         case e1000_82545:
 430         case e1000_82545_rev_3:
 431         case e1000_82546:
 432         case e1000_82546_rev_3:
 433                 eeprom->type = e1000_eeprom_microwire;
 434                 eeprom->opcode_bits = 3;
 435                 eeprom->delay_usec = 50;
 436                 if (eecd & E1000_EECD_SIZE) {
 437                         eeprom->word_size = 256;
 438                         eeprom->address_bits = 8;
 439                 } else {
 440                         eeprom->word_size = 64;
 441                         eeprom->address_bits = 6;
 442                 }
 443                 eeprom->use_eerd = false;
 444                 eeprom->use_eewr = false;
 445                 break;
 446         case e1000_82541:
 447         case e1000_82541_rev_2:
 448         case e1000_82547:
 449         case e1000_82547_rev_2:
 450                 if (eecd & E1000_EECD_TYPE) {
 451                         eeprom->type = e1000_eeprom_spi;
 452                         eeprom->opcode_bits = 8;
 453                         eeprom->delay_usec = 1;
 454                         if (eecd & E1000_EECD_ADDR_BITS) {
 455                                 eeprom->page_size = 32;
 456                                 eeprom->address_bits = 16;
 457                         } else {
 458                                 eeprom->page_size = 8;
 459                                 eeprom->address_bits = 8;
 460                         }
 461                 } else {
 462                         eeprom->type = e1000_eeprom_microwire;
 463                         eeprom->opcode_bits = 3;
 464                         eeprom->delay_usec = 50;
 465                         if (eecd & E1000_EECD_ADDR_BITS) {
 466                                 eeprom->word_size = 256;
 467                                 eeprom->address_bits = 8;
 468                         } else {
 469                                 eeprom->word_size = 64;
 470                                 eeprom->address_bits = 6;
 471                         }
 472                 }
 473                 eeprom->use_eerd = false;
 474                 eeprom->use_eewr = false;
 475                 break;
 476         case e1000_82571:
 477         case e1000_82572:
 478                 eeprom->type = e1000_eeprom_spi;
 479                 eeprom->opcode_bits = 8;
 480                 eeprom->delay_usec = 1;
 481                 if (eecd & E1000_EECD_ADDR_BITS) {
 482                         eeprom->page_size = 32;
 483                         eeprom->address_bits = 16;
 484                 } else {
 485                         eeprom->page_size = 8;
 486                         eeprom->address_bits = 8;
 487                 }
 488                 eeprom->use_eerd = false;
 489                 eeprom->use_eewr = false;
 490                 break;
 491         case e1000_82573:
 492         case e1000_82574:
 493                 eeprom->type = e1000_eeprom_spi;
 494                 eeprom->opcode_bits = 8;
 495                 eeprom->delay_usec = 1;
 496                 if (eecd & E1000_EECD_ADDR_BITS) {
 497                         eeprom->page_size = 32;
 498                         eeprom->address_bits = 16;
 499                 } else {
 500                         eeprom->page_size = 8;
 501                         eeprom->address_bits = 8;
 502                 }
 503                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 504                         eeprom->use_eerd = true;
 505                         eeprom->use_eewr = true;
 506
 507                         eeprom->type = e1000_eeprom_flash;
 508                         eeprom->word_size = 2048;
 509
 510                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 511                  * Flash update issue on parts which use a FLASH for NVM. */
 512                         eecd &= ~E1000_EECD_AUPDEN;
 513                         E1000_WRITE_REG(hw, EECD, eecd);
 514                 }
 515                 break;
 516         case e1000_80003es2lan:
 517                 eeprom->type = e1000_eeprom_spi;
 518                 eeprom->opcode_bits = 8;
 519                 eeprom->delay_usec = 1;
 520                 if (eecd & E1000_EECD_ADDR_BITS) {
 521                         eeprom->page_size = 32;
 522                         eeprom->address_bits = 16;
 523                 } else {
 524                         eeprom->page_size = 8;
 525                         eeprom->address_bits = 8;
 526                 }
 527                 eeprom->use_eerd = true;
 528                 eeprom->use_eewr = false;
 529                 break;
 530         case e1000_igb:
 531                 /* i210 has 4k of iNVM mapped as EEPROM */
 532                 eeprom->type = e1000_eeprom_invm;
 533                 eeprom->opcode_bits = 8;
 534                 eeprom->delay_usec = 1;
 535                 eeprom->page_size = 32;
 536                 eeprom->address_bits = 16;
 537                 eeprom->use_eerd = true;
 538                 eeprom->use_eewr = false;
 539                 break;
 540
 541         /* ich8lan does not support currently. if needed, please
 542          * add corresponding code and functions.
 543          */
 544 #if 0
 545         case e1000_ich8lan:
 546                 {
 547                 int32_t  i = 0;
 548
 549                 eeprom->type = e1000_eeprom_ich8;
 550                 eeprom->use_eerd = false;
 551                 eeprom->use_eewr = false;
 552                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 553                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 554                                 ICH_FLASH_GFPREG);
 555                 /* Zero the shadow RAM structure. But don't load it from NVM
 556                  * so as to save time for driver init */
 557                 if (hw->eeprom_shadow_ram != NULL) {
 558                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 559                                 hw->eeprom_shadow_ram[i].modified = false;
 560                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 561                         }
 562                 }
 563
 564                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 565                                 ICH_FLASH_SECTOR_SIZE;
 566
 567                 hw->flash_bank_size = ((flash_size >> 16)
 568                                 & ICH_GFPREG_BASE_MASK) + 1;
 569                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 570
 571                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 572
 573                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 574                 break;
 575                 }
 576 #endif
 577         default:
 578                 break;
 579         }
 580
 581         if (eeprom->type == e1000_eeprom_spi ||
 582             eeprom->type == e1000_eeprom_invm) {
 583                 /* eeprom_size will be an enum [0..8] that maps
 584                  * to eeprom sizes 128B to
 585                  * 32KB (incremented by powers of 2).
 586                  */
 587                 if (hw->mac_type <= e1000_82547_rev_2) {
 588                         /* Set to default value for initial eeprom read. */
 589                         eeprom->word_size = 64;
 590                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 591                                         &eeprom_size);
 592                         if (ret_val)
 593                                 return ret_val;
 594                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 595                                 >> EEPROM_SIZE_SHIFT;
 596                         /* 256B eeprom size was not supported in earlier
 597                          * hardware, so we bump eeprom_size up one to
 598                          * ensure that "1" (which maps to 256B) is never
 599                          * the result used in the shifting logic below. */
 600                         if (eeprom_size)
 601                                 eeprom_size++;
 602                 } else {
 603                         eeprom_size = (uint16_t)((eecd &
 604                                 E1000_EECD_SIZE_EX_MASK) >>
 605                                 E1000_EECD_SIZE_EX_SHIFT);
 606                 }
 607
 608                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 609         }
 610         return ret_val;
 611 }
 612
 613 /******************************************************************************
 614  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 615  *
 616  * hw - Struct containing variables accessed by shared code
 617  *****************************************************************************/
 618 static int32_t
 619 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 620 {
 621         uint32_t attempts = 100000;
 622         uint32_t i, reg = 0;
 623         int32_t done = E1000_ERR_EEPROM;
 624
 625         for (i = 0; i < attempts; i++) {
 626                 if (eerd == E1000_EEPROM_POLL_READ) {
 627                         if (hw->mac_type == e1000_igb)
 628                                 reg = E1000_READ_REG(hw, I210_EERD);
 629                         else
 630                                 reg = E1000_READ_REG(hw, EERD);
 631                 } else {
 632                         if (hw->mac_type == e1000_igb)
 633                                 reg = E1000_READ_REG(hw, I210_EEWR);
 634                         else
 635                                 reg = E1000_READ_REG(hw, EEWR);
 636                 }
 637
 638                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 639                         done = E1000_SUCCESS;
 640                         break;
 641                 }
 642                 udelay(5);
 643         }
 644
 645         return done;
 646 }
 647
 648 /******************************************************************************
 649  * Reads a 16 bit word from the EEPROM using the EERD register.
 650  *
 651  * hw - Struct containing variables accessed by shared code
 652  * offset - offset of  word in the EEPROM to read
 653  * data - word read from the EEPROM
 654  * words - number of words to read
 655  *****************************************************************************/
 656 static int32_t
 657 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 658                         uint16_t offset,
 659                         uint16_t words,
 660                         uint16_t *data)
 661 {
 662         uint32_t i, eerd = 0;
 663         int32_t error = 0;
 664
 665         for (i = 0; i < words; i++) {
 666                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 667                         E1000_EEPROM_RW_REG_START;
 668
 669                 if (hw->mac_type == e1000_igb)
 670                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 671                 else
 672                         E1000_WRITE_REG(hw, EERD, eerd);
 673
 674                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 675
 676                 if (error)
 677                         break;
 678
 679                 if (hw->mac_type == e1000_igb) {
 680                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 681                                 E1000_EEPROM_RW_REG_DATA);
 682                 } else {
 683                         data[i] = (E1000_READ_REG(hw, EERD) >>
 684                                 E1000_EEPROM_RW_REG_DATA);
 685                 }
 686
 687         }
 688
 689         return error;
 690 }
 691
 692 void e1000_release_eeprom(struct e1000_hw *hw)
 693 {
 694         uint32_t eecd;
 695
 696         DEBUGFUNC();
 697
 698         eecd = E1000_READ_REG(hw, EECD);
 699
 700         if (hw->eeprom.type == e1000_eeprom_spi) {
 701                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 702                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 703
 704                 E1000_WRITE_REG(hw, EECD, eecd);
 705
 706                 udelay(hw->eeprom.delay_usec);
 707         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 708                 /* cleanup eeprom */
 709
 710                 /* CS on Microwire is active-high */
 711                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 712
 713                 E1000_WRITE_REG(hw, EECD, eecd);
 714
 715                 /* Rising edge of clock */
 716                 eecd |= E1000_EECD_SK;
 717                 E1000_WRITE_REG(hw, EECD, eecd);
 718                 E1000_WRITE_FLUSH(hw);
 719                 udelay(hw->eeprom.delay_usec);
 720
 721                 /* Falling edge of clock */
 722                 eecd &= ~E1000_EECD_SK;
 723                 E1000_WRITE_REG(hw, EECD, eecd);
 724                 E1000_WRITE_FLUSH(hw);
 725                 udelay(hw->eeprom.delay_usec);
 726         }
 727
 728         /* Stop requesting EEPROM access */
 729         if (hw->mac_type > e1000_82544) {
 730                 eecd &= ~E1000_EECD_REQ;
 731                 E1000_WRITE_REG(hw, EECD, eecd);
 732         }
 733
 734         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 735 }
 736
 737 /******************************************************************************
 738  * Reads a 16 bit word from the EEPROM.
 739  *
 740  * hw - Struct containing variables accessed by shared code
 741  *****************************************************************************/
 742 static int32_t
 743 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 744 {
 745         uint16_t retry_count = 0;
 746         uint8_t spi_stat_reg;
 747
 748         DEBUGFUNC();
 749
 750         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 751          * EEPROM will signal that the command has been completed by clearing
 752          * bit 0 of the internal status register.  If it's not cleared within
 753          * 5 milliseconds, then error out.
 754          */
 755         retry_count = 0;
 756         do {
 757                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 758                         hw->eeprom.opcode_bits);
 759                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 760                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 761                         break;
 762
 763                 udelay(5);
 764                 retry_count += 5;
 765
 766                 e1000_standby_eeprom(hw);
 767         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 768
 769         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 770          * only 0-5mSec on 5V devices)
 771          */
 772         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 773                 DEBUGOUT("SPI EEPROM Status error\n");
 774                 return -E1000_ERR_EEPROM;
 775         }
 776
 777         return E1000_SUCCESS;
 778 }
 779
 780 /******************************************************************************
 781  * Reads a 16 bit word from the EEPROM.
 782  *
 783  * hw - Struct containing variables accessed by shared code
 784  * offset - offset of  word in the EEPROM to read
 785  * data - word read from the EEPROM
 786  *****************************************************************************/
 787 static int32_t
 788 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 789                 uint16_t words, uint16_t *data)
 790 {
 791         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 792         uint32_t i = 0;
 793
 794         DEBUGFUNC();
 795
 796         /* If eeprom is not yet detected, do so now */
 797         if (eeprom->word_size == 0)
 798                 e1000_init_eeprom_params(hw);
 799
 800         /* A check for invalid values:  offset too large, too many words,
 801          * and not enough words.
 802          */
 803         if ((offset >= eeprom->word_size) ||
 804                 (words > eeprom->word_size - offset) ||
 805                 (words == 0)) {
 806                 DEBUGOUT("\"words\" parameter out of bounds."
 807                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 808                 return -E1000_ERR_EEPROM;
 809         }
 810
 811         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 812          * directly. In this case, we need to acquire the EEPROM so that
 813          * FW or other port software does not interrupt.
 814          */
 815         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 816                 hw->eeprom.use_eerd == false) {
 817
 818                 /* Prepare the EEPROM for bit-bang reading */
 819                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 820                         return -E1000_ERR_EEPROM;
 821         }
 822
 823         /* Eerd register EEPROM access requires no eeprom aquire/release */
 824         if (eeprom->use_eerd == true)
 825                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 826
 827         /* ich8lan does not support currently. if needed, please
 828          * add corresponding code and functions.
 829          */
 830 #if 0
 831         /* ICH EEPROM access is done via the ICH flash controller */
 832         if (eeprom->type == e1000_eeprom_ich8)
 833                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 834 #endif
 835         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 836          * acquired the EEPROM at this point, so any returns should relase it */
 837         if (eeprom->type == e1000_eeprom_spi) {
 838                 uint16_t word_in;
 839                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 840
 841                 if (e1000_spi_eeprom_ready(hw)) {
 842                         e1000_release_eeprom(hw);
 843                         return -E1000_ERR_EEPROM;
 844                 }
 845
 846                 e1000_standby_eeprom(hw);
 847
 848                 /* Some SPI eeproms use the 8th address bit embedded in
 849                  * the opcode */
 850                 if ((eeprom->address_bits == 8) && (offset >= 128))
 851                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 852
 853                 /* Send the READ command (opcode + addr)  */
 854                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 855                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 856                                 eeprom->address_bits);
 857
 858                 /* Read the data.  The address of the eeprom internally
 859                  * increments with each byte (spi) being read, saving on the
 860                  * overhead of eeprom setup and tear-down.  The address
 861                  * counter will roll over if reading beyond the size of
 862                  * the eeprom, thus allowing the entire memory to be read
 863                  * starting from any offset. */
 864                 for (i = 0; i < words; i++) {
 865                         word_in = e1000_shift_in_ee_bits(hw, 16);
 866                         data[i] = (word_in >> 8) | (word_in << 8);
 867                 }
 868         } else if (eeprom->type == e1000_eeprom_microwire) {
 869                 for (i = 0; i < words; i++) {
 870                         /* Send the READ command (opcode + addr)  */
 871                         e1000_shift_out_ee_bits(hw,
 872                                 EEPROM_READ_OPCODE_MICROWIRE,
 873                                 eeprom->opcode_bits);
 874                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 875                                 eeprom->address_bits);
 876
 877                         /* Read the data.  For microwire, each word requires
 878                          * the overhead of eeprom setup and tear-down. */
 879                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 880                         e1000_standby_eeprom(hw);
 881                 }
 882         }
 883
 884         /* End this read operation */
 885         e1000_release_eeprom(hw);
 886
 887         return E1000_SUCCESS;
 888 }
 889
 890 /******************************************************************************
 891  * Verifies that the EEPROM has a valid checksum
 892  *
 893  * hw - Struct containing variables accessed by shared code
 894  *
 895  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 896  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 897  * valid.
 898  *****************************************************************************/
 899 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 900 {
 901         uint16_t i, checksum, checksum_reg, *buf;
 902
 903         DEBUGFUNC();
 904
 905         /* Allocate a temporary buffer */
 906         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 907         if (!buf) {
 908                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 909                 return -E1000_ERR_EEPROM;
 910         }
 911
 912         /* Read the EEPROM */
 913         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 914                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 915                 return -E1000_ERR_EEPROM;
 916         }
 917
 918         /* Compute the checksum */
 919         checksum = 0;
 920         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 921                 checksum += buf[i];
 922         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 923         checksum_reg = buf[i];
 924
 925         /* Verify it! */
 926         if (checksum == checksum_reg)
 927                 return 0;
 928
 929         /* Hrm, verification failed, print an error */
 930         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 931         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 932                         checksum_reg, checksum);
 933
 934         return -E1000_ERR_EEPROM;
 935 }
 936 #endif /* CONFIG_E1000_NO_NVM */
 937
 938 /*****************************************************************************
 939  * Set PHY to class A mode
 940  * Assumes the following operations will follow to enable the new class mode.
 941  *  1. Do a PHY soft reset
 942  *  2. Restart auto-negotiation or force link.
 943  *
 944  * hw - Struct containing variables accessed by shared code
 945  ****************************************************************************/
 946 static int32_t
 947 e1000_set_phy_mode(struct e1000_hw *hw)
 948 {
 949 #ifndef CONFIG_E1000_NO_NVM
 950         int32_t ret_val;
 951         uint16_t eeprom_data;
 952
 953         DEBUGFUNC();
 954
 955         if ((hw->mac_type == e1000_82545_rev_3) &&
 956                 (hw->media_type == e1000_media_type_copper)) {
 957                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 958                                 1, &eeprom_data);
 959                 if (ret_val)
 960                         return ret_val;
 961
 962                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 963                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 964                         ret_val = e1000_write_phy_reg(hw,
 965                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 966                         if (ret_val)
 967                                 return ret_val;
 968                         ret_val = e1000_write_phy_reg(hw,
 969                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 970                         if (ret_val)
 971                                 return ret_val;
 972
 973                         hw->phy_reset_disable = false;
 974                 }
 975         }
 976 #endif
 977         return E1000_SUCCESS;
 978 }
 979
 980 #ifndef CONFIG_E1000_NO_NVM
 981 /***************************************************************************
 982  *
 983  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 984  *
 985  * hw: Struct containing variables accessed by shared code
 986  *
 987  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 988  *            E1000_SUCCESS at any other case.
 989  *
 990  ***************************************************************************/
 991 static int32_t
 992 e1000_get_software_semaphore(struct e1000_hw *hw)
 993 {
 994          int32_t timeout = hw->eeprom.word_size + 1;
 995          uint32_t swsm;
 996
 997         DEBUGFUNC();
 998
 999                 swsm = E1000_READ_REG(hw, SWSM);
1000                 swsm &= ~E1000_SWSM_SMBI;
1001                 E1000_WRITE_REG(hw, SWSM, swsm);
1002
1003         if (hw->mac_type != e1000_80003es2lan)
1004                 return E1000_SUCCESS;
1005
1006         while (timeout) {
1007                 swsm = E1000_READ_REG(hw, SWSM);
1008                 /* If SMBI bit cleared, it is now set and we hold
1009                  * the semaphore */
1010                 if (!(swsm & E1000_SWSM_SMBI))
1011                         break;
1012                 mdelay(1);
1013                 timeout--;
1014         }
1015
1016         if (!timeout) {
1017                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1018                 return -E1000_ERR_RESET;
1019         }
1020
1021         return E1000_SUCCESS;
1022 }
1023 #endif
1024
1025 /***************************************************************************
1026  * This function clears HW semaphore bits.
1027  *
1028  * hw: Struct containing variables accessed by shared code
1029  *
1030  * returns: - None.
1031  *
1032  ***************************************************************************/
1033 static void
1034 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1035 {
1036 #ifndef CONFIG_E1000_NO_NVM
1037          uint32_t swsm;
1038
1039         DEBUGFUNC();
1040
1041         if (!hw->eeprom_semaphore_present)
1042                 return;
1043
1044         swsm = E1000_READ_REG(hw, SWSM);
1045         if (hw->mac_type == e1000_80003es2lan) {
1046                 /* Release both semaphores. */
1047                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1048         } else
1049                 swsm &= ~(E1000_SWSM_SWESMBI);
1050         E1000_WRITE_REG(hw, SWSM, swsm);
1051 #endif
1052 }
1053
1054 /***************************************************************************
1055  *
1056  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1057  * adapter or Eeprom access.
1058  *
1059  * hw: Struct containing variables accessed by shared code
1060  *
1061  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1062  *            E1000_SUCCESS at any other case.
1063  *
1064  ***************************************************************************/
1065 static int32_t
1066 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1067 {
1068 #ifndef CONFIG_E1000_NO_NVM
1069         int32_t timeout;
1070         uint32_t swsm;
1071
1072         DEBUGFUNC();
1073
1074         if (!hw->eeprom_semaphore_present)
1075                 return E1000_SUCCESS;
1076
1077         if (hw->mac_type == e1000_80003es2lan) {
1078                 /* Get the SW semaphore. */
1079                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1080                         return -E1000_ERR_EEPROM;
1081         }
1082
1083         /* Get the FW semaphore. */
1084         timeout = hw->eeprom.word_size + 1;
1085         while (timeout) {
1086                 swsm = E1000_READ_REG(hw, SWSM);
1087                 swsm |= E1000_SWSM_SWESMBI;
1088                 E1000_WRITE_REG(hw, SWSM, swsm);
1089                 /* if we managed to set the bit we got the semaphore. */
1090                 swsm = E1000_READ_REG(hw, SWSM);
1091                 if (swsm & E1000_SWSM_SWESMBI)
1092                         break;
1093
1094                 udelay(50);
1095                 timeout--;
1096         }
1097
1098         if (!timeout) {
1099                 /* Release semaphores */
1100                 e1000_put_hw_eeprom_semaphore(hw);
1101                 DEBUGOUT("Driver can't access the Eeprom - "
1102                                 "SWESMBI bit is set.\n");
1103                 return -E1000_ERR_EEPROM;
1104         }
1105 #endif
1106         return E1000_SUCCESS;
1107 }
1108
1109 /* Take ownership of the PHY */
1110 static int32_t
1111 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1112 {
1113         uint32_t swfw_sync = 0;
1114         uint32_t swmask = mask;
1115         uint32_t fwmask = mask << 16;
1116         int32_t timeout = 200;
1117
1118         DEBUGFUNC();
1119         while (timeout) {
1120                 if (e1000_get_hw_eeprom_semaphore(hw))
1121                         return -E1000_ERR_SWFW_SYNC;
1122
1123                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1124                 if (!(swfw_sync & (fwmask | swmask)))
1125                         break;
1126
1127                 /* firmware currently using resource (fwmask) */
1128                 /* or other software thread currently using resource (swmask) */
1129                 e1000_put_hw_eeprom_semaphore(hw);
1130                 mdelay(5);
1131                 timeout--;
1132         }
1133
1134         if (!timeout) {
1135                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1136                 return -E1000_ERR_SWFW_SYNC;
1137         }
1138
1139         swfw_sync |= swmask;
1140         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1141
1142         e1000_put_hw_eeprom_semaphore(hw);
1143         return E1000_SUCCESS;
1144 }
1145
1146 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1147 {
1148         uint32_t swfw_sync = 0;
1149
1150         DEBUGFUNC();
1151         while (e1000_get_hw_eeprom_semaphore(hw))
1152                 ; /* Empty */
1153
1154         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1155         swfw_sync &= ~mask;
1156         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1157
1158         e1000_put_hw_eeprom_semaphore(hw);
1159 }
1160
1161 static bool e1000_is_second_port(struct e1000_hw *hw)
1162 {
1163         switch (hw->mac_type) {
1164         case e1000_80003es2lan:
1165         case e1000_82546:
1166         case e1000_82571:
1167                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1168                         return true;
1169                 /* Fallthrough */
1170         default:
1171                 return false;
1172         }
1173 }
1174
1175 #ifndef CONFIG_E1000_NO_NVM
1176 /******************************************************************************
1177  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1178  * second function of dual function devices
1179  *
1180  * nic - Struct containing variables accessed by shared code
1181  *****************************************************************************/
1182 static int
1183 e1000_read_mac_addr(struct eth_device *nic)
1184 {
1185         struct e1000_hw *hw = nic->priv;
1186         uint16_t offset;
1187         uint16_t eeprom_data;
1188         uint32_t reg_data = 0;
1189         int i;
1190
1191         DEBUGFUNC();
1192
1193         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1194                 offset = i >> 1;
1195                 if (hw->mac_type == e1000_igb) {
1196                         /* i210 preloads MAC address into RAL/RAH registers */
1197                         if (offset == 0)
1198                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1199                         else if (offset == 1)
1200                                 reg_data >>= 16;
1201                         else if (offset == 2)
1202                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1203                         eeprom_data = reg_data & 0xffff;
1204                 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1205                         DEBUGOUT("EEPROM Read Error\n");
1206                         return -E1000_ERR_EEPROM;
1207                 }
1208                 nic->enetaddr[i] = eeprom_data & 0xff;
1209                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1210         }
1211
1212         /* Invert the last bit if this is the second device */
1213         if (e1000_is_second_port(hw))
1214                 nic->enetaddr[5] ^= 1;
1215
1216 #ifdef CONFIG_E1000_FALLBACK_MAC
1217         if (!is_valid_ethaddr(nic->enetaddr)) {
1218                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1219
1220                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1221         }
1222 #endif
1223         return 0;
1224 }
1225 #endif
1226
1227 /******************************************************************************
1228  * Initializes receive address filters.
1229  *
1230  * hw - Struct containing variables accessed by shared code
1231  *
1232  * Places the MAC address in receive address register 0 and clears the rest
1233  * of the receive addresss registers. Clears the multicast table. Assumes
1234  * the receiver is in reset when the routine is called.
1235  *****************************************************************************/
1236 static void
1237 e1000_init_rx_addrs(struct eth_device *nic)
1238 {
1239         struct e1000_hw *hw = nic->priv;
1240         uint32_t i;
1241         uint32_t addr_low;
1242         uint32_t addr_high;
1243
1244         DEBUGFUNC();
1245
1246         /* Setup the receive address. */
1247         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1248         addr_low = (nic->enetaddr[0] |
1249                     (nic->enetaddr[1] << 8) |
1250                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1251
1252         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1253
1254         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1255         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1256
1257         /* Zero out the other 15 receive addresses. */
1258         DEBUGOUT("Clearing RAR[1-15]\n");
1259         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1260                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1261                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1262         }
1263 }
1264
1265 /******************************************************************************
1266  * Clears the VLAN filer table
1267  *
1268  * hw - Struct containing variables accessed by shared code
1269  *****************************************************************************/
1270 static void
1271 e1000_clear_vfta(struct e1000_hw *hw)
1272 {
1273         uint32_t offset;
1274
1275         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1276                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1277 }
1278
1279 /******************************************************************************
1280  * Set the mac type member in the hw struct.
1281  *
1282  * hw - Struct containing variables accessed by shared code
1283  *****************************************************************************/
1284 int32_t
1285 e1000_set_mac_type(struct e1000_hw *hw)
1286 {
1287         DEBUGFUNC();
1288
1289         switch (hw->device_id) {
1290         case E1000_DEV_ID_82542:
1291                 switch (hw->revision_id) {
1292                 case E1000_82542_2_0_REV_ID:
1293                         hw->mac_type = e1000_82542_rev2_0;
1294                         break;
1295                 case E1000_82542_2_1_REV_ID:
1296                         hw->mac_type = e1000_82542_rev2_1;
1297                         break;
1298                 default:
1299                         /* Invalid 82542 revision ID */
1300                         return -E1000_ERR_MAC_TYPE;
1301                 }
1302                 break;
1303         case E1000_DEV_ID_82543GC_FIBER:
1304         case E1000_DEV_ID_82543GC_COPPER:
1305                 hw->mac_type = e1000_82543;
1306                 break;
1307         case E1000_DEV_ID_82544EI_COPPER:
1308         case E1000_DEV_ID_82544EI_FIBER:
1309         case E1000_DEV_ID_82544GC_COPPER:
1310         case E1000_DEV_ID_82544GC_LOM:
1311                 hw->mac_type = e1000_82544;
1312                 break;
1313         case E1000_DEV_ID_82540EM:
1314         case E1000_DEV_ID_82540EM_LOM:
1315         case E1000_DEV_ID_82540EP:
1316         case E1000_DEV_ID_82540EP_LOM:
1317         case E1000_DEV_ID_82540EP_LP:
1318                 hw->mac_type = e1000_82540;
1319                 break;
1320         case E1000_DEV_ID_82545EM_COPPER:
1321         case E1000_DEV_ID_82545EM_FIBER:
1322                 hw->mac_type = e1000_82545;
1323                 break;
1324         case E1000_DEV_ID_82545GM_COPPER:
1325         case E1000_DEV_ID_82545GM_FIBER:
1326         case E1000_DEV_ID_82545GM_SERDES:
1327                 hw->mac_type = e1000_82545_rev_3;
1328                 break;
1329         case E1000_DEV_ID_82546EB_COPPER:
1330         case E1000_DEV_ID_82546EB_FIBER:
1331         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1332                 hw->mac_type = e1000_82546;
1333                 break;
1334         case E1000_DEV_ID_82546GB_COPPER:
1335         case E1000_DEV_ID_82546GB_FIBER:
1336         case E1000_DEV_ID_82546GB_SERDES:
1337         case E1000_DEV_ID_82546GB_PCIE:
1338         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1339         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1340                 hw->mac_type = e1000_82546_rev_3;
1341                 break;
1342         case E1000_DEV_ID_82541EI:
1343         case E1000_DEV_ID_82541EI_MOBILE:
1344         case E1000_DEV_ID_82541ER_LOM:
1345                 hw->mac_type = e1000_82541;
1346                 break;
1347         case E1000_DEV_ID_82541ER:
1348         case E1000_DEV_ID_82541GI:
1349         case E1000_DEV_ID_82541GI_LF:
1350         case E1000_DEV_ID_82541GI_MOBILE:
1351                 hw->mac_type = e1000_82541_rev_2;
1352                 break;
1353         case E1000_DEV_ID_82547EI:
1354         case E1000_DEV_ID_82547EI_MOBILE:
1355                 hw->mac_type = e1000_82547;
1356                 break;
1357         case E1000_DEV_ID_82547GI:
1358                 hw->mac_type = e1000_82547_rev_2;
1359                 break;
1360         case E1000_DEV_ID_82571EB_COPPER:
1361         case E1000_DEV_ID_82571EB_FIBER:
1362         case E1000_DEV_ID_82571EB_SERDES:
1363         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1364         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1365         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1366         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1367         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1368         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1369                 hw->mac_type = e1000_82571;
1370                 break;
1371         case E1000_DEV_ID_82572EI_COPPER:
1372         case E1000_DEV_ID_82572EI_FIBER:
1373         case E1000_DEV_ID_82572EI_SERDES:
1374         case E1000_DEV_ID_82572EI:
1375                 hw->mac_type = e1000_82572;
1376                 break;
1377         case E1000_DEV_ID_82573E:
1378         case E1000_DEV_ID_82573E_IAMT:
1379         case E1000_DEV_ID_82573L:
1380                 hw->mac_type = e1000_82573;
1381                 break;
1382         case E1000_DEV_ID_82574L:
1383                 hw->mac_type = e1000_82574;
1384                 break;
1385         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1386         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1387         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1388         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1389                 hw->mac_type = e1000_80003es2lan;
1390                 break;
1391         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1392         case E1000_DEV_ID_ICH8_IGP_AMT:
1393         case E1000_DEV_ID_ICH8_IGP_C:
1394         case E1000_DEV_ID_ICH8_IFE:
1395         case E1000_DEV_ID_ICH8_IFE_GT:
1396         case E1000_DEV_ID_ICH8_IFE_G:
1397         case E1000_DEV_ID_ICH8_IGP_M:
1398                 hw->mac_type = e1000_ich8lan;
1399                 break;
1400         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1401         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1402         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1403         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1404         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1405         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1406         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1407         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1408                 hw->mac_type = e1000_igb;
1409                 break;
1410         default:
1411                 /* Should never have loaded on this device */
1412                 return -E1000_ERR_MAC_TYPE;
1413         }
1414         return E1000_SUCCESS;
1415 }
1416
1417 /******************************************************************************
1418  * Reset the transmit and receive units; mask and clear all interrupts.
1419  *
1420  * hw - Struct containing variables accessed by shared code
1421  *****************************************************************************/
1422 void
1423 e1000_reset_hw(struct e1000_hw *hw)
1424 {
1425         uint32_t ctrl;
1426         uint32_t ctrl_ext;
1427         uint32_t manc;
1428         uint32_t pba = 0;
1429         uint32_t reg;
1430
1431         DEBUGFUNC();
1432
1433         /* get the correct pba value for both PCI and PCIe*/
1434         if (hw->mac_type <  e1000_82571)
1435                 pba = E1000_DEFAULT_PCI_PBA;
1436         else
1437                 pba = E1000_DEFAULT_PCIE_PBA;
1438
1439         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1440         if (hw->mac_type == e1000_82542_rev2_0) {
1441                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1442                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1443                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1444         }
1445
1446         /* Clear interrupt mask to stop board from generating interrupts */
1447         DEBUGOUT("Masking off all interrupts\n");
1448         if (hw->mac_type == e1000_igb)
1449                 E1000_WRITE_REG(hw, I210_IAM, 0);
1450         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1451
1452         /* Disable the Transmit and Receive units.  Then delay to allow
1453          * any pending transactions to complete before we hit the MAC with
1454          * the global reset.
1455          */
1456         E1000_WRITE_REG(hw, RCTL, 0);
1457         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1458         E1000_WRITE_FLUSH(hw);
1459
1460         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1461         hw->tbi_compatibility_on = false;
1462
1463         /* Delay to allow any outstanding PCI transactions to complete before
1464          * resetting the device
1465          */
1466         mdelay(10);
1467
1468         /* Issue a global reset to the MAC.  This will reset the chip's
1469          * transmit, receive, DMA, and link units.  It will not effect
1470          * the current PCI configuration.  The global reset bit is self-
1471          * clearing, and should clear within a microsecond.
1472          */
1473         DEBUGOUT("Issuing a global reset to MAC\n");
1474         ctrl = E1000_READ_REG(hw, CTRL);
1475
1476         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1477
1478         /* Force a reload from the EEPROM if necessary */
1479         if (hw->mac_type == e1000_igb) {
1480                 mdelay(20);
1481                 reg = E1000_READ_REG(hw, STATUS);
1482                 if (reg & E1000_STATUS_PF_RST_DONE)
1483                         DEBUGOUT("PF OK\n");
1484                 reg = E1000_READ_REG(hw, I210_EECD);
1485                 if (reg & E1000_EECD_AUTO_RD)
1486                         DEBUGOUT("EEC OK\n");
1487         } else if (hw->mac_type < e1000_82540) {
1488                 /* Wait for reset to complete */
1489                 udelay(10);
1490                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1491                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1492                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1493                 E1000_WRITE_FLUSH(hw);
1494                 /* Wait for EEPROM reload */
1495                 mdelay(2);
1496         } else {
1497                 /* Wait for EEPROM reload (it happens automatically) */
1498                 mdelay(4);
1499                 /* Dissable HW ARPs on ASF enabled adapters */
1500                 manc = E1000_READ_REG(hw, MANC);
1501                 manc &= ~(E1000_MANC_ARP_EN);
1502                 E1000_WRITE_REG(hw, MANC, manc);
1503         }
1504
1505         /* Clear interrupt mask to stop board from generating interrupts */
1506         DEBUGOUT("Masking off all interrupts\n");
1507         if (hw->mac_type == e1000_igb)
1508                 E1000_WRITE_REG(hw, I210_IAM, 0);
1509         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1510
1511         /* Clear any pending interrupt events. */
1512         E1000_READ_REG(hw, ICR);
1513
1514         /* If MWI was previously enabled, reenable it. */
1515         if (hw->mac_type == e1000_82542_rev2_0) {
1516                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1517         }
1518         if (hw->mac_type != e1000_igb)
1519                 E1000_WRITE_REG(hw, PBA, pba);
1520 }
1521
1522 /******************************************************************************
1523  *
1524  * Initialize a number of hardware-dependent bits
1525  *
1526  * hw: Struct containing variables accessed by shared code
1527  *
1528  * This function contains hardware limitation workarounds for PCI-E adapters
1529  *
1530  *****************************************************************************/
1531 static void
1532 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1533 {
1534         if ((hw->mac_type >= e1000_82571) &&
1535                         (!hw->initialize_hw_bits_disable)) {
1536                 /* Settings common to all PCI-express silicon */
1537                 uint32_t reg_ctrl, reg_ctrl_ext;
1538                 uint32_t reg_tarc0, reg_tarc1;
1539                 uint32_t reg_tctl;
1540                 uint32_t reg_txdctl, reg_txdctl1;
1541
1542                 /* link autonegotiation/sync workarounds */
1543                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1544                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1545
1546                 /* Enable not-done TX descriptor counting */
1547                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1548                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1549                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1550
1551                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1552                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1553                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1554
1555         /* IGB is cool */
1556         if (hw->mac_type == e1000_igb)
1557                 return;
1558
1559                 switch (hw->mac_type) {
1560                 case e1000_82571:
1561                 case e1000_82572:
1562                         /* Clear PHY TX compatible mode bits */
1563                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1564                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1565
1566                         /* link autonegotiation/sync workarounds */
1567                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1568
1569                         /* TX ring control fixes */
1570                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1571
1572                         /* Multiple read bit is reversed polarity */
1573                         reg_tctl = E1000_READ_REG(hw, TCTL);
1574                         if (reg_tctl & E1000_TCTL_MULR)
1575                                 reg_tarc1 &= ~(1 << 28);
1576                         else
1577                                 reg_tarc1 |= (1 << 28);
1578
1579                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1580                         break;
1581                 case e1000_82573:
1582                 case e1000_82574:
1583                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1584                         reg_ctrl_ext &= ~(1 << 23);
1585                         reg_ctrl_ext |= (1 << 22);
1586
1587                         /* TX byte count fix */
1588                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1589                         reg_ctrl &= ~(1 << 29);
1590
1591                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1592                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1593                         break;
1594                 case e1000_80003es2lan:
1595         /* improve small packet performace for fiber/serdes */
1596                         if ((hw->media_type == e1000_media_type_fiber)
1597                         || (hw->media_type ==
1598                                 e1000_media_type_internal_serdes)) {
1599                                 reg_tarc0 &= ~(1 << 20);
1600                         }
1601
1602                 /* Multiple read bit is reversed polarity */
1603                         reg_tctl = E1000_READ_REG(hw, TCTL);
1604                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1605                         if (reg_tctl & E1000_TCTL_MULR)
1606                                 reg_tarc1 &= ~(1 << 28);
1607                         else
1608                                 reg_tarc1 |= (1 << 28);
1609
1610                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1611                         break;
1612                 case e1000_ich8lan:
1613                         /* Reduce concurrent DMA requests to 3 from 4 */
1614                         if ((hw->revision_id < 3) ||
1615                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1616                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1617                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1618
1619                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1620                         reg_ctrl_ext |= (1 << 22);
1621                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1622
1623                         /* workaround TX hang with TSO=on */
1624                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1625
1626                         /* Multiple read bit is reversed polarity */
1627                         reg_tctl = E1000_READ_REG(hw, TCTL);
1628                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1629                         if (reg_tctl & E1000_TCTL_MULR)
1630                                 reg_tarc1 &= ~(1 << 28);
1631                         else
1632                                 reg_tarc1 |= (1 << 28);
1633
1634                         /* workaround TX hang with TSO=on */
1635                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1636
1637                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1638                         break;
1639                 default:
1640                         break;
1641                 }
1642
1643                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1644         }
1645 }
1646
1647 /******************************************************************************
1648  * Performs basic configuration of the adapter.
1649  *
1650  * hw - Struct containing variables accessed by shared code
1651  *
1652  * Assumes that the controller has previously been reset and is in a
1653  * post-reset uninitialized state. Initializes the receive address registers,
1654  * multicast table, and VLAN filter table. Calls routines to setup link
1655  * configuration and flow control settings. Clears all on-chip counters. Leaves
1656  * the transmit and receive units disabled and uninitialized.
1657  *****************************************************************************/
1658 static int
1659 e1000_init_hw(struct eth_device *nic)
1660 {
1661         struct e1000_hw *hw = nic->priv;
1662         uint32_t ctrl;
1663         uint32_t i;
1664         int32_t ret_val;
1665         uint16_t pcix_cmd_word;
1666         uint16_t pcix_stat_hi_word;
1667         uint16_t cmd_mmrbc;
1668         uint16_t stat_mmrbc;
1669         uint32_t mta_size;
1670         uint32_t reg_data;
1671         uint32_t ctrl_ext;
1672         DEBUGFUNC();
1673         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1674         if ((hw->mac_type == e1000_ich8lan) &&
1675                 ((hw->revision_id < 3) ||
1676                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1677                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1678                         reg_data = E1000_READ_REG(hw, STATUS);
1679                         reg_data &= ~0x80000000;
1680                         E1000_WRITE_REG(hw, STATUS, reg_data);
1681         }
1682         /* Do not need initialize Identification LED */
1683
1684         /* Set the media type and TBI compatibility */
1685         e1000_set_media_type(hw);
1686
1687         /* Must be called after e1000_set_media_type
1688          * because media_type is used */
1689         e1000_initialize_hardware_bits(hw);
1690
1691         /* Disabling VLAN filtering. */
1692         DEBUGOUT("Initializing the IEEE VLAN\n");
1693         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1694         if (hw->mac_type != e1000_ich8lan) {
1695                 if (hw->mac_type < e1000_82545_rev_3)
1696                         E1000_WRITE_REG(hw, VET, 0);
1697                 e1000_clear_vfta(hw);
1698         }
1699
1700         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1701         if (hw->mac_type == e1000_82542_rev2_0) {
1702                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1703                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1704                                       hw->
1705                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1706                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1707                 E1000_WRITE_FLUSH(hw);
1708                 mdelay(5);
1709         }
1710
1711         /* Setup the receive address. This involves initializing all of the Receive
1712          * Address Registers (RARs 0 - 15).
1713          */
1714         e1000_init_rx_addrs(nic);
1715
1716         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1717         if (hw->mac_type == e1000_82542_rev2_0) {
1718                 E1000_WRITE_REG(hw, RCTL, 0);
1719                 E1000_WRITE_FLUSH(hw);
1720                 mdelay(1);
1721                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1722         }
1723
1724         /* Zero out the Multicast HASH table */
1725         DEBUGOUT("Zeroing the MTA\n");
1726         mta_size = E1000_MC_TBL_SIZE;
1727         if (hw->mac_type == e1000_ich8lan)
1728                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1729         for (i = 0; i < mta_size; i++) {
1730                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1731                 /* use write flush to prevent Memory Write Block (MWB) from
1732                  * occuring when accessing our register space */
1733                 E1000_WRITE_FLUSH(hw);
1734         }
1735 #if 0
1736         /* Set the PCI priority bit correctly in the CTRL register.  This
1737          * determines if the adapter gives priority to receives, or if it
1738          * gives equal priority to transmits and receives.  Valid only on
1739          * 82542 and 82543 silicon.
1740          */
1741         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1742                 ctrl = E1000_READ_REG(hw, CTRL);
1743                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1744         }
1745 #endif
1746         switch (hw->mac_type) {
1747         case e1000_82545_rev_3:
1748         case e1000_82546_rev_3:
1749         case e1000_igb:
1750                 break;
1751         default:
1752         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1753         if (hw->bus_type == e1000_bus_type_pcix) {
1754                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1755                                      &pcix_cmd_word);
1756                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1757                                      &pcix_stat_hi_word);
1758                 cmd_mmrbc =
1759                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1760                     PCIX_COMMAND_MMRBC_SHIFT;
1761                 stat_mmrbc =
1762                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1763                     PCIX_STATUS_HI_MMRBC_SHIFT;
1764                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1765                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1766                 if (cmd_mmrbc > stat_mmrbc) {
1767                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1768                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1769                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1770                                               pcix_cmd_word);
1771                 }
1772         }
1773                 break;
1774         }
1775
1776         /* More time needed for PHY to initialize */
1777         if (hw->mac_type == e1000_ich8lan)
1778                 mdelay(15);
1779         if (hw->mac_type == e1000_igb)
1780                 mdelay(15);
1781
1782         /* Call a subroutine to configure the link and setup flow control. */
1783         ret_val = e1000_setup_link(nic);
1784
1785         /* Set the transmit descriptor write-back policy */
1786         if (hw->mac_type > e1000_82544) {
1787                 ctrl = E1000_READ_REG(hw, TXDCTL);
1788                 ctrl =
1789                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1790                     E1000_TXDCTL_FULL_TX_DESC_WB;
1791                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1792         }
1793
1794         /* Set the receive descriptor write back policy */
1795         if (hw->mac_type >= e1000_82571) {
1796                 ctrl = E1000_READ_REG(hw, RXDCTL);
1797                 ctrl =
1798                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1799                     E1000_RXDCTL_FULL_RX_DESC_WB;
1800                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1801         }
1802
1803         switch (hw->mac_type) {
1804         default:
1805                 break;
1806         case e1000_80003es2lan:
1807                 /* Enable retransmit on late collisions */
1808                 reg_data = E1000_READ_REG(hw, TCTL);
1809                 reg_data |= E1000_TCTL_RTLC;
1810                 E1000_WRITE_REG(hw, TCTL, reg_data);
1811
1812                 /* Configure Gigabit Carry Extend Padding */
1813                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1814                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1815                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1816                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1817
1818                 /* Configure Transmit Inter-Packet Gap */
1819                 reg_data = E1000_READ_REG(hw, TIPG);
1820                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1821                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1822                 E1000_WRITE_REG(hw, TIPG, reg_data);
1823
1824                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1825                 reg_data &= ~0x00100000;
1826                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1827                 /* Fall through */
1828         case e1000_82571:
1829         case e1000_82572:
1830         case e1000_ich8lan:
1831                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1832                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1833                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1834                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1835                 break;
1836         case e1000_82573:
1837         case e1000_82574:
1838                 reg_data = E1000_READ_REG(hw, GCR);
1839                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1840                 E1000_WRITE_REG(hw, GCR, reg_data);
1841         case e1000_igb:
1842                 break;
1843         }
1844
1845 #if 0
1846         /* Clear all of the statistics registers (clear on read).  It is
1847          * important that we do this after we have tried to establish link
1848          * because the symbol error count will increment wildly if there
1849          * is no link.
1850          */
1851         e1000_clear_hw_cntrs(hw);
1852
1853         /* ICH8 No-snoop bits are opposite polarity.
1854          * Set to snoop by default after reset. */
1855         if (hw->mac_type == e1000_ich8lan)
1856                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1857 #endif
1858
1859         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1860                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1861                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1862                 /* Relaxed ordering must be disabled to avoid a parity
1863                  * error crash in a PCI slot. */
1864                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1865                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1866         }
1867
1868         return ret_val;
1869 }
1870
1871 /******************************************************************************
1872  * Configures flow control and link settings.
1873  *
1874  * hw - Struct containing variables accessed by shared code
1875  *
1876  * Determines which flow control settings to use. Calls the apropriate media-
1877  * specific link configuration function. Configures the flow control settings.
1878  * Assuming the adapter has a valid link partner, a valid link should be
1879  * established. Assumes the hardware has previously been reset and the
1880  * transmitter and receiver are not enabled.
1881  *****************************************************************************/
1882 static int
1883 e1000_setup_link(struct eth_device *nic)
1884 {
1885         struct e1000_hw *hw = nic->priv;
1886         int32_t ret_val;
1887 #ifndef CONFIG_E1000_NO_NVM
1888         uint32_t ctrl_ext;
1889         uint16_t eeprom_data;
1890 #endif
1891
1892         DEBUGFUNC();
1893
1894         /* In the case of the phy reset being blocked, we already have a link.
1895          * We do not have to set it up again. */
1896         if (e1000_check_phy_reset_block(hw))
1897                 return E1000_SUCCESS;
1898
1899 #ifndef CONFIG_E1000_NO_NVM
1900         /* Read and store word 0x0F of the EEPROM. This word contains bits
1901          * that determine the hardware's default PAUSE (flow control) mode,
1902          * a bit that determines whether the HW defaults to enabling or
1903          * disabling auto-negotiation, and the direction of the
1904          * SW defined pins. If there is no SW over-ride of the flow
1905          * control setting, then the variable hw->fc will
1906          * be initialized based on a value in the EEPROM.
1907          */
1908         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1909                                 &eeprom_data) < 0) {
1910                 DEBUGOUT("EEPROM Read Error\n");
1911                 return -E1000_ERR_EEPROM;
1912         }
1913 #endif
1914         if (hw->fc == e1000_fc_default) {
1915                 switch (hw->mac_type) {
1916                 case e1000_ich8lan:
1917                 case e1000_82573:
1918                 case e1000_82574:
1919                 case e1000_igb:
1920                         hw->fc = e1000_fc_full;
1921                         break;
1922                 default:
1923 #ifndef CONFIG_E1000_NO_NVM
1924                         ret_val = e1000_read_eeprom(hw,
1925                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1926                         if (ret_val) {
1927                                 DEBUGOUT("EEPROM Read Error\n");
1928                                 return -E1000_ERR_EEPROM;
1929                         }
1930                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1931                                 hw->fc = e1000_fc_none;
1932                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1933                                     EEPROM_WORD0F_ASM_DIR)
1934                                 hw->fc = e1000_fc_tx_pause;
1935                         else
1936 #endif
1937                                 hw->fc = e1000_fc_full;
1938                         break;
1939                 }
1940         }
1941
1942         /* We want to save off the original Flow Control configuration just
1943          * in case we get disconnected and then reconnected into a different
1944          * hub or switch with different Flow Control capabilities.
1945          */
1946         if (hw->mac_type == e1000_82542_rev2_0)
1947                 hw->fc &= (~e1000_fc_tx_pause);
1948
1949         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1950                 hw->fc &= (~e1000_fc_rx_pause);
1951
1952         hw->original_fc = hw->fc;
1953
1954         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1955
1956 #ifndef CONFIG_E1000_NO_NVM
1957         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1958          * polarity value for the SW controlled pins, and setup the
1959          * Extended Device Control reg with that info.
1960          * This is needed because one of the SW controlled pins is used for
1961          * signal detection.  So this should be done before e1000_setup_pcs_link()
1962          * or e1000_phy_setup() is called.
1963          */
1964         if (hw->mac_type == e1000_82543) {
1965                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1966                             SWDPIO__EXT_SHIFT);
1967                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1968         }
1969 #endif
1970
1971         /* Call the necessary subroutine to configure the link. */
1972         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1973             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1974         if (ret_val < 0) {
1975                 return ret_val;
1976         }
1977
1978         /* Initialize the flow control address, type, and PAUSE timer
1979          * registers to their default values.  This is done even if flow
1980          * control is disabled, because it does not hurt anything to
1981          * initialize these registers.
1982          */
1983         DEBUGOUT("Initializing the Flow Control address, type"
1984                         "and timer regs\n");
1985
1986         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1987         if (hw->mac_type != e1000_ich8lan) {
1988                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1989                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1990                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1991         }
1992
1993         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1994
1995         /* Set the flow control receive threshold registers.  Normally,
1996          * these registers will be set to a default threshold that may be
1997          * adjusted later by the driver's runtime code.  However, if the
1998          * ability to transmit pause frames in not enabled, then these
1999          * registers will be set to 0.
2000          */
2001         if (!(hw->fc & e1000_fc_tx_pause)) {
2002                 E1000_WRITE_REG(hw, FCRTL, 0);
2003                 E1000_WRITE_REG(hw, FCRTH, 0);
2004         } else {
2005                 /* We need to set up the Receive Threshold high and low water marks
2006                  * as well as (optionally) enabling the transmission of XON frames.
2007                  */
2008                 if (hw->fc_send_xon) {
2009                         E1000_WRITE_REG(hw, FCRTL,
2010                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2011                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2012                 } else {
2013                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2014                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2015                 }
2016         }
2017         return ret_val;
2018 }
2019
2020 /******************************************************************************
2021  * Sets up link for a fiber based adapter
2022  *
2023  * hw - Struct containing variables accessed by shared code
2024  *
2025  * Manipulates Physical Coding Sublayer functions in order to configure
2026  * link. Assumes the hardware has been previously reset and the transmitter
2027  * and receiver are not enabled.
2028  *****************************************************************************/
2029 static int
2030 e1000_setup_fiber_link(struct eth_device *nic)
2031 {
2032         struct e1000_hw *hw = nic->priv;
2033         uint32_t ctrl;
2034         uint32_t status;
2035         uint32_t txcw = 0;
2036         uint32_t i;
2037         uint32_t signal;
2038         int32_t ret_val;
2039
2040         DEBUGFUNC();
2041         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2042          * set when the optics detect a signal. On older adapters, it will be
2043          * cleared when there is a signal
2044          */
2045         ctrl = E1000_READ_REG(hw, CTRL);
2046         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2047                 signal = E1000_CTRL_SWDPIN1;
2048         else
2049                 signal = 0;
2050
2051         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2052                ctrl);
2053         /* Take the link out of reset */
2054         ctrl &= ~(E1000_CTRL_LRST);
2055
2056         e1000_config_collision_dist(hw);
2057
2058         /* Check for a software override of the flow control settings, and setup
2059          * the device accordingly.  If auto-negotiation is enabled, then software
2060          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2061          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2062          * auto-negotiation is disabled, then software will have to manually
2063          * configure the two flow control enable bits in the CTRL register.
2064          *
2065          * The possible values of the "fc" parameter are:
2066          *      0:  Flow control is completely disabled
2067          *      1:  Rx flow control is enabled (we can receive pause frames, but
2068          *          not send pause frames).
2069          *      2:  Tx flow control is enabled (we can send pause frames but we do
2070          *          not support receiving pause frames).
2071          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2072          */
2073         switch (hw->fc) {
2074         case e1000_fc_none:
2075                 /* Flow control is completely disabled by a software over-ride. */
2076                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2077                 break;
2078         case e1000_fc_rx_pause:
2079                 /* RX Flow control is enabled and TX Flow control is disabled by a
2080                  * software over-ride. Since there really isn't a way to advertise
2081                  * that we are capable of RX Pause ONLY, we will advertise that we
2082                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2083                  *  disable the adapter's ability to send PAUSE frames.
2084                  */
2085                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2086                 break;
2087         case e1000_fc_tx_pause:
2088                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2089                  * software over-ride.
2090                  */
2091                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2092                 break;
2093         case e1000_fc_full:
2094                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2095                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2096                 break;
2097         default:
2098                 DEBUGOUT("Flow control param set incorrectly\n");
2099                 return -E1000_ERR_CONFIG;
2100                 break;
2101         }
2102
2103         /* Since auto-negotiation is enabled, take the link out of reset (the link
2104          * will be in reset, because we previously reset the chip). This will
2105          * restart auto-negotiation.  If auto-neogtiation is successful then the
2106          * link-up status bit will be set and the flow control enable bits (RFCE
2107          * and TFCE) will be set according to their negotiated value.
2108          */
2109         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2110
2111         E1000_WRITE_REG(hw, TXCW, txcw);
2112         E1000_WRITE_REG(hw, CTRL, ctrl);
2113         E1000_WRITE_FLUSH(hw);
2114
2115         hw->txcw = txcw;
2116         mdelay(1);
2117
2118         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2119          * indication in the Device Status Register.  Time-out if a link isn't
2120          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2121          * less than 500 milliseconds even if the other end is doing it in SW).
2122          */
2123         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2124                 DEBUGOUT("Looking for Link\n");
2125                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2126                         mdelay(10);
2127                         status = E1000_READ_REG(hw, STATUS);
2128                         if (status & E1000_STATUS_LU)
2129                                 break;
2130                 }
2131                 if (i == (LINK_UP_TIMEOUT / 10)) {
2132                         /* AutoNeg failed to achieve a link, so we'll call
2133                          * e1000_check_for_link. This routine will force the link up if we
2134                          * detect a signal. This will allow us to communicate with
2135                          * non-autonegotiating link partners.
2136                          */
2137                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2138                         hw->autoneg_failed = 1;
2139                         ret_val = e1000_check_for_link(nic);
2140                         if (ret_val < 0) {
2141                                 DEBUGOUT("Error while checking for link\n");
2142                                 return ret_val;
2143                         }
2144                         hw->autoneg_failed = 0;
2145                 } else {
2146                         hw->autoneg_failed = 0;
2147                         DEBUGOUT("Valid Link Found\n");
2148                 }
2149         } else {
2150                 DEBUGOUT("No Signal Detected\n");
2151                 return -E1000_ERR_NOLINK;
2152         }
2153         return 0;
2154 }
2155
2156 /******************************************************************************
2157 * Make sure we have a valid PHY and change PHY mode before link setup.
2158 *
2159 * hw - Struct containing variables accessed by shared code
2160 ******************************************************************************/
2161 static int32_t
2162 e1000_copper_link_preconfig(struct e1000_hw *hw)
2163 {
2164         uint32_t ctrl;
2165         int32_t ret_val;
2166         uint16_t phy_data;
2167
2168         DEBUGFUNC();
2169
2170         ctrl = E1000_READ_REG(hw, CTRL);
2171         /* With 82543, we need to force speed and duplex on the MAC equal to what
2172          * the PHY speed and duplex configuration is. In addition, we need to
2173          * perform a hardware reset on the PHY to take it out of reset.
2174          */
2175         if (hw->mac_type > e1000_82543) {
2176                 ctrl |= E1000_CTRL_SLU;
2177                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2178                 E1000_WRITE_REG(hw, CTRL, ctrl);
2179         } else {
2180                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2181                                 | E1000_CTRL_SLU);
2182                 E1000_WRITE_REG(hw, CTRL, ctrl);
2183                 ret_val = e1000_phy_hw_reset(hw);
2184                 if (ret_val)
2185                         return ret_val;
2186         }
2187
2188         /* Make sure we have a valid PHY */
2189         ret_val = e1000_detect_gig_phy(hw);
2190         if (ret_val) {
2191                 DEBUGOUT("Error, did not detect valid phy.\n");
2192                 return ret_val;
2193         }
2194         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2195
2196         /* Set PHY to class A mode (if necessary) */
2197         ret_val = e1000_set_phy_mode(hw);
2198         if (ret_val)
2199                 return ret_val;
2200         if ((hw->mac_type == e1000_82545_rev_3) ||
2201                 (hw->mac_type == e1000_82546_rev_3)) {
2202                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2203                                 &phy_data);
2204                 phy_data |= 0x00000008;
2205                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2206                                 phy_data);
2207         }
2208
2209         if (hw->mac_type <= e1000_82543 ||
2210                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2211                 hw->mac_type == e1000_82541_rev_2
2212                 || hw->mac_type == e1000_82547_rev_2)
2213                         hw->phy_reset_disable = false;
2214
2215         return E1000_SUCCESS;
2216 }
2217
2218 /*****************************************************************************
2219  *
2220  * This function sets the lplu state according to the active flag.  When
2221  * activating lplu this function also disables smart speed and vise versa.
2222  * lplu will not be activated unless the device autonegotiation advertisment
2223  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2224  * hw: Struct containing variables accessed by shared code
2225  * active - true to enable lplu false to disable lplu.
2226  *
2227  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2228  *            E1000_SUCCESS at any other case.
2229  *
2230  ****************************************************************************/
2231
2232 static int32_t
2233 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2234 {
2235         uint32_t phy_ctrl = 0;
2236         int32_t ret_val;
2237         uint16_t phy_data;
2238         DEBUGFUNC();
2239
2240         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2241             && hw->phy_type != e1000_phy_igp_3)
2242                 return E1000_SUCCESS;
2243
2244         /* During driver activity LPLU should not be used or it will attain link
2245          * from the lowest speeds starting from 10Mbps. The capability is used
2246          * for Dx transitions and states */
2247         if (hw->mac_type == e1000_82541_rev_2
2248                         || hw->mac_type == e1000_82547_rev_2) {
2249                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2250                                 &phy_data);
2251                 if (ret_val)
2252                         return ret_val;
2253         } else if (hw->mac_type == e1000_ich8lan) {
2254                 /* MAC writes into PHY register based on the state transition
2255                  * and start auto-negotiation. SW driver can overwrite the
2256                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2257                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2258         } else {
2259                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2260                                 &phy_data);
2261                 if (ret_val)
2262                         return ret_val;
2263         }
2264
2265         if (!active) {
2266                 if (hw->mac_type == e1000_82541_rev_2 ||
2267                         hw->mac_type == e1000_82547_rev_2) {
2268                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2269                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2270                                         phy_data);
2271                         if (ret_val)
2272                                 return ret_val;
2273                 } else {
2274                         if (hw->mac_type == e1000_ich8lan) {
2275                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2276                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2277                         } else {
2278                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2279                                 ret_val = e1000_write_phy_reg(hw,
2280                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2281                                 if (ret_val)
2282                                         return ret_val;
2283                         }
2284                 }
2285
2286         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2287          * Dx states where the power conservation is most important.  During
2288          * driver activity we should enable SmartSpeed, so performance is
2289          * maintained. */
2290                 if (hw->smart_speed == e1000_smart_speed_on) {
2291                         ret_val = e1000_read_phy_reg(hw,
2292                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2293                         if (ret_val)
2294                                 return ret_val;
2295
2296                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2297                         ret_val = e1000_write_phy_reg(hw,
2298                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2299                         if (ret_val)
2300                                 return ret_val;
2301                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2302                         ret_val = e1000_read_phy_reg(hw,
2303                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2304                         if (ret_val)
2305                                 return ret_val;
2306
2307                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2308                         ret_val = e1000_write_phy_reg(hw,
2309                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2310                         if (ret_val)
2311                                 return ret_val;
2312                 }
2313
2314         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2315                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2316                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2317
2318                 if (hw->mac_type == e1000_82541_rev_2 ||
2319                     hw->mac_type == e1000_82547_rev_2) {
2320                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2321                         ret_val = e1000_write_phy_reg(hw,
2322                                         IGP01E1000_GMII_FIFO, phy_data);
2323                         if (ret_val)
2324                                 return ret_val;
2325                 } else {
2326                         if (hw->mac_type == e1000_ich8lan) {
2327                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2328                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2329                         } else {
2330                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2331                                 ret_val = e1000_write_phy_reg(hw,
2332                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2333                                 if (ret_val)
2334                                         return ret_val;
2335                         }
2336                 }
2337
2338                 /* When LPLU is enabled we should disable SmartSpeed */
2339                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2340                                 &phy_data);
2341                 if (ret_val)
2342                         return ret_val;
2343
2344                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2345                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2346                                 phy_data);
2347                 if (ret_val)
2348                         return ret_val;
2349         }
2350         return E1000_SUCCESS;
2351 }
2352
2353 /*****************************************************************************
2354  *
2355  * This function sets the lplu d0 state according to the active flag.  When
2356  * activating lplu this function also disables smart speed and vise versa.
2357  * lplu will not be activated unless the device autonegotiation advertisment
2358  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2359  * hw: Struct containing variables accessed by shared code
2360  * active - true to enable lplu false to disable lplu.
2361  *
2362  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2363  *            E1000_SUCCESS at any other case.
2364  *
2365  ****************************************************************************/
2366
2367 static int32_t
2368 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2369 {
2370         uint32_t phy_ctrl = 0;
2371         int32_t ret_val;
2372         uint16_t phy_data;
2373         DEBUGFUNC();
2374
2375         if (hw->mac_type <= e1000_82547_rev_2)
2376                 return E1000_SUCCESS;
2377
2378         if (hw->mac_type == e1000_ich8lan) {
2379                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2380         } else if (hw->mac_type == e1000_igb) {
2381                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2382         } else {
2383                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2384                                 &phy_data);
2385                 if (ret_val)
2386                         return ret_val;
2387         }
2388
2389         if (!active) {
2390                 if (hw->mac_type == e1000_ich8lan) {
2391                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2392                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2393                 } else if (hw->mac_type == e1000_igb) {
2394                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2395                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2396                 } else {
2397                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2398                         ret_val = e1000_write_phy_reg(hw,
2399                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2400                         if (ret_val)
2401                                 return ret_val;
2402                 }
2403
2404                 if (hw->mac_type == e1000_igb)
2405                         return E1000_SUCCESS;
2406
2407         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2408          * Dx states where the power conservation is most important.  During
2409          * driver activity we should enable SmartSpeed, so performance is
2410          * maintained. */
2411                 if (hw->smart_speed == e1000_smart_speed_on) {
2412                         ret_val = e1000_read_phy_reg(hw,
2413                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2414                         if (ret_val)
2415                                 return ret_val;
2416
2417                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2418                         ret_val = e1000_write_phy_reg(hw,
2419                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2420                         if (ret_val)
2421                                 return ret_val;
2422                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2423                         ret_val = e1000_read_phy_reg(hw,
2424                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2425                         if (ret_val)
2426                                 return ret_val;
2427
2428                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2429                         ret_val = e1000_write_phy_reg(hw,
2430                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2431                         if (ret_val)
2432                                 return ret_val;
2433                 }
2434
2435
2436         } else {
2437
2438                 if (hw->mac_type == e1000_ich8lan) {
2439                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2440                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2441                 } else if (hw->mac_type == e1000_igb) {
2442                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2443                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2444                 } else {
2445                         phy_data |= IGP02E1000_PM_D0_LPLU;
2446                         ret_val = e1000_write_phy_reg(hw,
2447                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2448                         if (ret_val)
2449                                 return ret_val;
2450                 }
2451
2452                 if (hw->mac_type == e1000_igb)
2453                         return E1000_SUCCESS;
2454
2455                 /* When LPLU is enabled we should disable SmartSpeed */
2456                 ret_val = e1000_read_phy_reg(hw,
2457                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2458                 if (ret_val)
2459                         return ret_val;
2460
2461                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2462                 ret_val = e1000_write_phy_reg(hw,
2463                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2464                 if (ret_val)
2465                         return ret_val;
2466
2467         }
2468         return E1000_SUCCESS;
2469 }
2470
2471 /********************************************************************
2472 * Copper link setup for e1000_phy_igp series.
2473 *
2474 * hw - Struct containing variables accessed by shared code
2475 *********************************************************************/
2476 static int32_t
2477 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2478 {
2479         uint32_t led_ctrl;
2480         int32_t ret_val;
2481         uint16_t phy_data;
2482
2483         DEBUGFUNC();
2484
2485         if (hw->phy_reset_disable)
2486                 return E1000_SUCCESS;
2487
2488         ret_val = e1000_phy_reset(hw);
2489         if (ret_val) {
2490                 DEBUGOUT("Error Resetting the PHY\n");
2491                 return ret_val;
2492         }
2493
2494         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2495         mdelay(15);
2496         if (hw->mac_type != e1000_ich8lan) {
2497                 /* Configure activity LED after PHY reset */
2498                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2499                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2500                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2501                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2502         }
2503
2504         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2505         if (hw->phy_type == e1000_phy_igp) {
2506                 /* disable lplu d3 during driver init */
2507                 ret_val = e1000_set_d3_lplu_state(hw, false);
2508                 if (ret_val) {
2509                         DEBUGOUT("Error Disabling LPLU D3\n");
2510                         return ret_val;
2511                 }
2512         }
2513
2514         /* disable lplu d0 during driver init */
2515         ret_val = e1000_set_d0_lplu_state(hw, false);
2516         if (ret_val) {
2517                 DEBUGOUT("Error Disabling LPLU D0\n");
2518                 return ret_val;
2519         }
2520         /* Configure mdi-mdix settings */
2521         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2522         if (ret_val)
2523                 return ret_val;
2524
2525         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2526                 hw->dsp_config_state = e1000_dsp_config_disabled;
2527                 /* Force MDI for earlier revs of the IGP PHY */
2528                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2529                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2530                 hw->mdix = 1;
2531
2532         } else {
2533                 hw->dsp_config_state = e1000_dsp_config_enabled;
2534                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2535
2536                 switch (hw->mdix) {
2537                 case 1:
2538                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2539                         break;
2540                 case 2:
2541                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2542                         break;
2543                 case 0:
2544                 default:
2545                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2546                         break;
2547                 }
2548         }
2549         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2550         if (ret_val)
2551                 return ret_val;
2552
2553         /* set auto-master slave resolution settings */
2554         if (hw->autoneg) {
2555                 e1000_ms_type phy_ms_setting = hw->master_slave;
2556
2557                 if (hw->ffe_config_state == e1000_ffe_config_active)
2558                         hw->ffe_config_state = e1000_ffe_config_enabled;
2559
2560                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2561                         hw->dsp_config_state = e1000_dsp_config_enabled;
2562
2563                 /* when autonegotiation advertisment is only 1000Mbps then we
2564                   * should disable SmartSpeed and enable Auto MasterSlave
2565                   * resolution as hardware default. */
2566                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2567                         /* Disable SmartSpeed */
2568                         ret_val = e1000_read_phy_reg(hw,
2569                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2570                         if (ret_val)
2571                                 return ret_val;
2572                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2573                         ret_val = e1000_write_phy_reg(hw,
2574                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2575                         if (ret_val)
2576                                 return ret_val;
2577                         /* Set auto Master/Slave resolution process */
2578                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2579                                         &phy_data);
2580                         if (ret_val)
2581                                 return ret_val;
2582                         phy_data &= ~CR_1000T_MS_ENABLE;
2583                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2584                                         phy_data);
2585                         if (ret_val)
2586                                 return ret_val;
2587                 }
2588
2589                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2590                 if (ret_val)
2591                         return ret_val;
2592
2593                 /* load defaults for future use */
2594                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2595                                 ((phy_data & CR_1000T_MS_VALUE) ?
2596                                 e1000_ms_force_master :
2597                                 e1000_ms_force_slave) :
2598                                 e1000_ms_auto;
2599
2600                 switch (phy_ms_setting) {
2601                 case e1000_ms_force_master:
2602                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2603                         break;
2604                 case e1000_ms_force_slave:
2605                         phy_data |= CR_1000T_MS_ENABLE;
2606                         phy_data &= ~(CR_1000T_MS_VALUE);
2607                         break;
2608                 case e1000_ms_auto:
2609                         phy_data &= ~CR_1000T_MS_ENABLE;
2610                 default:
2611                         break;
2612                 }
2613                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2614                 if (ret_val)
2615                         return ret_val;
2616         }
2617
2618         return E1000_SUCCESS;
2619 }
2620
2621 /*****************************************************************************
2622  * This function checks the mode of the firmware.
2623  *
2624  * returns  - true when the mode is IAMT or false.
2625  ****************************************************************************/
2626 bool
2627 e1000_check_mng_mode(struct e1000_hw *hw)
2628 {
2629         uint32_t fwsm;
2630         DEBUGFUNC();
2631
2632         fwsm = E1000_READ_REG(hw, FWSM);
2633
2634         if (hw->mac_type == e1000_ich8lan) {
2635                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2636                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2637                         return true;
2638         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2639                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2640                         return true;
2641
2642         return false;
2643 }
2644
2645 static int32_t
2646 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2647 {
2648         uint16_t swfw = E1000_SWFW_PHY0_SM;
2649         uint32_t reg_val;
2650         DEBUGFUNC();
2651
2652         if (e1000_is_second_port(hw))
2653                 swfw = E1000_SWFW_PHY1_SM;
2654
2655         if (e1000_swfw_sync_acquire(hw, swfw))
2656                 return -E1000_ERR_SWFW_SYNC;
2657
2658         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2659                         & E1000_KUMCTRLSTA_OFFSET) | data;
2660         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2661         udelay(2);
2662
2663         return E1000_SUCCESS;
2664 }
2665
2666 static int32_t
2667 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2668 {
2669         uint16_t swfw = E1000_SWFW_PHY0_SM;
2670         uint32_t reg_val;
2671         DEBUGFUNC();
2672
2673         if (e1000_is_second_port(hw))
2674                 swfw = E1000_SWFW_PHY1_SM;
2675
2676         if (e1000_swfw_sync_acquire(hw, swfw)) {
2677                 debug("%s[%i]\n", __func__, __LINE__);
2678                 return -E1000_ERR_SWFW_SYNC;
2679         }
2680
2681         /* Write register address */
2682         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2683                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2684         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2685         udelay(2);
2686
2687         /* Read the data returned */
2688         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2689         *data = (uint16_t)reg_val;
2690
2691         return E1000_SUCCESS;
2692 }
2693
2694 /********************************************************************
2695 * Copper link setup for e1000_phy_gg82563 series.
2696 *
2697 * hw - Struct containing variables accessed by shared code
2698 *********************************************************************/
2699 static int32_t
2700 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2701 {
2702         int32_t ret_val;
2703         uint16_t phy_data;
2704         uint32_t reg_data;
2705
2706         DEBUGFUNC();
2707
2708         if (!hw->phy_reset_disable) {
2709                 /* Enable CRS on TX for half-duplex operation. */
2710                 ret_val = e1000_read_phy_reg(hw,
2711                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2712                 if (ret_val)
2713                         return ret_val;
2714
2715                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2716                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2717                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2718
2719                 ret_val = e1000_write_phy_reg(hw,
2720                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2721                 if (ret_val)
2722                         return ret_val;
2723
2724                 /* Options:
2725                  *   MDI/MDI-X = 0 (default)
2726                  *   0 - Auto for all speeds
2727                  *   1 - MDI mode
2728                  *   2 - MDI-X mode
2729                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2730                  */
2731                 ret_val = e1000_read_phy_reg(hw,
2732                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2733                 if (ret_val)
2734                         return ret_val;
2735
2736                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2737
2738                 switch (hw->mdix) {
2739                 case 1:
2740                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2741                         break;
2742                 case 2:
2743                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2744                         break;
2745                 case 0:
2746                 default:
2747                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2748                         break;
2749                 }
2750
2751                 /* Options:
2752                  *   disable_polarity_correction = 0 (default)
2753                  *       Automatic Correction for Reversed Cable Polarity
2754                  *   0 - Disabled
2755                  *   1 - Enabled
2756                  */
2757                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2758                 ret_val = e1000_write_phy_reg(hw,
2759                                 GG82563_PHY_SPEC_CTRL, phy_data);
2760
2761                 if (ret_val)
2762                         return ret_val;
2763
2764                 /* SW Reset the PHY so all changes take effect */
2765                 ret_val = e1000_phy_reset(hw);
2766                 if (ret_val) {
2767                         DEBUGOUT("Error Resetting the PHY\n");
2768                         return ret_val;
2769                 }
2770         } /* phy_reset_disable */
2771
2772         if (hw->mac_type == e1000_80003es2lan) {
2773                 /* Bypass RX and TX FIFO's */
2774                 ret_val = e1000_write_kmrn_reg(hw,
2775                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2776                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2777                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2778                 if (ret_val)
2779                         return ret_val;
2780
2781                 ret_val = e1000_read_phy_reg(hw,
2782                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2783                 if (ret_val)
2784                         return ret_val;
2785
2786                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2787                 ret_val = e1000_write_phy_reg(hw,
2788                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2789
2790                 if (ret_val)
2791                         return ret_val;
2792
2793                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2794                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2795                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2796
2797                 ret_val = e1000_read_phy_reg(hw,
2798                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2799                 if (ret_val)
2800                         return ret_val;
2801
2802         /* Do not init these registers when the HW is in IAMT mode, since the
2803          * firmware will have already initialized them.  We only initialize
2804          * them if the HW is not in IAMT mode.
2805          */
2806                 if (e1000_check_mng_mode(hw) == false) {
2807                         /* Enable Electrical Idle on the PHY */
2808                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2809                         ret_val = e1000_write_phy_reg(hw,
2810                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2811                         if (ret_val)
2812                                 return ret_val;
2813
2814                         ret_val = e1000_read_phy_reg(hw,
2815                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2816                         if (ret_val)
2817                                 return ret_val;
2818
2819                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2820                         ret_val = e1000_write_phy_reg(hw,
2821                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2822
2823                         if (ret_val)
2824                                 return ret_val;
2825                 }
2826
2827                 /* Workaround: Disable padding in Kumeran interface in the MAC
2828                  * and in the PHY to avoid CRC errors.
2829                  */
2830                 ret_val = e1000_read_phy_reg(hw,
2831                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2832                 if (ret_val)
2833                         return ret_val;
2834                 phy_data |= GG82563_ICR_DIS_PADDING;
2835                 ret_val = e1000_write_phy_reg(hw,
2836                                 GG82563_PHY_INBAND_CTRL, phy_data);
2837                 if (ret_val)
2838                         return ret_val;
2839         }
2840         return E1000_SUCCESS;
2841 }
2842
2843 /********************************************************************
2844 * Copper link setup for e1000_phy_m88 series.
2845 *
2846 * hw - Struct containing variables accessed by shared code
2847 *********************************************************************/
2848 static int32_t
2849 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2850 {
2851         int32_t ret_val;
2852         uint16_t phy_data;
2853
2854         DEBUGFUNC();
2855
2856         if (hw->phy_reset_disable)
2857                 return E1000_SUCCESS;
2858
2859         /* Enable CRS on TX. This must be set for half-duplex operation. */
2860         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2861         if (ret_val)
2862                 return ret_val;
2863
2864         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2865
2866         /* Options:
2867          *   MDI/MDI-X = 0 (default)
2868          *   0 - Auto for all speeds
2869          *   1 - MDI mode
2870          *   2 - MDI-X mode
2871          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2872          */
2873         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2874
2875         switch (hw->mdix) {
2876         case 1:
2877                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2878                 break;
2879         case 2:
2880                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2881                 break;
2882         case 3:
2883                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2884                 break;
2885         case 0:
2886         default:
2887                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2888                 break;
2889         }
2890
2891         /* Options:
2892          *   disable_polarity_correction = 0 (default)
2893          *       Automatic Correction for Reversed Cable Polarity
2894          *   0 - Disabled
2895          *   1 - Enabled
2896          */
2897         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2898         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2899         if (ret_val)
2900                 return ret_val;
2901
2902         if (hw->phy_revision < M88E1011_I_REV_4) {
2903                 /* Force TX_CLK in the Extended PHY Specific Control Register
2904                  * to 25MHz clock.
2905                  */
2906                 ret_val = e1000_read_phy_reg(hw,
2907                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2908                 if (ret_val)
2909                         return ret_val;
2910
2911                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2912
2913                 if ((hw->phy_revision == E1000_REVISION_2) &&
2914                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2915                         /* Vidalia Phy, set the downshift counter to 5x */
2916                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2917                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2918                         ret_val = e1000_write_phy_reg(hw,
2919                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2920                         if (ret_val)
2921                                 return ret_val;
2922                 } else {
2923                         /* Configure Master and Slave downshift values */
2924                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2925                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2926                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2927                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2928                         ret_val = e1000_write_phy_reg(hw,
2929                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2930                         if (ret_val)
2931                                 return ret_val;
2932                 }
2933         }
2934
2935         /* SW Reset the PHY so all changes take effect */
2936         ret_val = e1000_phy_reset(hw);
2937         if (ret_val) {
2938                 DEBUGOUT("Error Resetting the PHY\n");
2939                 return ret_val;
2940         }
2941
2942         return E1000_SUCCESS;
2943 }
2944
2945 /********************************************************************
2946 * Setup auto-negotiation and flow control advertisements,
2947 * and then perform auto-negotiation.
2948 *
2949 * hw - Struct containing variables accessed by shared code
2950 *********************************************************************/
2951 static int32_t
2952 e1000_copper_link_autoneg(struct e1000_hw *hw)
2953 {
2954         int32_t ret_val;
2955         uint16_t phy_data;
2956
2957         DEBUGFUNC();
2958
2959         /* Perform some bounds checking on the hw->autoneg_advertised
2960          * parameter.  If this variable is zero, then set it to the default.
2961          */
2962         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2963
2964         /* If autoneg_advertised is zero, we assume it was not defaulted
2965          * by the calling code so we set to advertise full capability.
2966          */
2967         if (hw->autoneg_advertised == 0)
2968                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2969
2970         /* IFE phy only supports 10/100 */
2971         if (hw->phy_type == e1000_phy_ife)
2972                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2973
2974         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2975         ret_val = e1000_phy_setup_autoneg(hw);
2976         if (ret_val) {
2977                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2978                 return ret_val;
2979         }
2980         DEBUGOUT("Restarting Auto-Neg\n");
2981
2982         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2983          * the Auto Neg Restart bit in the PHY control register.
2984          */
2985         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2986         if (ret_val)
2987                 return ret_val;
2988
2989         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2990         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2991         if (ret_val)
2992                 return ret_val;
2993
2994         /* Does the user want to wait for Auto-Neg to complete here, or
2995          * check at a later time (for example, callback routine).
2996          */
2997         /* If we do not wait for autonegtation to complete I
2998          * do not see a valid link status.
2999          * wait_autoneg_complete = 1 .
3000          */
3001         if (hw->wait_autoneg_complete) {
3002                 ret_val = e1000_wait_autoneg(hw);
3003                 if (ret_val) {
3004                         DEBUGOUT("Error while waiting for autoneg"
3005                                         "to complete\n");
3006                         return ret_val;
3007                 }
3008         }
3009
3010         hw->get_link_status = true;
3011
3012         return E1000_SUCCESS;
3013 }
3014
3015 /******************************************************************************
3016 * Config the MAC and the PHY after link is up.
3017 *   1) Set up the MAC to the current PHY speed/duplex
3018 *      if we are on 82543.  If we
3019 *      are on newer silicon, we only need to configure
3020 *      collision distance in the Transmit Control Register.
3021 *   2) Set up flow control on the MAC to that established with
3022 *      the link partner.
3023 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3024 *
3025 * hw - Struct containing variables accessed by shared code
3026 ******************************************************************************/
3027 static int32_t
3028 e1000_copper_link_postconfig(struct e1000_hw *hw)
3029 {
3030         int32_t ret_val;
3031         DEBUGFUNC();
3032
3033         if (hw->mac_type >= e1000_82544) {
3034                 e1000_config_collision_dist(hw);
3035         } else {
3036                 ret_val = e1000_config_mac_to_phy(hw);
3037                 if (ret_val) {
3038                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3039                         return ret_val;
3040                 }
3041         }
3042         ret_val = e1000_config_fc_after_link_up(hw);
3043         if (ret_val) {
3044                 DEBUGOUT("Error Configuring Flow Control\n");
3045                 return ret_val;
3046         }
3047         return E1000_SUCCESS;
3048 }
3049
3050 /******************************************************************************
3051 * Detects which PHY is present and setup the speed and duplex
3052 *
3053 * hw - Struct containing variables accessed by shared code
3054 ******************************************************************************/
3055 static int
3056 e1000_setup_copper_link(struct eth_device *nic)
3057 {
3058         struct e1000_hw *hw = nic->priv;
3059         int32_t ret_val;
3060         uint16_t i;
3061         uint16_t phy_data;
3062         uint16_t reg_data;
3063
3064         DEBUGFUNC();
3065
3066         switch (hw->mac_type) {
3067         case e1000_80003es2lan:
3068         case e1000_ich8lan:
3069                 /* Set the mac to wait the maximum time between each
3070                  * iteration and increase the max iterations when
3071                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3072                 ret_val = e1000_write_kmrn_reg(hw,
3073                                 GG82563_REG(0x34, 4), 0xFFFF);
3074                 if (ret_val)
3075                         return ret_val;
3076                 ret_val = e1000_read_kmrn_reg(hw,
3077                                 GG82563_REG(0x34, 9), &reg_data);
3078                 if (ret_val)
3079                         return ret_val;
3080                 reg_data |= 0x3F;
3081                 ret_val = e1000_write_kmrn_reg(hw,
3082                                 GG82563_REG(0x34, 9), reg_data);
3083                 if (ret_val)
3084                         return ret_val;
3085         default:
3086                 break;
3087         }
3088
3089         /* Check if it is a valid PHY and set PHY mode if necessary. */
3090         ret_val = e1000_copper_link_preconfig(hw);
3091         if (ret_val)
3092                 return ret_val;
3093         switch (hw->mac_type) {
3094         case e1000_80003es2lan:
3095                 /* Kumeran registers are written-only */
3096                 reg_data =
3097                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3098                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3099                 ret_val = e1000_write_kmrn_reg(hw,
3100                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3101                 if (ret_val)
3102                         return ret_val;
3103                 break;
3104         default:
3105                 break;
3106         }
3107
3108         if (hw->phy_type == e1000_phy_igp ||
3109                 hw->phy_type == e1000_phy_igp_3 ||
3110                 hw->phy_type == e1000_phy_igp_2) {
3111                 ret_val = e1000_copper_link_igp_setup(hw);
3112                 if (ret_val)
3113                         return ret_val;
3114         } else if (hw->phy_type == e1000_phy_m88 ||
3115                 hw->phy_type == e1000_phy_igb) {
3116                 ret_val = e1000_copper_link_mgp_setup(hw);
3117                 if (ret_val)
3118                         return ret_val;
3119         } else if (hw->phy_type == e1000_phy_gg82563) {
3120                 ret_val = e1000_copper_link_ggp_setup(hw);
3121                 if (ret_val)
3122                         return ret_val;
3123         }
3124
3125         /* always auto */
3126         /* Setup autoneg and flow control advertisement
3127           * and perform autonegotiation */
3128         ret_val = e1000_copper_link_autoneg(hw);
3129         if (ret_val)
3130                 return ret_val;
3131
3132         /* Check link status. Wait up to 100 microseconds for link to become
3133          * valid.
3134          */
3135         for (i = 0; i < 10; i++) {
3136                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3137                 if (ret_val)
3138                         return ret_val;
3139                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3140                 if (ret_val)
3141                         return ret_val;
3142
3143                 if (phy_data & MII_SR_LINK_STATUS) {
3144                         /* Config the MAC and PHY after link is up */
3145                         ret_val = e1000_copper_link_postconfig(hw);
3146                         if (ret_val)
3147                                 return ret_val;
3148
3149                         DEBUGOUT("Valid link established!!!\n");
3150                         return E1000_SUCCESS;
3151                 }
3152                 udelay(10);
3153         }
3154
3155         DEBUGOUT("Unable to establish link!!!\n");
3156         return E1000_SUCCESS;
3157 }
3158
3159 /******************************************************************************
3160 * Configures PHY autoneg and flow control advertisement settings
3161 *
3162 * hw - Struct containing variables accessed by shared code
3163 ******************************************************************************/
3164 int32_t
3165 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3166 {
3167         int32_t ret_val;
3168         uint16_t mii_autoneg_adv_reg;
3169         uint16_t mii_1000t_ctrl_reg;
3170
3171         DEBUGFUNC();
3172
3173         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3174         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3175         if (ret_val)
3176                 return ret_val;
3177
3178         if (hw->phy_type != e1000_phy_ife) {
3179                 /* Read the MII 1000Base-T Control Register (Address 9). */
3180                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3181                                 &mii_1000t_ctrl_reg);
3182                 if (ret_val)
3183                         return ret_val;
3184         } else
3185                 mii_1000t_ctrl_reg = 0;
3186
3187         /* Need to parse both autoneg_advertised and fc and set up
3188          * the appropriate PHY registers.  First we will parse for
3189          * autoneg_advertised software override.  Since we can advertise
3190          * a plethora of combinations, we need to check each bit
3191          * individually.
3192          */
3193
3194         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3195          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3196          * the  1000Base-T Control Register (Address 9).
3197          */
3198         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3199         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3200
3201         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3202
3203         /* Do we want to advertise 10 Mb Half Duplex? */
3204         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3205                 DEBUGOUT("Advertise 10mb Half duplex\n");
3206                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3207         }
3208
3209         /* Do we want to advertise 10 Mb Full Duplex? */
3210         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3211                 DEBUGOUT("Advertise 10mb Full duplex\n");
3212                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3213         }
3214
3215         /* Do we want to advertise 100 Mb Half Duplex? */
3216         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3217                 DEBUGOUT("Advertise 100mb Half duplex\n");
3218                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3219         }
3220
3221         /* Do we want to advertise 100 Mb Full Duplex? */
3222         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3223                 DEBUGOUT("Advertise 100mb Full duplex\n");
3224                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3225         }
3226
3227         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3228         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3229                 DEBUGOUT
3230                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3231         }
3232
3233         /* Do we want to advertise 1000 Mb Full Duplex? */
3234         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3235                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3236                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3237         }
3238
3239         /* Check for a software override of the flow control settings, and
3240          * setup the PHY advertisement registers accordingly.  If
3241          * auto-negotiation is enabled, then software will have to set the
3242          * "PAUSE" bits to the correct value in the Auto-Negotiation
3243          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3244          *
3245          * The possible values of the "fc" parameter are:
3246          *      0:  Flow control is completely disabled
3247          *      1:  Rx flow control is enabled (we can receive pause frames
3248          *          but not send pause frames).
3249          *      2:  Tx flow control is enabled (we can send pause frames
3250          *          but we do not support receiving pause frames).
3251          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3252          *  other:  No software override.  The flow control configuration
3253          *          in the EEPROM is used.
3254          */
3255         switch (hw->fc) {
3256         case e1000_fc_none:     /* 0 */
3257                 /* Flow control (RX & TX) is completely disabled by a
3258                  * software over-ride.
3259                  */
3260                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3261                 break;
3262         case e1000_fc_rx_pause: /* 1 */
3263                 /* RX Flow control is enabled, and TX Flow control is
3264                  * disabled, by a software over-ride.
3265                  */
3266                 /* Since there really isn't a way to advertise that we are
3267                  * capable of RX Pause ONLY, we will advertise that we
3268                  * support both symmetric and asymmetric RX PAUSE.  Later
3269                  * (in e1000_config_fc_after_link_up) we will disable the
3270                  *hw's ability to send PAUSE frames.
3271                  */
3272                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3273                 break;
3274         case e1000_fc_tx_pause: /* 2 */
3275                 /* TX Flow control is enabled, and RX Flow control is
3276                  * disabled, by a software over-ride.
3277                  */
3278                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3279                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3280                 break;
3281         case e1000_fc_full:     /* 3 */
3282                 /* Flow control (both RX and TX) is enabled by a software
3283                  * over-ride.
3284                  */
3285                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3286                 break;
3287         default:
3288                 DEBUGOUT("Flow control param set incorrectly\n");
3289                 return -E1000_ERR_CONFIG;
3290         }
3291
3292         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3293         if (ret_val)
3294                 return ret_val;
3295
3296         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3297
3298         if (hw->phy_type != e1000_phy_ife) {
3299                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3300                                 mii_1000t_ctrl_reg);
3301                 if (ret_val)
3302                         return ret_val;
3303         }
3304
3305         return E1000_SUCCESS;
3306 }
3307
3308 /******************************************************************************
3309 * Sets the collision distance in the Transmit Control register
3310 *
3311 * hw - Struct containing variables accessed by shared code
3312 *
3313 * Link should have been established previously. Reads the speed and duplex
3314 * information from the Device Status register.
3315 ******************************************************************************/
3316 static void
3317 e1000_config_collision_dist(struct e1000_hw *hw)
3318 {
3319         uint32_t tctl, coll_dist;
3320
3321         DEBUGFUNC();
3322
3323         if (hw->mac_type < e1000_82543)
3324                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3325         else
3326                 coll_dist = E1000_COLLISION_DISTANCE;
3327
3328         tctl = E1000_READ_REG(hw, TCTL);
3329
3330         tctl &= ~E1000_TCTL_COLD;
3331         tctl |= coll_dist << E1000_COLD_SHIFT;
3332
3333         E1000_WRITE_REG(hw, TCTL, tctl);
3334         E1000_WRITE_FLUSH(hw);
3335 }
3336
3337 /******************************************************************************
3338 * Sets MAC speed and duplex settings to reflect the those in the PHY
3339 *
3340 * hw - Struct containing variables accessed by shared code
3341 * mii_reg - data to write to the MII control register
3342 *
3343 * The contents of the PHY register containing the needed information need to
3344 * be passed in.
3345 ******************************************************************************/
3346 static int
3347 e1000_config_mac_to_phy(struct e1000_hw *hw)
3348 {
3349         uint32_t ctrl;
3350         uint16_t phy_data;
3351
3352         DEBUGFUNC();
3353
3354         /* Read the Device Control Register and set the bits to Force Speed
3355          * and Duplex.
3356          */
3357         ctrl = E1000_READ_REG(hw, CTRL);
3358         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3359         ctrl &= ~(E1000_CTRL_ILOS);
3360         ctrl |= (E1000_CTRL_SPD_SEL);
3361
3362         /* Set up duplex in the Device Control and Transmit Control
3363          * registers depending on negotiated values.
3364          */
3365         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3366                 DEBUGOUT("PHY Read Error\n");
3367                 return -E1000_ERR_PHY;
3368         }
3369         if (phy_data & M88E1000_PSSR_DPLX)
3370                 ctrl |= E1000_CTRL_FD;
3371         else
3372                 ctrl &= ~E1000_CTRL_FD;
3373
3374         e1000_config_collision_dist(hw);
3375
3376         /* Set up speed in the Device Control register depending on
3377          * negotiated values.
3378          */
3379         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3380                 ctrl |= E1000_CTRL_SPD_1000;
3381         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3382                 ctrl |= E1000_CTRL_SPD_100;
3383         /* Write the configured values back to the Device Control Reg. */
3384         E1000_WRITE_REG(hw, CTRL, ctrl);
3385         return 0;
3386 }
3387
3388 /******************************************************************************
3389  * Forces the MAC's flow control settings.
3390  *
3391  * hw - Struct containing variables accessed by shared code
3392  *
3393  * Sets the TFCE and RFCE bits in the device control register to reflect
3394  * the adapter settings. TFCE and RFCE need to be explicitly set by
3395  * software when a Copper PHY is used because autonegotiation is managed
3396  * by the PHY rather than the MAC. Software must also configure these
3397  * bits when link is forced on a fiber connection.
3398  *****************************************************************************/
3399 static int
3400 e1000_force_mac_fc(struct e1000_hw *hw)
3401 {
3402         uint32_t ctrl;
3403
3404         DEBUGFUNC();
3405
3406         /* Get the current configuration of the Device Control Register */
3407         ctrl = E1000_READ_REG(hw, CTRL);
3408
3409         /* Because we didn't get link via the internal auto-negotiation
3410          * mechanism (we either forced link or we got link via PHY
3411          * auto-neg), we have to manually enable/disable transmit an
3412          * receive flow control.
3413          *
3414          * The "Case" statement below enables/disable flow control
3415          * according to the "hw->fc" parameter.
3416          *
3417          * The possible values of the "fc" parameter are:
3418          *      0:  Flow control is completely disabled
3419          *      1:  Rx flow control is enabled (we can receive pause
3420          *          frames but not send pause frames).
3421          *      2:  Tx flow control is enabled (we can send pause frames
3422          *          frames but we do not receive pause frames).
3423          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3424          *  other:  No other values should be possible at this point.
3425          */
3426
3427         switch (hw->fc) {
3428         case e1000_fc_none:
3429                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3430                 break;
3431         case e1000_fc_rx_pause:
3432                 ctrl &= (~E1000_CTRL_TFCE);
3433                 ctrl |= E1000_CTRL_RFCE;
3434                 break;
3435         case e1000_fc_tx_pause:
3436                 ctrl &= (~E1000_CTRL_RFCE);
3437                 ctrl |= E1000_CTRL_TFCE;
3438                 break;
3439         case e1000_fc_full:
3440                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3441                 break;
3442         default:
3443                 DEBUGOUT("Flow control param set incorrectly\n");
3444                 return -E1000_ERR_CONFIG;
3445         }
3446
3447         /* Disable TX Flow Control for 82542 (rev 2.0) */
3448         if (hw->mac_type == e1000_82542_rev2_0)
3449                 ctrl &= (~E1000_CTRL_TFCE);
3450
3451         E1000_WRITE_REG(hw, CTRL, ctrl);
3452         return 0;
3453 }
3454
3455 /******************************************************************************
3456  * Configures flow control settings after link is established
3457  *
3458  * hw - Struct containing variables accessed by shared code
3459  *
3460  * Should be called immediately after a valid link has been established.
3461  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3462  * and autonegotiation is enabled, the MAC flow control settings will be set
3463  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3464  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3465  *****************************************************************************/
3466 static int32_t
3467 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3468 {
3469         int32_t ret_val;
3470         uint16_t mii_status_reg;
3471         uint16_t mii_nway_adv_reg;
3472         uint16_t mii_nway_lp_ability_reg;
3473         uint16_t speed;
3474         uint16_t duplex;
3475
3476         DEBUGFUNC();
3477
3478         /* Check for the case where we have fiber media and auto-neg failed
3479          * so we had to force link.  In this case, we need to force the
3480          * configuration of the MAC to match the "fc" parameter.
3481          */
3482         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3483                 || ((hw->media_type == e1000_media_type_internal_serdes)
3484                 && (hw->autoneg_failed))
3485                 || ((hw->media_type == e1000_media_type_copper)
3486                 && (!hw->autoneg))) {
3487                 ret_val = e1000_force_mac_fc(hw);
3488                 if (ret_val < 0) {
3489                         DEBUGOUT("Error forcing flow control settings\n");
3490                         return ret_val;
3491                 }
3492         }
3493
3494         /* Check for the case where we have copper media and auto-neg is
3495          * enabled.  In this case, we need to check and see if Auto-Neg
3496          * has completed, and if so, how the PHY and link partner has
3497          * flow control configured.
3498          */
3499         if (hw->media_type == e1000_media_type_copper) {
3500                 /* Read the MII Status Register and check to see if AutoNeg
3501                  * has completed.  We read this twice because this reg has
3502                  * some "sticky" (latched) bits.
3503                  */
3504                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3505                         DEBUGOUT("PHY Read Error\n");
3506                         return -E1000_ERR_PHY;
3507                 }
3508                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3509                         DEBUGOUT("PHY Read Error\n");
3510                         return -E1000_ERR_PHY;
3511                 }
3512
3513                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3514                         /* The AutoNeg process has completed, so we now need to
3515                          * read both the Auto Negotiation Advertisement Register
3516                          * (Address 4) and the Auto_Negotiation Base Page Ability
3517                          * Register (Address 5) to determine how flow control was
3518                          * negotiated.
3519                          */
3520                         if (e1000_read_phy_reg
3521                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3522                                 DEBUGOUT("PHY Read Error\n");
3523                                 return -E1000_ERR_PHY;
3524                         }
3525                         if (e1000_read_phy_reg
3526                             (hw, PHY_LP_ABILITY,
3527                              &mii_nway_lp_ability_reg) < 0) {
3528                                 DEBUGOUT("PHY Read Error\n");
3529                                 return -E1000_ERR_PHY;
3530                         }
3531
3532                         /* Two bits in the Auto Negotiation Advertisement Register
3533                          * (Address 4) and two bits in the Auto Negotiation Base
3534                          * Page Ability Register (Address 5) determine flow control
3535                          * for both the PHY and the link partner.  The following
3536                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3537                          * 1999, describes these PAUSE resolution bits and how flow
3538                          * control is determined based upon these settings.
3539                          * NOTE:  DC = Don't Care
3540                          *
3541                          *   LOCAL DEVICE  |   LINK PARTNER
3542                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3543                          *-------|---------|-------|---------|--------------------
3544                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3545                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3546                          *   0   |    1    |   1   |    0    | e1000_fc_none
3547                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3548                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3549                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3550                          *   1   |    1    |   0   |    0    | e1000_fc_none
3551                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3552                          *
3553                          */
3554                         /* Are both PAUSE bits set to 1?  If so, this implies
3555                          * Symmetric Flow Control is enabled at both ends.  The
3556                          * ASM_DIR bits are irrelevant per the spec.
3557                          *
3558                          * For Symmetric Flow Control:
3559                          *
3560                          *   LOCAL DEVICE  |   LINK PARTNER
3561                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3562                          *-------|---------|-------|---------|--------------------
3563                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3564                          *
3565                          */
3566                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3567                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3568                                 /* Now we need to check if the user selected RX ONLY
3569                                  * of pause frames.  In this case, we had to advertise
3570                                  * FULL flow control because we could not advertise RX
3571                                  * ONLY. Hence, we must now check to see if we need to
3572                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3573                                  */
3574                                 if (hw->original_fc == e1000_fc_full) {
3575                                         hw->fc = e1000_fc_full;
3576                                         DEBUGOUT("Flow Control = FULL.\r\n");
3577                                 } else {
3578                                         hw->fc = e1000_fc_rx_pause;
3579                                         DEBUGOUT
3580                                             ("Flow Control = RX PAUSE frames only.\r\n");
3581                                 }
3582                         }
3583                         /* For receiving PAUSE frames ONLY.
3584                          *
3585                          *   LOCAL DEVICE  |   LINK PARTNER
3586                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3587                          *-------|---------|-------|---------|--------------------
3588                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3589                          *
3590                          */
3591                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3592                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3593                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3594                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3595                         {
3596                                 hw->fc = e1000_fc_tx_pause;
3597                                 DEBUGOUT
3598                                     ("Flow Control = TX PAUSE frames only.\r\n");
3599                         }
3600                         /* For transmitting PAUSE frames ONLY.
3601                          *
3602                          *   LOCAL DEVICE  |   LINK PARTNER
3603                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3604                          *-------|---------|-------|---------|--------------------
3605                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3606                          *
3607                          */
3608                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3609                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3610                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3611                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3612                         {
3613                                 hw->fc = e1000_fc_rx_pause;
3614                                 DEBUGOUT
3615                                     ("Flow Control = RX PAUSE frames only.\r\n");
3616                         }
3617                         /* Per the IEEE spec, at this point flow control should be
3618                          * disabled.  However, we want to consider that we could
3619                          * be connected to a legacy switch that doesn't advertise
3620                          * desired flow control, but can be forced on the link
3621                          * partner.  So if we advertised no flow control, that is
3622                          * what we will resolve to.  If we advertised some kind of
3623                          * receive capability (Rx Pause Only or Full Flow Control)
3624                          * and the link partner advertised none, we will configure
3625                          * ourselves to enable Rx Flow Control only.  We can do
3626                          * this safely for two reasons:  If the link partner really
3627                          * didn't want flow control enabled, and we enable Rx, no
3628                          * harm done since we won't be receiving any PAUSE frames
3629                          * anyway.  If the intent on the link partner was to have
3630                          * flow control enabled, then by us enabling RX only, we
3631                          * can at least receive pause frames and process them.
3632                          * This is a good idea because in most cases, since we are
3633                          * predominantly a server NIC, more times than not we will
3634                          * be asked to delay transmission of packets than asking
3635                          * our link partner to pause transmission of frames.
3636                          */
3637                         else if (hw->original_fc == e1000_fc_none ||
3638                                  hw->original_fc == e1000_fc_tx_pause) {
3639                                 hw->fc = e1000_fc_none;
3640                                 DEBUGOUT("Flow Control = NONE.\r\n");
3641                         } else {
3642                                 hw->fc = e1000_fc_rx_pause;
3643                                 DEBUGOUT
3644                                     ("Flow Control = RX PAUSE frames only.\r\n");
3645                         }
3646
3647                         /* Now we need to do one last check...  If we auto-
3648                          * negotiated to HALF DUPLEX, flow control should not be
3649                          * enabled per IEEE 802.3 spec.
3650                          */
3651                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3652
3653                         if (duplex == HALF_DUPLEX)
3654                                 hw->fc = e1000_fc_none;
3655
3656                         /* Now we call a subroutine to actually force the MAC
3657                          * controller to use the correct flow control settings.
3658                          */
3659                         ret_val = e1000_force_mac_fc(hw);
3660                         if (ret_val < 0) {
3661                                 DEBUGOUT
3662                                     ("Error forcing flow control settings\n");
3663                                 return ret_val;
3664                         }
3665                 } else {
3666                         DEBUGOUT
3667                             ("Copper PHY and Auto Neg has not completed.\r\n");
3668                 }
3669         }
3670         return E1000_SUCCESS;
3671 }
3672
3673 /******************************************************************************
3674  * Checks to see if the link status of the hardware has changed.
3675  *
3676  * hw - Struct containing variables accessed by shared code
3677  *
3678  * Called by any function that needs to check the link status of the adapter.
3679  *****************************************************************************/
3680 static int
3681 e1000_check_for_link(struct eth_device *nic)
3682 {
3683         struct e1000_hw *hw = nic->priv;
3684         uint32_t rxcw;
3685         uint32_t ctrl;
3686         uint32_t status;
3687         uint32_t rctl;
3688         uint32_t signal;
3689         int32_t ret_val;
3690         uint16_t phy_data;
3691         uint16_t lp_capability;
3692
3693         DEBUGFUNC();
3694
3695         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3696          * set when the optics detect a signal. On older adapters, it will be
3697          * cleared when there is a signal
3698          */
3699         ctrl = E1000_READ_REG(hw, CTRL);
3700         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3701                 signal = E1000_CTRL_SWDPIN1;
3702         else
3703                 signal = 0;
3704
3705         status = E1000_READ_REG(hw, STATUS);
3706         rxcw = E1000_READ_REG(hw, RXCW);
3707         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3708
3709         /* If we have a copper PHY then we only want to go out to the PHY
3710          * registers to see if Auto-Neg has completed and/or if our link
3711          * status has changed.  The get_link_status flag will be set if we
3712          * receive a Link Status Change interrupt or we have Rx Sequence
3713          * Errors.
3714          */
3715         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3716                 /* First we want to see if the MII Status Register reports
3717                  * link.  If so, then we want to get the current speed/duplex
3718                  * of the PHY.
3719                  * Read the register twice since the link bit is sticky.
3720                  */
3721                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3722                         DEBUGOUT("PHY Read Error\n");
3723                         return -E1000_ERR_PHY;
3724                 }
3725                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3726                         DEBUGOUT("PHY Read Error\n");
3727                         return -E1000_ERR_PHY;
3728                 }
3729
3730                 if (phy_data & MII_SR_LINK_STATUS) {
3731                         hw->get_link_status = false;
3732                 } else {
3733                         /* No link detected */
3734                         return -E1000_ERR_NOLINK;
3735                 }
3736
3737                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3738                  * have Si on board that is 82544 or newer, Auto
3739                  * Speed Detection takes care of MAC speed/duplex
3740                  * configuration.  So we only need to configure Collision
3741                  * Distance in the MAC.  Otherwise, we need to force
3742                  * speed/duplex on the MAC to the current PHY speed/duplex
3743                  * settings.
3744                  */
3745                 if (hw->mac_type >= e1000_82544)
3746                         e1000_config_collision_dist(hw);
3747                 else {
3748                         ret_val = e1000_config_mac_to_phy(hw);
3749                         if (ret_val < 0) {
3750                                 DEBUGOUT
3751                                     ("Error configuring MAC to PHY settings\n");
3752                                 return ret_val;
3753                         }
3754                 }
3755
3756                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3757                  * need to restore the desired flow control settings because we may
3758                  * have had to re-autoneg with a different link partner.
3759                  */
3760                 ret_val = e1000_config_fc_after_link_up(hw);
3761                 if (ret_val < 0) {
3762                         DEBUGOUT("Error configuring flow control\n");
3763                         return ret_val;
3764                 }
3765
3766                 /* At this point we know that we are on copper and we have
3767                  * auto-negotiated link.  These are conditions for checking the link
3768                  * parter capability register.  We use the link partner capability to
3769                  * determine if TBI Compatibility needs to be turned on or off.  If
3770                  * the link partner advertises any speed in addition to Gigabit, then
3771                  * we assume that they are GMII-based, and TBI compatibility is not
3772                  * needed. If no other speeds are advertised, we assume the link
3773                  * partner is TBI-based, and we turn on TBI Compatibility.
3774                  */
3775                 if (hw->tbi_compatibility_en) {
3776                         if (e1000_read_phy_reg
3777                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3778                                 DEBUGOUT("PHY Read Error\n");
3779                                 return -E1000_ERR_PHY;
3780                         }
3781                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3782                                              NWAY_LPAR_10T_FD_CAPS |
3783                                              NWAY_LPAR_100TX_HD_CAPS |
3784                                              NWAY_LPAR_100TX_FD_CAPS |
3785                                              NWAY_LPAR_100T4_CAPS)) {
3786                                 /* If our link partner advertises anything in addition to
3787                                  * gigabit, we do not need to enable TBI compatibility.
3788                                  */
3789                                 if (hw->tbi_compatibility_on) {
3790                                         /* If we previously were in the mode, turn it off. */
3791                                         rctl = E1000_READ_REG(hw, RCTL);
3792                                         rctl &= ~E1000_RCTL_SBP;
3793                                         E1000_WRITE_REG(hw, RCTL, rctl);
3794                                         hw->tbi_compatibility_on = false;
3795                                 }
3796                         } else {
3797                                 /* If TBI compatibility is was previously off, turn it on. For
3798                                  * compatibility with a TBI link partner, we will store bad
3799                                  * packets. Some frames have an additional byte on the end and
3800                                  * will look like CRC errors to to the hardware.
3801                                  */
3802                                 if (!hw->tbi_compatibility_on) {
3803                                         hw->tbi_compatibility_on = true;
3804                                         rctl = E1000_READ_REG(hw, RCTL);
3805                                         rctl |= E1000_RCTL_SBP;
3806                                         E1000_WRITE_REG(hw, RCTL, rctl);
3807                                 }
3808                         }
3809                 }
3810         }
3811         /* If we don't have link (auto-negotiation failed or link partner cannot
3812          * auto-negotiate), the cable is plugged in (we have signal), and our
3813          * link partner is not trying to auto-negotiate with us (we are receiving
3814          * idles or data), we need to force link up. We also need to give
3815          * auto-negotiation time to complete, in case the cable was just plugged
3816          * in. The autoneg_failed flag does this.
3817          */
3818         else if ((hw->media_type == e1000_media_type_fiber) &&
3819                  (!(status & E1000_STATUS_LU)) &&
3820                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3821                  (!(rxcw & E1000_RXCW_C))) {
3822                 if (hw->autoneg_failed == 0) {
3823                         hw->autoneg_failed = 1;
3824                         return 0;
3825                 }
3826                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3827
3828                 /* Disable auto-negotiation in the TXCW register */
3829                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3830
3831                 /* Force link-up and also force full-duplex. */
3832                 ctrl = E1000_READ_REG(hw, CTRL);
3833                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3834                 E1000_WRITE_REG(hw, CTRL, ctrl);
3835
3836                 /* Configure Flow Control after forcing link up. */
3837                 ret_val = e1000_config_fc_after_link_up(hw);
3838                 if (ret_val < 0) {
3839                         DEBUGOUT("Error configuring flow control\n");
3840                         return ret_val;
3841                 }
3842         }
3843         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3844          * auto-negotiation in the TXCW register and disable forced link in the
3845          * Device Control register in an attempt to auto-negotiate with our link
3846          * partner.
3847          */
3848         else if ((hw->media_type == e1000_media_type_fiber) &&
3849                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3850                 DEBUGOUT
3851                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3852                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3853                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3854         }
3855         return 0;
3856 }
3857
3858 /******************************************************************************
3859 * Configure the MAC-to-PHY interface for 10/100Mbps
3860 *
3861 * hw - Struct containing variables accessed by shared code
3862 ******************************************************************************/
3863 static int32_t
3864 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3865 {
3866         int32_t ret_val = E1000_SUCCESS;
3867         uint32_t tipg;
3868         uint16_t reg_data;
3869
3870         DEBUGFUNC();
3871
3872         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3873         ret_val = e1000_write_kmrn_reg(hw,
3874                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3875         if (ret_val)
3876                 return ret_val;
3877
3878         /* Configure Transmit Inter-Packet Gap */
3879         tipg = E1000_READ_REG(hw, TIPG);
3880         tipg &= ~E1000_TIPG_IPGT_MASK;
3881         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3882         E1000_WRITE_REG(hw, TIPG, tipg);
3883
3884         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3885
3886         if (ret_val)
3887                 return ret_val;
3888
3889         if (duplex == HALF_DUPLEX)
3890                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3891         else
3892                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3893
3894         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3895
3896         return ret_val;
3897 }
3898
3899 static int32_t
3900 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3901 {
3902         int32_t ret_val = E1000_SUCCESS;
3903         uint16_t reg_data;
3904         uint32_t tipg;
3905
3906         DEBUGFUNC();
3907
3908         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3909         ret_val = e1000_write_kmrn_reg(hw,
3910                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3911         if (ret_val)
3912                 return ret_val;
3913
3914         /* Configure Transmit Inter-Packet Gap */
3915         tipg = E1000_READ_REG(hw, TIPG);
3916         tipg &= ~E1000_TIPG_IPGT_MASK;
3917         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3918         E1000_WRITE_REG(hw, TIPG, tipg);
3919
3920         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3921
3922         if (ret_val)
3923                 return ret_val;
3924
3925         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3926         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3927
3928         return ret_val;
3929 }
3930
3931 /******************************************************************************
3932  * Detects the current speed and duplex settings of the hardware.
3933  *
3934  * hw - Struct containing variables accessed by shared code
3935  * speed - Speed of the connection
3936  * duplex - Duplex setting of the connection
3937  *****************************************************************************/
3938 static int
3939 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3940                 uint16_t *duplex)
3941 {
3942         uint32_t status;
3943         int32_t ret_val;
3944         uint16_t phy_data;
3945
3946         DEBUGFUNC();
3947
3948         if (hw->mac_type >= e1000_82543) {
3949                 status = E1000_READ_REG(hw, STATUS);
3950                 if (status & E1000_STATUS_SPEED_1000) {
3951                         *speed = SPEED_1000;
3952                         DEBUGOUT("1000 Mbs, ");
3953                 } else if (status & E1000_STATUS_SPEED_100) {
3954                         *speed = SPEED_100;
3955                         DEBUGOUT("100 Mbs, ");
3956                 } else {
3957                         *speed = SPEED_10;
3958                         DEBUGOUT("10 Mbs, ");
3959                 }
3960
3961                 if (status & E1000_STATUS_FD) {
3962                         *duplex = FULL_DUPLEX;
3963                         DEBUGOUT("Full Duplex\r\n");
3964                 } else {
3965                         *duplex = HALF_DUPLEX;
3966                         DEBUGOUT(" Half Duplex\r\n");
3967                 }
3968         } else {
3969                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3970                 *speed = SPEED_1000;
3971                 *duplex = FULL_DUPLEX;
3972         }
3973
3974         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3975          * even if it is operating at half duplex.  Here we set the duplex
3976          * settings to match the duplex in the link partner's capabilities.
3977          */
3978         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3979                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3980                 if (ret_val)
3981                         return ret_val;
3982
3983                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3984                         *duplex = HALF_DUPLEX;
3985                 else {
3986                         ret_val = e1000_read_phy_reg(hw,
3987                                         PHY_LP_ABILITY, &phy_data);
3988                         if (ret_val)
3989                                 return ret_val;
3990                         if ((*speed == SPEED_100 &&
3991                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3992                                 || (*speed == SPEED_10
3993                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3994                                 *duplex = HALF_DUPLEX;
3995                 }
3996         }
3997
3998         if ((hw->mac_type == e1000_80003es2lan) &&
3999                 (hw->media_type == e1000_media_type_copper)) {
4000                 if (*speed == SPEED_1000)
4001                         ret_val = e1000_configure_kmrn_for_1000(hw);
4002                 else
4003                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4004                 if (ret_val)
4005                         return ret_val;
4006         }
4007         return E1000_SUCCESS;
4008 }
4009
4010 /******************************************************************************
4011 * Blocks until autoneg completes or times out (~4.5 seconds)
4012 *
4013 * hw - Struct containing variables accessed by shared code
4014 ******************************************************************************/
4015 static int
4016 e1000_wait_autoneg(struct e1000_hw *hw)
4017 {
4018         uint16_t i;
4019         uint16_t phy_data;
4020
4021         DEBUGFUNC();
4022         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4023
4024         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4025         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4026                 /* Read the MII Status Register and wait for Auto-Neg
4027                  * Complete bit to be set.
4028                  */
4029                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4030                         DEBUGOUT("PHY Read Error\n");
4031                         return -E1000_ERR_PHY;
4032                 }
4033                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4034                         DEBUGOUT("PHY Read Error\n");
4035                         return -E1000_ERR_PHY;
4036                 }
4037                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4038                         DEBUGOUT("Auto-Neg complete.\n");
4039                         return 0;
4040                 }
4041                 mdelay(100);
4042         }
4043         DEBUGOUT("Auto-Neg timedout.\n");
4044         return -E1000_ERR_TIMEOUT;
4045 }
4046
4047 /******************************************************************************
4048 * Raises the Management Data Clock
4049 *
4050 * hw - Struct containing variables accessed by shared code
4051 * ctrl - Device control register's current value
4052 ******************************************************************************/
4053 static void
4054 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4055 {
4056         /* Raise the clock input to the Management Data Clock (by setting the MDC
4057          * bit), and then delay 2 microseconds.
4058          */
4059         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4060         E1000_WRITE_FLUSH(hw);
4061         udelay(2);
4062 }
4063
4064 /******************************************************************************
4065 * Lowers the Management Data Clock
4066 *
4067 * hw - Struct containing variables accessed by shared code
4068 * ctrl - Device control register's current value
4069 ******************************************************************************/
4070 static void
4071 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4072 {
4073         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4074          * bit), and then delay 2 microseconds.
4075          */
4076         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4077         E1000_WRITE_FLUSH(hw);
4078         udelay(2);
4079 }
4080
4081 /******************************************************************************
4082 * Shifts data bits out to the PHY
4083 *
4084 * hw - Struct containing variables accessed by shared code
4085 * data - Data to send out to the PHY
4086 * count - Number of bits to shift out
4087 *
4088 * Bits are shifted out in MSB to LSB order.
4089 ******************************************************************************/
4090 static void
4091 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4092 {
4093         uint32_t ctrl;
4094         uint32_t mask;
4095
4096         /* We need to shift "count" number of bits out to the PHY. So, the value
4097          * in the "data" parameter will be shifted out to the PHY one bit at a
4098          * time. In order to do this, "data" must be broken down into bits.
4099          */
4100         mask = 0x01;
4101         mask <<= (count - 1);
4102
4103         ctrl = E1000_READ_REG(hw, CTRL);
4104
4105         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4106         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4107
4108         while (mask) {
4109                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4110                  * then raising and lowering the Management Data Clock. A "0" is
4111                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4112                  * raising and lowering the clock.
4113                  */
4114                 if (data & mask)
4115                         ctrl |= E1000_CTRL_MDIO;
4116                 else
4117                         ctrl &= ~E1000_CTRL_MDIO;
4118
4119                 E1000_WRITE_REG(hw, CTRL, ctrl);
4120                 E1000_WRITE_FLUSH(hw);
4121
4122                 udelay(2);
4123
4124                 e1000_raise_mdi_clk(hw, &ctrl);
4125                 e1000_lower_mdi_clk(hw, &ctrl);
4126
4127                 mask = mask >> 1;
4128         }
4129 }
4130
4131 /******************************************************************************
4132 * Shifts data bits in from the PHY
4133 *
4134 * hw - Struct containing variables accessed by shared code
4135 *
4136 * Bits are shifted in in MSB to LSB order.
4137 ******************************************************************************/
4138 static uint16_t
4139 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4140 {
4141         uint32_t ctrl;
4142         uint16_t data = 0;
4143         uint8_t i;
4144
4145         /* In order to read a register from the PHY, we need to shift in a total
4146          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4147          * to avoid contention on the MDIO pin when a read operation is performed.
4148          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4149          * by raising the input to the Management Data Clock (setting the MDC bit),
4150          * and then reading the value of the MDIO bit.
4151          */
4152         ctrl = E1000_READ_REG(hw, CTRL);
4153
4154         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4155         ctrl &= ~E1000_CTRL_MDIO_DIR;
4156         ctrl &= ~E1000_CTRL_MDIO;
4157
4158         E1000_WRITE_REG(hw, CTRL, ctrl);
4159         E1000_WRITE_FLUSH(hw);
4160
4161         /* Raise and Lower the clock before reading in the data. This accounts for
4162          * the turnaround bits. The first clock occurred when we clocked out the
4163          * last bit of the Register Address.
4164          */
4165         e1000_raise_mdi_clk(hw, &ctrl);
4166         e1000_lower_mdi_clk(hw, &ctrl);
4167
4168         for (data = 0, i = 0; i < 16; i++) {
4169                 data = data << 1;
4170                 e1000_raise_mdi_clk(hw, &ctrl);
4171                 ctrl = E1000_READ_REG(hw, CTRL);
4172                 /* Check to see if we shifted in a "1". */
4173                 if (ctrl & E1000_CTRL_MDIO)
4174                         data |= 1;
4175                 e1000_lower_mdi_clk(hw, &ctrl);
4176         }
4177
4178         e1000_raise_mdi_clk(hw, &ctrl);
4179         e1000_lower_mdi_clk(hw, &ctrl);
4180
4181         return data;
4182 }
4183
4184 /*****************************************************************************
4185 * Reads the value from a PHY register
4186 *
4187 * hw - Struct containing variables accessed by shared code
4188 * reg_addr - address of the PHY register to read
4189 ******************************************************************************/
4190 static int
4191 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4192 {
4193         uint32_t i;
4194         uint32_t mdic = 0;
4195         const uint32_t phy_addr = 1;
4196
4197         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4198                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4199                 return -E1000_ERR_PARAM;
4200         }
4201
4202         if (hw->mac_type > e1000_82543) {
4203                 /* Set up Op-code, Phy Address, and register address in the MDI
4204                  * Control register.  The MAC will take care of interfacing with the
4205                  * PHY to retrieve the desired data.
4206                  */
4207                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4208                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4209                         (E1000_MDIC_OP_READ));
4210
4211                 E1000_WRITE_REG(hw, MDIC, mdic);
4212
4213                 /* Poll the ready bit to see if the MDI read completed */
4214                 for (i = 0; i < 64; i++) {
4215                         udelay(10);
4216                         mdic = E1000_READ_REG(hw, MDIC);
4217                         if (mdic & E1000_MDIC_READY)
4218                                 break;
4219                 }
4220                 if (!(mdic & E1000_MDIC_READY)) {
4221                         DEBUGOUT("MDI Read did not complete\n");
4222                         return -E1000_ERR_PHY;
4223                 }
4224                 if (mdic & E1000_MDIC_ERROR) {
4225                         DEBUGOUT("MDI Error\n");
4226                         return -E1000_ERR_PHY;
4227                 }
4228                 *phy_data = (uint16_t) mdic;
4229         } else {
4230                 /* We must first send a preamble through the MDIO pin to signal the
4231                  * beginning of an MII instruction.  This is done by sending 32
4232                  * consecutive "1" bits.
4233                  */
4234                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4235
4236                 /* Now combine the next few fields that are required for a read
4237                  * operation.  We use this method instead of calling the
4238                  * e1000_shift_out_mdi_bits routine five different times. The format of
4239                  * a MII read instruction consists of a shift out of 14 bits and is
4240                  * defined as follows:
4241                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4242                  * followed by a shift in of 18 bits.  This first two bits shifted in
4243                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4244                  * READ operation is performed.  These two bits are thrown away
4245                  * followed by a shift in of 16 bits which contains the desired data.
4246                  */
4247                 mdic = ((reg_addr) | (phy_addr << 5) |
4248                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4249
4250                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4251
4252                 /* Now that we've shifted out the read command to the MII, we need to
4253                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4254                  * register address.
4255                  */
4256                 *phy_data = e1000_shift_in_mdi_bits(hw);
4257         }
4258         return 0;
4259 }
4260
4261 /******************************************************************************
4262 * Writes a value to a PHY register
4263 *
4264 * hw - Struct containing variables accessed by shared code
4265 * reg_addr - address of the PHY register to write
4266 * data - data to write to the PHY
4267 ******************************************************************************/
4268 static int
4269 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4270 {
4271         uint32_t i;
4272         uint32_t mdic = 0;
4273         const uint32_t phy_addr = 1;
4274
4275         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4276                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4277                 return -E1000_ERR_PARAM;
4278         }
4279
4280         if (hw->mac_type > e1000_82543) {
4281                 /* Set up Op-code, Phy Address, register address, and data intended
4282                  * for the PHY register in the MDI Control register.  The MAC will take
4283                  * care of interfacing with the PHY to send the desired data.
4284                  */
4285                 mdic = (((uint32_t) phy_data) |
4286                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4287                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4288                         (E1000_MDIC_OP_WRITE));
4289
4290                 E1000_WRITE_REG(hw, MDIC, mdic);
4291
4292                 /* Poll the ready bit to see if the MDI read completed */
4293                 for (i = 0; i < 64; i++) {
4294                         udelay(10);
4295                         mdic = E1000_READ_REG(hw, MDIC);
4296                         if (mdic & E1000_MDIC_READY)
4297                                 break;
4298                 }
4299                 if (!(mdic & E1000_MDIC_READY)) {
4300                         DEBUGOUT("MDI Write did not complete\n");
4301                         return -E1000_ERR_PHY;
4302                 }
4303         } else {
4304                 /* We'll need to use the SW defined pins to shift the write command
4305                  * out to the PHY. We first send a preamble to the PHY to signal the
4306                  * beginning of the MII instruction.  This is done by sending 32
4307                  * consecutive "1" bits.
4308                  */
4309                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4310
4311                 /* Now combine the remaining required fields that will indicate a
4312                  * write operation. We use this method instead of calling the
4313                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4314                  * format of a MII write instruction is as follows:
4315                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4316                  */
4317                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4318                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4319                 mdic <<= 16;
4320                 mdic |= (uint32_t) phy_data;
4321
4322                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4323         }
4324         return 0;
4325 }
4326
4327 /******************************************************************************
4328  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4329  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4330  * the caller to figure out how to deal with it.
4331  *
4332  * hw - Struct containing variables accessed by shared code
4333  *
4334  * returns: - E1000_BLK_PHY_RESET
4335  *            E1000_SUCCESS
4336  *
4337  *****************************************************************************/
4338 int32_t
4339 e1000_check_phy_reset_block(struct e1000_hw *hw)
4340 {
4341         uint32_t manc = 0;
4342         uint32_t fwsm = 0;
4343
4344         if (hw->mac_type == e1000_ich8lan) {
4345                 fwsm = E1000_READ_REG(hw, FWSM);
4346                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4347                                                 : E1000_BLK_PHY_RESET;
4348         }
4349
4350         if (hw->mac_type > e1000_82547_rev_2)
4351                 manc = E1000_READ_REG(hw, MANC);
4352         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4353                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4354 }
4355
4356 /***************************************************************************
4357  * Checks if the PHY configuration is done
4358  *
4359  * hw: Struct containing variables accessed by shared code
4360  *
4361  * returns: - E1000_ERR_RESET if fail to reset MAC
4362  *            E1000_SUCCESS at any other case.
4363  *
4364  ***************************************************************************/
4365 static int32_t
4366 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4367 {
4368         int32_t timeout = PHY_CFG_TIMEOUT;
4369         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4370
4371         DEBUGFUNC();
4372
4373         switch (hw->mac_type) {
4374         default:
4375                 mdelay(10);
4376                 break;
4377
4378         case e1000_80003es2lan:
4379                 /* Separate *_CFG_DONE_* bit for each port */
4380                 if (e1000_is_second_port(hw))
4381                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4382                 /* Fall Through */
4383
4384         case e1000_82571:
4385         case e1000_82572:
4386         case e1000_igb:
4387                 while (timeout) {
4388                         if (hw->mac_type == e1000_igb) {
4389                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4390                                         break;
4391                         } else {
4392                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4393                                         break;
4394                         }
4395                         mdelay(1);
4396                         timeout--;
4397                 }
4398                 if (!timeout) {
4399                         DEBUGOUT("MNG configuration cycle has not "
4400                                         "completed.\n");
4401                         return -E1000_ERR_RESET;
4402                 }
4403                 break;
4404         }
4405
4406         return E1000_SUCCESS;
4407 }
4408
4409 /******************************************************************************
4410 * Returns the PHY to the power-on reset state
4411 *
4412 * hw - Struct containing variables accessed by shared code
4413 ******************************************************************************/
4414 int32_t
4415 e1000_phy_hw_reset(struct e1000_hw *hw)
4416 {
4417         uint16_t swfw = E1000_SWFW_PHY0_SM;
4418         uint32_t ctrl, ctrl_ext;
4419         uint32_t led_ctrl;
4420         int32_t ret_val;
4421
4422         DEBUGFUNC();
4423
4424         /* In the case of the phy reset being blocked, it's not an error, we
4425          * simply return success without performing the reset. */
4426         ret_val = e1000_check_phy_reset_block(hw);
4427         if (ret_val)
4428                 return E1000_SUCCESS;
4429
4430         DEBUGOUT("Resetting Phy...\n");
4431
4432         if (hw->mac_type > e1000_82543) {
4433                 if (e1000_is_second_port(hw))
4434                         swfw = E1000_SWFW_PHY1_SM;
4435
4436                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4437                         DEBUGOUT("Unable to acquire swfw sync\n");
4438                         return -E1000_ERR_SWFW_SYNC;
4439                 }
4440
4441                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4442                  * bit. Then, take it out of reset.
4443                  */
4444                 ctrl = E1000_READ_REG(hw, CTRL);
4445                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4446                 E1000_WRITE_FLUSH(hw);
4447
4448                 if (hw->mac_type < e1000_82571)
4449                         udelay(10);
4450                 else
4451                         udelay(100);
4452
4453                 E1000_WRITE_REG(hw, CTRL, ctrl);
4454                 E1000_WRITE_FLUSH(hw);
4455
4456                 if (hw->mac_type >= e1000_82571)
4457                         mdelay(10);
4458
4459         } else {
4460                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4461                  * bit to put the PHY into reset. Then, take it out of reset.
4462                  */
4463                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4464                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4465                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4466                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4467                 E1000_WRITE_FLUSH(hw);
4468                 mdelay(10);
4469                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4470                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4471                 E1000_WRITE_FLUSH(hw);
4472         }
4473         udelay(150);
4474
4475         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4476                 /* Configure activity LED after PHY reset */
4477                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4478                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4479                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4480                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4481         }
4482
4483         e1000_swfw_sync_release(hw, swfw);
4484
4485         /* Wait for FW to finish PHY configuration. */
4486         ret_val = e1000_get_phy_cfg_done(hw);
4487         if (ret_val != E1000_SUCCESS)
4488                 return ret_val;
4489
4490         return ret_val;
4491 }
4492
4493 /******************************************************************************
4494  * IGP phy init script - initializes the GbE PHY
4495  *
4496  * hw - Struct containing variables accessed by shared code
4497  *****************************************************************************/
4498 static void
4499 e1000_phy_init_script(struct e1000_hw *hw)
4500 {
4501         uint32_t ret_val;
4502         uint16_t phy_saved_data;
4503         DEBUGFUNC();
4504
4505         if (hw->phy_init_script) {
4506                 mdelay(20);
4507
4508                 /* Save off the current value of register 0x2F5B to be
4509                  * restored at the end of this routine. */
4510                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4511
4512                 /* Disabled the PHY transmitter */
4513                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4514
4515                 mdelay(20);
4516
4517                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4518
4519                 mdelay(5);
4520
4521                 switch (hw->mac_type) {
4522                 case e1000_82541:
4523                 case e1000_82547:
4524                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4525
4526                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4527
4528                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4529
4530                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4531
4532                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4533
4534                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4535
4536                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4537
4538                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4539
4540                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4541                         break;
4542
4543                 case e1000_82541_rev_2:
4544                 case e1000_82547_rev_2:
4545                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4546                         break;
4547                 default:
4548                         break;
4549                 }
4550
4551                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4552
4553                 mdelay(20);
4554
4555                 /* Now enable the transmitter */
4556                 if (!ret_val)
4557                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4558
4559                 if (hw->mac_type == e1000_82547) {
4560                         uint16_t fused, fine, coarse;
4561
4562                         /* Move to analog registers page */
4563                         e1000_read_phy_reg(hw,
4564                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4565
4566                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4567                                 e1000_read_phy_reg(hw,
4568                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4569
4570                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4571                                 coarse = fused
4572                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4573
4574                                 if (coarse >
4575                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4576                                         coarse -=
4577                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4578                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4579                                 } else if (coarse
4580                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4581                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4582
4583                                 fused = (fused
4584                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4585                                         (fine
4586                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4587                                         (coarse
4588                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4589
4590                                 e1000_write_phy_reg(hw,
4591                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4592                                 e1000_write_phy_reg(hw,
4593                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4594                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4595                         }
4596                 }
4597         }
4598 }
4599
4600 /******************************************************************************
4601 * Resets the PHY
4602 *
4603 * hw - Struct containing variables accessed by shared code
4604 *
4605 * Sets bit 15 of the MII Control register
4606 ******************************************************************************/
4607 int32_t
4608 e1000_phy_reset(struct e1000_hw *hw)
4609 {
4610         int32_t ret_val;
4611         uint16_t phy_data;
4612
4613         DEBUGFUNC();
4614
4615         /* In the case of the phy reset being blocked, it's not an error, we
4616          * simply return success without performing the reset. */
4617         ret_val = e1000_check_phy_reset_block(hw);
4618         if (ret_val)
4619                 return E1000_SUCCESS;
4620
4621         switch (hw->phy_type) {
4622         case e1000_phy_igp:
4623         case e1000_phy_igp_2:
4624         case e1000_phy_igp_3:
4625         case e1000_phy_ife:
4626         case e1000_phy_igb:
4627                 ret_val = e1000_phy_hw_reset(hw);
4628                 if (ret_val)
4629                         return ret_val;
4630                 break;
4631         default:
4632                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4633                 if (ret_val)
4634                         return ret_val;
4635
4636                 phy_data |= MII_CR_RESET;
4637                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4638                 if (ret_val)
4639                         return ret_val;
4640
4641                 udelay(1);
4642                 break;
4643         }
4644
4645         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4646                 e1000_phy_init_script(hw);
4647
4648         return E1000_SUCCESS;
4649 }
4650
4651 static int e1000_set_phy_type (struct e1000_hw *hw)
4652 {
4653         DEBUGFUNC ();
4654
4655         if (hw->mac_type == e1000_undefined)
4656                 return -E1000_ERR_PHY_TYPE;
4657
4658         switch (hw->phy_id) {
4659         case M88E1000_E_PHY_ID:
4660         case M88E1000_I_PHY_ID:
4661         case M88E1011_I_PHY_ID:
4662         case M88E1111_I_PHY_ID:
4663                 hw->phy_type = e1000_phy_m88;
4664                 break;
4665         case IGP01E1000_I_PHY_ID:
4666                 if (hw->mac_type == e1000_82541 ||
4667                         hw->mac_type == e1000_82541_rev_2 ||
4668                         hw->mac_type == e1000_82547 ||
4669                         hw->mac_type == e1000_82547_rev_2) {
4670                         hw->phy_type = e1000_phy_igp;
4671                         break;
4672                 }
4673         case IGP03E1000_E_PHY_ID:
4674                 hw->phy_type = e1000_phy_igp_3;
4675                 break;
4676         case IFE_E_PHY_ID:
4677         case IFE_PLUS_E_PHY_ID:
4678         case IFE_C_E_PHY_ID:
4679                 hw->phy_type = e1000_phy_ife;
4680                 break;
4681         case GG82563_E_PHY_ID:
4682                 if (hw->mac_type == e1000_80003es2lan) {
4683                         hw->phy_type = e1000_phy_gg82563;
4684                         break;
4685                 }
4686         case BME1000_E_PHY_ID:
4687                 hw->phy_type = e1000_phy_bm;
4688                 break;
4689         case I210_I_PHY_ID:
4690                 hw->phy_type = e1000_phy_igb;
4691                 break;
4692                 /* Fall Through */
4693         default:
4694                 /* Should never have loaded on this device */
4695                 hw->phy_type = e1000_phy_undefined;
4696                 return -E1000_ERR_PHY_TYPE;
4697         }
4698
4699         return E1000_SUCCESS;
4700 }
4701
4702 /******************************************************************************
4703 * Probes the expected PHY address for known PHY IDs
4704 *
4705 * hw - Struct containing variables accessed by shared code
4706 ******************************************************************************/
4707 static int32_t
4708 e1000_detect_gig_phy(struct e1000_hw *hw)
4709 {
4710         int32_t phy_init_status, ret_val;
4711         uint16_t phy_id_high, phy_id_low;
4712         bool match = false;
4713
4714         DEBUGFUNC();
4715
4716         /* The 82571 firmware may still be configuring the PHY.  In this
4717          * case, we cannot access the PHY until the configuration is done.  So
4718          * we explicitly set the PHY values. */
4719         if (hw->mac_type == e1000_82571 ||
4720                 hw->mac_type == e1000_82572) {
4721                 hw->phy_id = IGP01E1000_I_PHY_ID;
4722                 hw->phy_type = e1000_phy_igp_2;
4723                 return E1000_SUCCESS;
4724         }
4725
4726         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4727          * work- around that forces PHY page 0 to be set or the reads fail.
4728          * The rest of the code in this routine uses e1000_read_phy_reg to
4729          * read the PHY ID.  So for ESB-2 we need to have this set so our
4730          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4731          * the routines below will figure this out as well. */
4732         if (hw->mac_type == e1000_80003es2lan)
4733                 hw->phy_type = e1000_phy_gg82563;
4734
4735         /* Read the PHY ID Registers to identify which PHY is onboard. */
4736         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4737         if (ret_val)
4738                 return ret_val;
4739
4740         hw->phy_id = (uint32_t) (phy_id_high << 16);
4741         udelay(20);
4742         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4743         if (ret_val)
4744                 return ret_val;
4745
4746         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4747         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4748
4749         switch (hw->mac_type) {
4750         case e1000_82543:
4751                 if (hw->phy_id == M88E1000_E_PHY_ID)
4752                         match = true;
4753                 break;
4754         case e1000_82544:
4755                 if (hw->phy_id == M88E1000_I_PHY_ID)
4756                         match = true;
4757                 break;
4758         case e1000_82540:
4759         case e1000_82545:
4760         case e1000_82545_rev_3:
4761         case e1000_82546:
4762         case e1000_82546_rev_3:
4763                 if (hw->phy_id == M88E1011_I_PHY_ID)
4764                         match = true;
4765                 break;
4766         case e1000_82541:
4767         case e1000_82541_rev_2:
4768         case e1000_82547:
4769         case e1000_82547_rev_2:
4770                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4771                         match = true;
4772
4773                 break;
4774         case e1000_82573:
4775                 if (hw->phy_id == M88E1111_I_PHY_ID)
4776                         match = true;
4777                 break;
4778         case e1000_82574:
4779                 if (hw->phy_id == BME1000_E_PHY_ID)
4780                         match = true;
4781                 break;
4782         case e1000_80003es2lan:
4783                 if (hw->phy_id == GG82563_E_PHY_ID)
4784                         match = true;
4785                 break;
4786         case e1000_ich8lan:
4787                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4788                         match = true;
4789                 if (hw->phy_id == IFE_E_PHY_ID)
4790                         match = true;
4791                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4792                         match = true;
4793                 if (hw->phy_id == IFE_C_E_PHY_ID)
4794                         match = true;
4795                 break;
4796         case e1000_igb:
4797                 if (hw->phy_id == I210_I_PHY_ID)
4798                         match = true;
4799                 break;
4800         default:
4801                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4802                 return -E1000_ERR_CONFIG;
4803         }
4804
4805         phy_init_status = e1000_set_phy_type(hw);
4806
4807         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4808                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4809                 return 0;
4810         }
4811         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4812         return -E1000_ERR_PHY;
4813 }
4814
4815 /*****************************************************************************
4816  * Set media type and TBI compatibility.
4817  *
4818  * hw - Struct containing variables accessed by shared code
4819  * **************************************************************************/
4820 void
4821 e1000_set_media_type(struct e1000_hw *hw)
4822 {
4823         uint32_t status;
4824
4825         DEBUGFUNC();
4826
4827         if (hw->mac_type != e1000_82543) {
4828                 /* tbi_compatibility is only valid on 82543 */
4829                 hw->tbi_compatibility_en = false;
4830         }
4831
4832         switch (hw->device_id) {
4833         case E1000_DEV_ID_82545GM_SERDES:
4834         case E1000_DEV_ID_82546GB_SERDES:
4835         case E1000_DEV_ID_82571EB_SERDES:
4836         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4837         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4838         case E1000_DEV_ID_82572EI_SERDES:
4839         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4840                 hw->media_type = e1000_media_type_internal_serdes;
4841                 break;
4842         default:
4843                 switch (hw->mac_type) {
4844                 case e1000_82542_rev2_0:
4845                 case e1000_82542_rev2_1:
4846                         hw->media_type = e1000_media_type_fiber;
4847                         break;
4848                 case e1000_ich8lan:
4849                 case e1000_82573:
4850                 case e1000_82574:
4851                 case e1000_igb:
4852                         /* The STATUS_TBIMODE bit is reserved or reused
4853                          * for the this device.
4854                          */
4855                         hw->media_type = e1000_media_type_copper;
4856                         break;
4857                 default:
4858                         status = E1000_READ_REG(hw, STATUS);
4859                         if (status & E1000_STATUS_TBIMODE) {
4860                                 hw->media_type = e1000_media_type_fiber;
4861                                 /* tbi_compatibility not valid on fiber */
4862                                 hw->tbi_compatibility_en = false;
4863                         } else {
4864                                 hw->media_type = e1000_media_type_copper;
4865                         }
4866                         break;
4867                 }
4868         }
4869 }
4870
4871 /**
4872  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4873  *
4874  * e1000_sw_init initializes the Adapter private data structure.
4875  * Fields are initialized based on PCI device information and
4876  * OS network device settings (MTU size).
4877  **/
4878
4879 static int
4880 e1000_sw_init(struct eth_device *nic)
4881 {
4882         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4883         int result;
4884
4885         /* PCI config space info */
4886         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4887         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4888         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4889                              &hw->subsystem_vendor_id);
4890         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4891
4892         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4893         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4894
4895         /* identify the MAC */
4896         result = e1000_set_mac_type(hw);
4897         if (result) {
4898                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4899                 return result;
4900         }
4901
4902         switch (hw->mac_type) {
4903         default:
4904                 break;
4905         case e1000_82541:
4906         case e1000_82547:
4907         case e1000_82541_rev_2:
4908         case e1000_82547_rev_2:
4909                 hw->phy_init_script = 1;
4910                 break;
4911         }
4912
4913         /* flow control settings */
4914         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4915         hw->fc_low_water = E1000_FC_LOW_THRESH;
4916         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4917         hw->fc_send_xon = 1;
4918
4919         /* Media type - copper or fiber */
4920         hw->tbi_compatibility_en = true;
4921         e1000_set_media_type(hw);
4922
4923         if (hw->mac_type >= e1000_82543) {
4924                 uint32_t status = E1000_READ_REG(hw, STATUS);
4925
4926                 if (status & E1000_STATUS_TBIMODE) {
4927                         DEBUGOUT("fiber interface\n");
4928                         hw->media_type = e1000_media_type_fiber;
4929                 } else {
4930                         DEBUGOUT("copper interface\n");
4931                         hw->media_type = e1000_media_type_copper;
4932                 }
4933         } else {
4934                 hw->media_type = e1000_media_type_fiber;
4935         }
4936
4937         hw->wait_autoneg_complete = true;
4938         if (hw->mac_type < e1000_82543)
4939                 hw->report_tx_early = 0;
4940         else
4941                 hw->report_tx_early = 1;
4942
4943         return E1000_SUCCESS;
4944 }
4945
4946 void
4947 fill_rx(struct e1000_hw *hw)
4948 {
4949         struct e1000_rx_desc *rd;
4950         unsigned long flush_start, flush_end;
4951
4952         rx_last = rx_tail;
4953         rd = rx_base + rx_tail;
4954         rx_tail = (rx_tail + 1) % 8;
4955         memset(rd, 0, 16);
4956         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4957
4958         /*
4959          * Make sure there are no stale data in WB over this area, which
4960          * might get written into the memory while the e1000 also writes
4961          * into the same memory area.
4962          */
4963         invalidate_dcache_range((unsigned long)packet,
4964                                 (unsigned long)packet + 4096);
4965         /* Dump the DMA descriptor into RAM. */
4966         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4967         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4968         flush_dcache_range(flush_start, flush_end);
4969
4970         E1000_WRITE_REG(hw, RDT, rx_tail);
4971 }
4972
4973 /**
4974  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4975  * @adapter: board private structure
4976  *
4977  * Configure the Tx unit of the MAC after a reset.
4978  **/
4979
4980 static void
4981 e1000_configure_tx(struct e1000_hw *hw)
4982 {
4983         unsigned long tctl;
4984         unsigned long tipg, tarc;
4985         uint32_t ipgr1, ipgr2;
4986
4987         E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
4988         E1000_WRITE_REG(hw, TDBAH, 0);
4989
4990         E1000_WRITE_REG(hw, TDLEN, 128);
4991
4992         /* Setup the HW Tx Head and Tail descriptor pointers */
4993         E1000_WRITE_REG(hw, TDH, 0);
4994         E1000_WRITE_REG(hw, TDT, 0);
4995         tx_tail = 0;
4996
4997         /* Set the default values for the Tx Inter Packet Gap timer */
4998         if (hw->mac_type <= e1000_82547_rev_2 &&
4999             (hw->media_type == e1000_media_type_fiber ||
5000              hw->media_type == e1000_media_type_internal_serdes))
5001                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5002         else
5003                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5004
5005         /* Set the default values for the Tx Inter Packet Gap timer */
5006         switch (hw->mac_type) {
5007         case e1000_82542_rev2_0:
5008         case e1000_82542_rev2_1:
5009                 tipg = DEFAULT_82542_TIPG_IPGT;
5010                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5011                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5012                 break;
5013         case e1000_80003es2lan:
5014                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5015                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5016                 break;
5017         default:
5018                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5019                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5020                 break;
5021         }
5022         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5023         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5024         E1000_WRITE_REG(hw, TIPG, tipg);
5025         /* Program the Transmit Control Register */
5026         tctl = E1000_READ_REG(hw, TCTL);
5027         tctl &= ~E1000_TCTL_CT;
5028         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5029             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5030
5031         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5032                 tarc = E1000_READ_REG(hw, TARC0);
5033                 /* set the speed mode bit, we'll clear it if we're not at
5034                  * gigabit link later */
5035                 /* git bit can be set to 1*/
5036         } else if (hw->mac_type == e1000_80003es2lan) {
5037                 tarc = E1000_READ_REG(hw, TARC0);
5038                 tarc |= 1;
5039                 E1000_WRITE_REG(hw, TARC0, tarc);
5040                 tarc = E1000_READ_REG(hw, TARC1);
5041                 tarc |= 1;
5042                 E1000_WRITE_REG(hw, TARC1, tarc);
5043         }
5044
5045
5046         e1000_config_collision_dist(hw);
5047         /* Setup Transmit Descriptor Settings for eop descriptor */
5048         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5049
5050         /* Need to set up RS bit */
5051         if (hw->mac_type < e1000_82543)
5052                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5053         else
5054                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5055
5056
5057         if (hw->mac_type == e1000_igb) {
5058                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5059
5060                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5061                 reg_txdctl |= 1 << 25;
5062                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5063                 mdelay(20);
5064         }
5065
5066
5067
5068         E1000_WRITE_REG(hw, TCTL, tctl);
5069
5070
5071 }
5072
5073 /**
5074  * e1000_setup_rctl - configure the receive control register
5075  * @adapter: Board private structure
5076  **/
5077 static void
5078 e1000_setup_rctl(struct e1000_hw *hw)
5079 {
5080         uint32_t rctl;
5081
5082         rctl = E1000_READ_REG(hw, RCTL);
5083
5084         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5085
5086         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5087                 | E1000_RCTL_RDMTS_HALF;        /* |
5088                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5089
5090         if (hw->tbi_compatibility_on == 1)
5091                 rctl |= E1000_RCTL_SBP;
5092         else
5093                 rctl &= ~E1000_RCTL_SBP;
5094
5095         rctl &= ~(E1000_RCTL_SZ_4096);
5096                 rctl |= E1000_RCTL_SZ_2048;
5097                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5098         E1000_WRITE_REG(hw, RCTL, rctl);
5099 }
5100
5101 /**
5102  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5103  * @adapter: board private structure
5104  *
5105  * Configure the Rx unit of the MAC after a reset.
5106  **/
5107 static void
5108 e1000_configure_rx(struct e1000_hw *hw)
5109 {
5110         unsigned long rctl, ctrl_ext;
5111         rx_tail = 0;
5112         /* make sure receives are disabled while setting up the descriptors */
5113         rctl = E1000_READ_REG(hw, RCTL);
5114         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5115         if (hw->mac_type >= e1000_82540) {
5116                 /* Set the interrupt throttling rate.  Value is calculated
5117                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5118 #define MAX_INTS_PER_SEC        8000
5119 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5120                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5121         }
5122
5123         if (hw->mac_type >= e1000_82571) {
5124                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5125                 /* Reset delay timers after every interrupt */
5126                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5127                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5128                 E1000_WRITE_FLUSH(hw);
5129         }
5130         /* Setup the Base and Length of the Rx Descriptor Ring */
5131         E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
5132         E1000_WRITE_REG(hw, RDBAH, 0);
5133
5134         E1000_WRITE_REG(hw, RDLEN, 128);
5135
5136         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5137         E1000_WRITE_REG(hw, RDH, 0);
5138         E1000_WRITE_REG(hw, RDT, 0);
5139         /* Enable Receives */
5140
5141         if (hw->mac_type == e1000_igb) {
5142
5143                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5144                 reg_rxdctl |= 1 << 25;
5145                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5146                 mdelay(20);
5147         }
5148
5149         E1000_WRITE_REG(hw, RCTL, rctl);
5150
5151         fill_rx(hw);
5152 }
5153
5154 /**************************************************************************
5155 POLL - Wait for a frame
5156 ***************************************************************************/
5157 static int
5158 e1000_poll(struct eth_device *nic)
5159 {
5160         struct e1000_hw *hw = nic->priv;
5161         struct e1000_rx_desc *rd;
5162         unsigned long inval_start, inval_end;
5163         uint32_t len;
5164
5165         /* return true if there's an ethernet packet ready to read */
5166         rd = rx_base + rx_last;
5167
5168         /* Re-load the descriptor from RAM. */
5169         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5170         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5171         invalidate_dcache_range(inval_start, inval_end);
5172
5173         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5174                 return 0;
5175         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5176         /* Packet received, make sure the data are re-loaded from RAM. */
5177         len = le32_to_cpu(rd->length);
5178         invalidate_dcache_range((unsigned long)packet,
5179                                 (unsigned long)packet +
5180                                 roundup(len, ARCH_DMA_MINALIGN));
5181         net_process_received_packet((uchar *)packet, len);
5182         fill_rx(hw);
5183         return 1;
5184 }
5185
5186 /**************************************************************************
5187 TRANSMIT - Transmit a frame
5188 ***************************************************************************/
5189 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5190 {
5191         void *nv_packet = (void *)txpacket;
5192         struct e1000_hw *hw = nic->priv;
5193         struct e1000_tx_desc *txp;
5194         int i = 0;
5195         unsigned long flush_start, flush_end;
5196
5197         txp = tx_base + tx_tail;
5198         tx_tail = (tx_tail + 1) % 8;
5199
5200         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5201         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5202         txp->upper.data = 0;
5203
5204         /* Dump the packet into RAM so e1000 can pick them. */
5205         flush_dcache_range((unsigned long)nv_packet,
5206                            (unsigned long)nv_packet +
5207                            roundup(length, ARCH_DMA_MINALIGN));
5208         /* Dump the descriptor into RAM as well. */
5209         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5210         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5211         flush_dcache_range(flush_start, flush_end);
5212
5213         E1000_WRITE_REG(hw, TDT, tx_tail);
5214
5215         E1000_WRITE_FLUSH(hw);
5216         while (1) {
5217                 invalidate_dcache_range(flush_start, flush_end);
5218                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5219                         break;
5220                 if (i++ > TOUT_LOOP) {
5221                         DEBUGOUT("e1000: tx timeout\n");
5222                         return 0;
5223                 }
5224                 udelay(10);     /* give the nic a chance to write to the register */
5225         }
5226         return 1;
5227 }
5228
5229 /*reset function*/
5230 static inline int
5231 e1000_reset(struct eth_device *nic)
5232 {
5233         struct e1000_hw *hw = nic->priv;
5234
5235         e1000_reset_hw(hw);
5236         if (hw->mac_type >= e1000_82544) {
5237                 E1000_WRITE_REG(hw, WUC, 0);
5238         }
5239         return e1000_init_hw(nic);
5240 }
5241
5242 /**************************************************************************
5243 DISABLE - Turn off ethernet interface
5244 ***************************************************************************/
5245 static void
5246 e1000_disable(struct eth_device *nic)
5247 {
5248         struct e1000_hw *hw = nic->priv;
5249
5250         /* Turn off the ethernet interface */
5251         E1000_WRITE_REG(hw, RCTL, 0);
5252         E1000_WRITE_REG(hw, TCTL, 0);
5253
5254         /* Clear the transmit ring */
5255         E1000_WRITE_REG(hw, TDH, 0);
5256         E1000_WRITE_REG(hw, TDT, 0);
5257
5258         /* Clear the receive ring */
5259         E1000_WRITE_REG(hw, RDH, 0);
5260         E1000_WRITE_REG(hw, RDT, 0);
5261
5262         /* put the card in its initial state */
5263 #if 0
5264         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5265 #endif
5266         mdelay(10);
5267
5268 }
5269
5270 /**************************************************************************
5271 INIT - set up ethernet interface(s)
5272 ***************************************************************************/
5273 static int
5274 e1000_init(struct eth_device *nic, bd_t * bis)
5275 {
5276         struct e1000_hw *hw = nic->priv;
5277         int ret_val = 0;
5278
5279         ret_val = e1000_reset(nic);
5280         if (ret_val < 0) {
5281                 if ((ret_val == -E1000_ERR_NOLINK) ||
5282                     (ret_val == -E1000_ERR_TIMEOUT)) {
5283                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5284                 } else {
5285                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5286                 }
5287                 return 0;
5288         }
5289         e1000_configure_tx(hw);
5290         e1000_setup_rctl(hw);
5291         e1000_configure_rx(hw);
5292         return 1;
5293 }
5294
5295 /******************************************************************************
5296  * Gets the current PCI bus type of hardware
5297  *
5298  * hw - Struct containing variables accessed by shared code
5299  *****************************************************************************/
5300 void e1000_get_bus_type(struct e1000_hw *hw)
5301 {
5302         uint32_t status;
5303
5304         switch (hw->mac_type) {
5305         case e1000_82542_rev2_0:
5306         case e1000_82542_rev2_1:
5307                 hw->bus_type = e1000_bus_type_pci;
5308                 break;
5309         case e1000_82571:
5310         case e1000_82572:
5311         case e1000_82573:
5312         case e1000_82574:
5313         case e1000_80003es2lan:
5314         case e1000_ich8lan:
5315         case e1000_igb:
5316                 hw->bus_type = e1000_bus_type_pci_express;
5317                 break;
5318         default:
5319                 status = E1000_READ_REG(hw, STATUS);
5320                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5321                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5322                 break;
5323         }
5324 }
5325
5326 /* A list of all registered e1000 devices */
5327 static LIST_HEAD(e1000_hw_list);
5328
5329 /**************************************************************************
5330 PROBE - Look for an adapter, this routine's visible to the outside
5331 You should omit the last argument struct pci_device * for a non-PCI NIC
5332 ***************************************************************************/
5333 int
5334 e1000_initialize(bd_t * bis)
5335 {
5336         unsigned int i;
5337         pci_dev_t devno;
5338
5339         DEBUGFUNC();
5340
5341         /* Find and probe all the matching PCI devices */
5342         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5343                 u32 val;
5344
5345                 /*
5346                  * These will never get freed due to errors, this allows us to
5347                  * perform SPI EEPROM programming from U-boot, for example.
5348                  */
5349                 struct eth_device *nic = malloc(sizeof(*nic));
5350                 struct e1000_hw *hw = malloc(sizeof(*hw));
5351                 if (!nic || !hw) {
5352                         printf("e1000#%u: Out of Memory!\n", i);
5353                         free(nic);
5354                         free(hw);
5355                         continue;
5356                 }
5357
5358                 /* Make sure all of the fields are initially zeroed */
5359                 memset(nic, 0, sizeof(*nic));
5360                 memset(hw, 0, sizeof(*hw));
5361
5362                 /* Assign the passed-in values */
5363                 hw->cardnum = i;
5364                 hw->pdev = devno;
5365                 hw->nic = nic;
5366                 nic->priv = hw;
5367
5368                 /* Generate a card name */
5369                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5370
5371                 /* Print a debug message with the IO base address */
5372                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5373                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5374
5375                 /* Try to enable I/O accesses and bus-mastering */
5376                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5377                 pci_write_config_dword(devno, PCI_COMMAND, val);
5378
5379                 /* Make sure it worked */
5380                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5381                 if (!(val & PCI_COMMAND_MEMORY)) {
5382                         E1000_ERR(nic, "Can't enable I/O memory\n");
5383                         continue;
5384                 }
5385                 if (!(val & PCI_COMMAND_MASTER)) {
5386                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5387                         continue;
5388                 }
5389
5390                 /* Are these variables needed? */
5391                 hw->fc = e1000_fc_default;
5392                 hw->original_fc = e1000_fc_default;
5393                 hw->autoneg_failed = 0;
5394                 hw->autoneg = 1;
5395                 hw->get_link_status = true;
5396 #ifndef CONFIG_E1000_NO_NVM
5397                 hw->eeprom_semaphore_present = true;
5398 #endif
5399                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5400                                                         PCI_REGION_MEM);
5401                 hw->mac_type = e1000_undefined;
5402
5403                 /* MAC and Phy settings */
5404                 if (e1000_sw_init(nic) < 0) {
5405                         E1000_ERR(nic, "Software init failed\n");
5406                         continue;
5407                 }
5408                 if (e1000_check_phy_reset_block(hw))
5409                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5410
5411                 /* Basic init was OK, reset the hardware and allow SPI access */
5412                 e1000_reset_hw(hw);
5413                 list_add_tail(&hw->list_node, &e1000_hw_list);
5414
5415 #ifndef CONFIG_E1000_NO_NVM
5416                 /* Validate the EEPROM and get chipset information */
5417 #if !defined(CONFIG_MVBC_1G)
5418                 if (e1000_init_eeprom_params(hw)) {
5419                         E1000_ERR(nic, "EEPROM is invalid!\n");
5420                         continue;
5421                 }
5422                 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5423                     e1000_validate_eeprom_checksum(hw))
5424                         continue;
5425 #endif
5426                 e1000_read_mac_addr(nic);
5427 #endif
5428                 e1000_get_bus_type(hw);
5429
5430 #ifndef CONFIG_E1000_NO_NVM
5431                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5432                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5433                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5434 #else
5435                 memset(nic->enetaddr, 0, 6);
5436                 printf("e1000: no NVM\n");
5437 #endif
5438
5439                 /* Set up the function pointers and register the device */
5440                 nic->init = e1000_init;
5441                 nic->recv = e1000_poll;
5442                 nic->send = e1000_transmit;
5443                 nic->halt = e1000_disable;
5444                 eth_register(nic);
5445         }
5446
5447         return i;
5448 }
5449
5450 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5451 {
5452         struct e1000_hw *hw;
5453
5454         list_for_each_entry(hw, &e1000_hw_list, list_node)
5455                 if (hw->cardnum == cardnum)
5456                         return hw;
5457
5458         return NULL;
5459 }
5460
5461 #ifdef CONFIG_CMD_E1000
5462 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5463                 int argc, char * const argv[])
5464 {
5465         struct e1000_hw *hw;
5466
5467         if (argc < 3) {
5468                 cmd_usage(cmdtp);
5469                 return 1;
5470         }
5471
5472         /* Make sure we can find the requested e1000 card */
5473         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5474         if (!hw) {
5475                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5476                 return 1;
5477         }
5478
5479         if (!strcmp(argv[2], "print-mac-address")) {
5480                 unsigned char *mac = hw->nic->enetaddr;
5481                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5482                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5483                 return 0;
5484         }
5485
5486 #ifdef CONFIG_E1000_SPI
5487         /* Handle the "SPI" subcommand */
5488         if (!strcmp(argv[2], "spi"))
5489                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5490 #endif
5491
5492         cmd_usage(cmdtp);
5493         return 1;
5494 }
5495
5496 U_BOOT_CMD(
5497         e1000, 7, 0, do_e1000,
5498         "Intel e1000 controller management",
5499         /*  */"<card#> print-mac-address\n"
5500 #ifdef CONFIG_E1000_SPI
5501         "e1000 <card#> spi show [<offset> [<length>]]\n"
5502         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5503         "e1000 <card#> spi program <addr> <offset> <length>\n"
5504         "e1000 <card#> spi checksum [update]\n"
5505 #endif
5506         "       - Manage the Intel E1000 PCI device"
5507 );
5508 #endif /* not CONFIG_CMD_E1000 */