drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004-2009 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19 #include <tsec.h>
  20 #include <asm/errno.h>
  21
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 #define MAXCONTROLLERS  (8)
  37
  38 static struct tsec_private *privlist[MAXCONTROLLERS];
  39 static int num_tsecs = 0;
  40
  41 #ifdef __GNUC__
  42 static RTXBD rtx __attribute__ ((aligned(8)));
  43 #else
  44 #error "rtx must be 64-bit aligned"
  45 #endif
  46
  47 static int tsec_send(struct eth_device *dev,
  48                      volatile void *packet, int length);
  49 static int tsec_recv(struct eth_device *dev);
  50 static int tsec_init(struct eth_device *dev, bd_t * bd);
  51 static void tsec_halt(struct eth_device *dev);
  52 static void init_registers(volatile tsec_t * regs);
  53 static void startup_tsec(struct eth_device *dev);
  54 static int init_phy(struct eth_device *dev);
  55 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
  56 uint read_phy_reg(struct tsec_private *priv, uint regnum);
  57 struct phy_info *get_phy_info(struct eth_device *dev);
  58 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
  59 static void adjust_link(struct eth_device *dev);
  60 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
  61         && !defined(BITBANGMII)
  62 static int tsec_miiphy_write(char *devname, unsigned char addr,
  63                              unsigned char reg, unsigned short value);
  64 static int tsec_miiphy_read(char *devname, unsigned char addr,
  65                             unsigned char reg, unsigned short *value);
  66 #endif
  67 #ifdef CONFIG_MCAST_TFTP
  68 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
  69 #endif
  70
  71 /* Default initializations for TSEC controllers. */
  72
  73 static struct tsec_info_struct tsec_info[] = {
  74 #ifdef CONFIG_TSEC1
  75         STD_TSEC_INFO(1),       /* TSEC1 */
  76 #endif
  77 #ifdef CONFIG_TSEC2
  78         STD_TSEC_INFO(2),       /* TSEC2 */
  79 #endif
  80 #ifdef CONFIG_MPC85XX_FEC
  81         {
  82                 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
  83                 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
  84                 .devname = CONFIG_MPC85XX_FEC_NAME,
  85                 .phyaddr = FEC_PHY_ADDR,
  86                 .flags = FEC_FLAGS
  87         },                      /* FEC */
  88 #endif
  89 #ifdef CONFIG_TSEC3
  90         STD_TSEC_INFO(3),       /* TSEC3 */
  91 #endif
  92 #ifdef CONFIG_TSEC4
  93         STD_TSEC_INFO(4),       /* TSEC4 */
  94 #endif
  95 };
  96
  97 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  98 {
  99         int i;
 100
 101         for (i = 0; i < num; i++)
 102                 tsec_initialize(bis, &tsecs[i]);
 103
 104         return 0;
 105 }
 106
 107 int tsec_standard_init(bd_t *bis)
 108 {
 109         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 110 }
 111
 112 /* Initialize device structure. Returns success if PHY
 113  * initialization succeeded (i.e. if it recognizes the PHY)
 114  */
 115 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
 116 {
 117         struct eth_device *dev;
 118         int i;
 119         struct tsec_private *priv;
 120
 121         dev = (struct eth_device *)malloc(sizeof *dev);
 122
 123         if (NULL == dev)
 124                 return 0;
 125
 126         memset(dev, 0, sizeof *dev);
 127
 128         priv = (struct tsec_private *)malloc(sizeof(*priv));
 129
 130         if (NULL == priv)
 131                 return 0;
 132
 133         privlist[num_tsecs++] = priv;
 134         priv->regs = tsec_info->regs;
 135         priv->phyregs = tsec_info->miiregs;
 136         priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 137
 138         priv->phyaddr = tsec_info->phyaddr;
 139         priv->flags = tsec_info->flags;
 140
 141         sprintf(dev->name, tsec_info->devname);
 142         dev->iobase = 0;
 143         dev->priv = priv;
 144         dev->init = tsec_init;
 145         dev->halt = tsec_halt;
 146         dev->send = tsec_send;
 147         dev->recv = tsec_recv;
 148 #ifdef CONFIG_MCAST_TFTP
 149         dev->mcast = tsec_mcast_addr;
 150 #endif
 151
 152         /* Tell u-boot to get the addr from the env */
 153         for (i = 0; i < 6; i++)
 154                 dev->enetaddr[i] = 0;
 155
 156         eth_register(dev);
 157
 158         /* Reset the MAC */
 159         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 160         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 161         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 162
 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 164         && !defined(BITBANGMII)
 165         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 166 #endif
 167
 168         /* Try to initialize PHY here, and return */
 169         return init_phy(dev);
 170 }
 171
 172 /* Initializes data structures and registers for the controller,
 173  * and brings the interface up.  Returns the link status, meaning
 174  * that it returns success if the link is up, failure otherwise.
 175  * This allows u-boot to find the first active controller.
 176  */
 177 int tsec_init(struct eth_device *dev, bd_t * bd)
 178 {
 179         uint tempval;
 180         char tmpbuf[MAC_ADDR_LEN];
 181         int i;
 182         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 183         volatile tsec_t *regs = priv->regs;
 184
 185         /* Make sure the controller is stopped */
 186         tsec_halt(dev);
 187
 188         /* Init MACCFG2.  Defaults to GMII */
 189         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 190
 191         /* Init ECNTRL */
 192         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 193
 194         /* Copy the station address into the address registers.
 195          * Backwards, because little endian MACS are dumb */
 196         for (i = 0; i < MAC_ADDR_LEN; i++) {
 197                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 198         }
 199         tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
 200                   tmpbuf[3];
 201
 202         regs->macstnaddr1 = tempval;
 203
 204         tempval = *((uint *) (tmpbuf + 4));
 205
 206         regs->macstnaddr2 = tempval;
 207
 208         /* reset the indices to zero */
 209         rxIdx = 0;
 210         txIdx = 0;
 211
 212         /* Clear out (for the most part) the other registers */
 213         init_registers(regs);
 214
 215         /* Ready the device for tx/rx */
 216         startup_tsec(dev);
 217
 218         /* If there's no link, fail */
 219         return (priv->link ? 0 : -1);
 220 }
 221
 222 /* Writes the given phy's reg with value, using the specified MDIO regs */
 223 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
 224                 uint reg, uint value)
 225 {
 226         int timeout = 1000000;
 227
 228         phyregs->miimadd = (addr << 8) | reg;
 229         phyregs->miimcon = value;
 230         asm("sync");
 231
 232         timeout = 1000000;
 233         while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
 234 }
 235
 236
 237 /* Provide the default behavior of writing the PHY of this ethernet device */
 238 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
 239
 240 /* Reads register regnum on the device's PHY through the
 241  * specified registers.  It lowers and raises the read
 242  * command, and waits for the data to become valid (miimind
 243  * notvalid bit cleared), and the bus to cease activity (miimind
 244  * busy bit cleared), and then returns the value
 245  */
 246 uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum)
 247 {
 248         uint value;
 249
 250         /* Put the address of the phy, and the register
 251          * number into MIIMADD */
 252         phyregs->miimadd = (phyid << 8) | regnum;
 253
 254         /* Clear the command register, and wait */
 255         phyregs->miimcom = 0;
 256         asm("sync");
 257
 258         /* Initiate a read command, and wait */
 259         phyregs->miimcom = MIIM_READ_COMMAND;
 260         asm("sync");
 261
 262         /* Wait for the the indication that the read is done */
 263         while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 264
 265         /* Grab the value read from the PHY */
 266         value = phyregs->miimstat;
 267
 268         return value;
 269 }
 270
 271 /* #define to provide old read_phy_reg functionality without duplicating code */
 272 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
 273
 274 #define TBIANA_SETTINGS ( \
 275                 TBIANA_ASYMMETRIC_PAUSE \
 276                 | TBIANA_SYMMETRIC_PAUSE \
 277                 | TBIANA_FULL_DUPLEX \
 278                 )
 279
 280 /* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
 281 #define TBICR_SETTINGS ( \
 282                 TBICR_PHY_RESET \
 283                 | TBICR_FULL_DUPLEX \
 284                 | TBICR_SPEED1_SET \
 285                 )
 286
 287 /* Configure the TBI for SGMII operation */
 288 static void tsec_configure_serdes(struct tsec_private *priv)
 289 {
 290         /* Access TBI PHY registers at given TSEC register offset as opposed to the
 291          * register offset used for external PHY accesses */
 292         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
 293                         TBIANA_SETTINGS);
 294         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
 295                         TBICON_CLK_SELECT);
 296         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
 297                         TBICR_SETTINGS);
 298 }
 299
 300 /* Discover which PHY is attached to the device, and configure it
 301  * properly.  If the PHY is not recognized, then return 0
 302  * (failure).  Otherwise, return 1
 303  */
 304 static int init_phy(struct eth_device *dev)
 305 {
 306         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 307         struct phy_info *curphy;
 308         volatile tsec_t *regs = priv->regs;
 309
 310         /* Assign a Physical address to the TBI */
 311         regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
 312         asm("sync");
 313
 314         /* Reset MII (due to new addresses) */
 315         priv->phyregs->miimcfg = MIIMCFG_RESET;
 316         asm("sync");
 317         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 318         asm("sync");
 319         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 320
 321         /* Get the cmd structure corresponding to the attached
 322          * PHY */
 323         curphy = get_phy_info(dev);
 324
 325         if (curphy == NULL) {
 326                 priv->phyinfo = NULL;
 327                 printf("%s: No PHY found\n", dev->name);
 328
 329                 return 0;
 330         }
 331
 332         if (regs->ecntrl & ECNTRL_SGMII_MODE)
 333                 tsec_configure_serdes(priv);
 334
 335         priv->phyinfo = curphy;
 336
 337         phy_run_commands(priv, priv->phyinfo->config);
 338
 339         return 1;
 340 }
 341
 342 /*
 343  * Returns which value to write to the control register.
 344  * For 10/100, the value is slightly different
 345  */
 346 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 347 {
 348         if (priv->flags & TSEC_GIGABIT)
 349                 return MIIM_CONTROL_INIT;
 350         else
 351                 return MIIM_CR_INIT;
 352 }
 353
 354 /*
 355  * Wait for auto-negotiation to complete, then determine link
 356  */
 357 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 358 {
 359         /*
 360          * Wait if the link is up, and autonegotiation is in progress
 361          * (ie - we're capable and it's not done)
 362          */
 363         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 364         if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 365                 int i = 0;
 366
 367                 puts("Waiting for PHY auto negotiation to complete");
 368                 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 369                         /*
 370                          * Timeout reached ?
 371                          */
 372                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 373                                 puts(" TIMEOUT !\n");
 374                                 priv->link = 0;
 375                                 return 0;
 376                         }
 377
 378                         if (ctrlc()) {
 379                                 puts("user interrupt!\n");
 380                                 priv->link = 0;
 381                                 return -EINTR;
 382                         }
 383
 384                         if ((i++ % 1000) == 0) {
 385                                 putc('.');
 386                         }
 387                         udelay(1000);   /* 1 ms */
 388                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 389                 }
 390                 puts(" done\n");
 391
 392                 /* Link status bit is latched low, read it again */
 393                 mii_reg = read_phy_reg(priv, MIIM_STATUS);
 394
 395                 udelay(500000); /* another 500 ms (results in faster booting) */
 396         }
 397
 398         priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
 399
 400         return 0;
 401 }
 402
 403 /* Generic function which updates the speed and duplex.  If
 404  * autonegotiation is enabled, it uses the AND of the link
 405  * partner's advertised capabilities and our advertised
 406  * capabilities.  If autonegotiation is disabled, we use the
 407  * appropriate bits in the control register.
 408  *
 409  * Stolen from Linux's mii.c and phy_device.c
 410  */
 411 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 412 {
 413         /* We're using autonegotiation */
 414         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 415                 uint lpa = 0;
 416                 uint gblpa = 0;
 417
 418                 /* Check for gigabit capability */
 419                 if (mii_reg & PHY_BMSR_EXT) {
 420                         /* We want a list of states supported by
 421                          * both PHYs in the link
 422                          */
 423                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 424                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 425                 }
 426
 427                 /* Set the baseline so we only have to set them
 428                  * if they're different
 429                  */
 430                 priv->speed = 10;
 431                 priv->duplexity = 0;
 432
 433                 /* Check the gigabit fields */
 434                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 435                         priv->speed = 1000;
 436
 437                         if (gblpa & PHY_1000BTSR_1000FD)
 438                                 priv->duplexity = 1;
 439
 440                         /* We're done! */
 441                         return 0;
 442                 }
 443
 444                 lpa = read_phy_reg(priv, PHY_ANAR);
 445                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 446
 447                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 448                         priv->speed = 100;
 449
 450                         if (lpa & PHY_ANLPAR_TXFD)
 451                                 priv->duplexity = 1;
 452
 453                 } else if (lpa & PHY_ANLPAR_10FD)
 454                         priv->duplexity = 1;
 455         } else {
 456                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 457
 458                 priv->speed = 10;
 459                 priv->duplexity = 0;
 460
 461                 if (bmcr & PHY_BMCR_DPLX)
 462                         priv->duplexity = 1;
 463
 464                 if (bmcr & PHY_BMCR_1000_MBPS)
 465                         priv->speed = 1000;
 466                 else if (bmcr & PHY_BMCR_100_MBPS)
 467                         priv->speed = 100;
 468         }
 469
 470         return 0;
 471 }
 472
 473 /*
 474  * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
 475  * circumstances.  eg a gigabit TSEC connected to a gigabit switch with
 476  * a 4-wire ethernet cable.  Both ends advertise gigabit, but can't
 477  * link.  "Ethernet@Wirespeed" reduces advertised speed until link
 478  * can be achieved.
 479  */
 480 uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
 481 {
 482         return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
 483 }
 484
 485 /*
 486  * Parse the BCM54xx status register for speed and duplex information.
 487  * The linux sungem_phy has this information, but in a table format.
 488  */
 489 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 490 {
 491         /* If there is no link, speed and duplex don't matter */
 492         if (!priv->link)
 493                 return 0;
 494
 495         switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
 496                 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
 497         case 1:
 498                 priv->duplexity = 0;
 499                 priv->speed = 10;
 500                 break;
 501         case 2:
 502                 priv->duplexity = 1;
 503                 priv->speed = 10;
 504                 break;
 505         case 3:
 506                 priv->duplexity = 0;
 507                 priv->speed = 100;
 508                 break;
 509         case 5:
 510                 priv->duplexity = 1;
 511                 priv->speed = 100;
 512                 break;
 513         case 6:
 514                 priv->duplexity = 0;
 515                 priv->speed = 1000;
 516                 break;
 517         case 7:
 518                 priv->duplexity = 1;
 519                 priv->speed = 1000;
 520                 break;
 521         default:
 522                 printf("Auto-neg error, defaulting to 10BT/HD\n");
 523                 priv->duplexity = 0;
 524                 priv->speed = 10;
 525                 break;
 526         }
 527
 528         return 0;
 529
 530 }
 531 /* Parse the 88E1011's status register for speed and duplex
 532  * information
 533  */
 534 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 535 {
 536         uint speed;
 537
 538         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 539
 540         if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
 541                 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 542                 int i = 0;
 543
 544                 puts("Waiting for PHY realtime link");
 545                 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 546                         /* Timeout reached ? */
 547                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 548                                 puts(" TIMEOUT !\n");
 549                                 priv->link = 0;
 550                                 break;
 551                         }
 552
 553                         if ((i++ % 1000) == 0) {
 554                                 putc('.');
 555                         }
 556                         udelay(1000);   /* 1 ms */
 557                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 558                 }
 559                 puts(" done\n");
 560                 udelay(500000); /* another 500 ms (results in faster booting) */
 561         } else {
 562                 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
 563                         priv->link = 1;
 564                 else
 565                         priv->link = 0;
 566         }
 567
 568         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 569                 priv->duplexity = 1;
 570         else
 571                 priv->duplexity = 0;
 572
 573         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 574
 575         switch (speed) {
 576         case MIIM_88E1011_PHYSTAT_GBIT:
 577                 priv->speed = 1000;
 578                 break;
 579         case MIIM_88E1011_PHYSTAT_100:
 580                 priv->speed = 100;
 581                 break;
 582         default:
 583                 priv->speed = 10;
 584         }
 585
 586         return 0;
 587 }
 588
 589 /* Parse the RTL8211B's status register for speed and duplex
 590  * information
 591  */
 592 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
 593 {
 594         uint speed;
 595
 596         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 597         if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 598                 int i = 0;
 599
 600                 /* in case of timeout ->link is cleared */
 601                 priv->link = 1;
 602                 puts("Waiting for PHY realtime link");
 603                 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 604                         /* Timeout reached ? */
 605                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 606                                 puts(" TIMEOUT !\n");
 607                                 priv->link = 0;
 608                                 break;
 609                         }
 610
 611                         if ((i++ % 1000) == 0) {
 612                                 putc('.');
 613                         }
 614                         udelay(1000);   /* 1 ms */
 615                         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 616                 }
 617                 puts(" done\n");
 618                 udelay(500000); /* another 500 ms (results in faster booting) */
 619         } else {
 620                 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
 621                         priv->link = 1;
 622                 else
 623                         priv->link = 0;
 624         }
 625
 626         if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
 627                 priv->duplexity = 1;
 628         else
 629                 priv->duplexity = 0;
 630
 631         speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
 632
 633         switch (speed) {
 634         case MIIM_RTL8211B_PHYSTAT_GBIT:
 635                 priv->speed = 1000;
 636                 break;
 637         case MIIM_RTL8211B_PHYSTAT_100:
 638                 priv->speed = 100;
 639                 break;
 640         default:
 641                 priv->speed = 10;
 642         }
 643
 644         return 0;
 645 }
 646
 647 /* Parse the cis8201's status register for speed and duplex
 648  * information
 649  */
 650 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 651 {
 652         uint speed;
 653
 654         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 655                 priv->duplexity = 1;
 656         else
 657                 priv->duplexity = 0;
 658
 659         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 660         switch (speed) {
 661         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 662                 priv->speed = 1000;
 663                 break;
 664         case MIIM_CIS8201_AUXCONSTAT_100:
 665                 priv->speed = 100;
 666                 break;
 667         default:
 668                 priv->speed = 10;
 669                 break;
 670         }
 671
 672         return 0;
 673 }
 674
 675 /* Parse the vsc8244's status register for speed and duplex
 676  * information
 677  */
 678 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 679 {
 680         uint speed;
 681
 682         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 683                 priv->duplexity = 1;
 684         else
 685                 priv->duplexity = 0;
 686
 687         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 688         switch (speed) {
 689         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 690                 priv->speed = 1000;
 691                 break;
 692         case MIIM_VSC8244_AUXCONSTAT_100:
 693                 priv->speed = 100;
 694                 break;
 695         default:
 696                 priv->speed = 10;
 697                 break;
 698         }
 699
 700         return 0;
 701 }
 702
 703 /* Parse the DM9161's status register for speed and duplex
 704  * information
 705  */
 706 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 707 {
 708         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 709                 priv->speed = 100;
 710         else
 711                 priv->speed = 10;
 712
 713         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 714                 priv->duplexity = 1;
 715         else
 716                 priv->duplexity = 0;
 717
 718         return 0;
 719 }
 720
 721 /*
 722  * Hack to write all 4 PHYs with the LED values
 723  */
 724 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 725 {
 726         uint phyid;
 727         volatile tsec_mdio_t *regbase = priv->phyregs;
 728         int timeout = 1000000;
 729
 730         for (phyid = 0; phyid < 4; phyid++) {
 731                 regbase->miimadd = (phyid << 8) | mii_reg;
 732                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 733                 asm("sync");
 734
 735                 timeout = 1000000;
 736                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 737         }
 738
 739         return MIIM_CIS8204_SLEDCON_INIT;
 740 }
 741
 742 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 743 {
 744         if (priv->flags & TSEC_REDUCED)
 745                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 746         else
 747                 return MIIM_CIS8204_EPHYCON_INIT;
 748 }
 749
 750 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
 751 {
 752         uint mii_data = read_phy_reg(priv, mii_reg);
 753
 754         if (priv->flags & TSEC_REDUCED)
 755                 mii_data = (mii_data & 0xfff0) | 0x000b;
 756         return mii_data;
 757 }
 758
 759 /* Initialized required registers to appropriate values, zeroing
 760  * those we don't care about (unless zero is bad, in which case,
 761  * choose a more appropriate value)
 762  */
 763 static void init_registers(volatile tsec_t * regs)
 764 {
 765         /* Clear IEVENT */
 766         regs->ievent = IEVENT_INIT_CLEAR;
 767
 768         regs->imask = IMASK_INIT_CLEAR;
 769
 770         regs->hash.iaddr0 = 0;
 771         regs->hash.iaddr1 = 0;
 772         regs->hash.iaddr2 = 0;
 773         regs->hash.iaddr3 = 0;
 774         regs->hash.iaddr4 = 0;
 775         regs->hash.iaddr5 = 0;
 776         regs->hash.iaddr6 = 0;
 777         regs->hash.iaddr7 = 0;
 778
 779         regs->hash.gaddr0 = 0;
 780         regs->hash.gaddr1 = 0;
 781         regs->hash.gaddr2 = 0;
 782         regs->hash.gaddr3 = 0;
 783         regs->hash.gaddr4 = 0;
 784         regs->hash.gaddr5 = 0;
 785         regs->hash.gaddr6 = 0;
 786         regs->hash.gaddr7 = 0;
 787
 788         regs->rctrl = 0x00000000;
 789
 790         /* Init RMON mib registers */
 791         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 792
 793         regs->rmon.cam1 = 0xffffffff;
 794         regs->rmon.cam2 = 0xffffffff;
 795
 796         regs->mrblr = MRBLR_INIT_SETTINGS;
 797
 798         regs->minflr = MINFLR_INIT_SETTINGS;
 799
 800         regs->attr = ATTR_INIT_SETTINGS;
 801         regs->attreli = ATTRELI_INIT_SETTINGS;
 802
 803 }
 804
 805 /* Configure maccfg2 based on negotiated speed and duplex
 806  * reported by PHY handling code
 807  */
 808 static void adjust_link(struct eth_device *dev)
 809 {
 810         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 811         volatile tsec_t *regs = priv->regs;
 812
 813         if (priv->link) {
 814                 if (priv->duplexity != 0)
 815                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 816                 else
 817                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 818
 819                 switch (priv->speed) {
 820                 case 1000:
 821                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 822                                          | MACCFG2_GMII);
 823                         break;
 824                 case 100:
 825                 case 10:
 826                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 827                                          | MACCFG2_MII);
 828
 829                         /* Set R100 bit in all modes although
 830                          * it is only used in RGMII mode
 831                          */
 832                         if (priv->speed == 100)
 833                                 regs->ecntrl |= ECNTRL_R100;
 834                         else
 835                                 regs->ecntrl &= ~(ECNTRL_R100);
 836                         break;
 837                 default:
 838                         printf("%s: Speed was bad\n", dev->name);
 839                         break;
 840                 }
 841
 842                 printf("Speed: %d, %s duplex\n", priv->speed,
 843                        (priv->duplexity) ? "full" : "half");
 844
 845         } else {
 846                 printf("%s: No link.\n", dev->name);
 847         }
 848 }
 849
 850 /* Set up the buffers and their descriptors, and bring up the
 851  * interface
 852  */
 853 static void startup_tsec(struct eth_device *dev)
 854 {
 855         int i;
 856         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 857         volatile tsec_t *regs = priv->regs;
 858
 859         /* Point to the buffer descriptors */
 860         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 861         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 862
 863         /* Initialize the Rx Buffer descriptors */
 864         for (i = 0; i < PKTBUFSRX; i++) {
 865                 rtx.rxbd[i].status = RXBD_EMPTY;
 866                 rtx.rxbd[i].length = 0;
 867                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 868         }
 869         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 870
 871         /* Initialize the TX Buffer Descriptors */
 872         for (i = 0; i < TX_BUF_CNT; i++) {
 873                 rtx.txbd[i].status = 0;
 874                 rtx.txbd[i].length = 0;
 875                 rtx.txbd[i].bufPtr = 0;
 876         }
 877         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 878
 879         /* Start up the PHY */
 880         if(priv->phyinfo)
 881                 phy_run_commands(priv, priv->phyinfo->startup);
 882
 883         adjust_link(dev);
 884
 885         /* Enable Transmit and Receive */
 886         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 887
 888         /* Tell the DMA it is clear to go */
 889         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 890         regs->tstat = TSTAT_CLEAR_THALT;
 891         regs->rstat = RSTAT_CLEAR_RHALT;
 892         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 893 }
 894
 895 /* This returns the status bits of the device.  The return value
 896  * is never checked, and this is what the 8260 driver did, so we
 897  * do the same.  Presumably, this would be zero if there were no
 898  * errors
 899  */
 900 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 901 {
 902         int i;
 903         int result = 0;
 904         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 905         volatile tsec_t *regs = priv->regs;
 906
 907         /* Find an empty buffer descriptor */
 908         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 909                 if (i >= TOUT_LOOP) {
 910                         debug("%s: tsec: tx buffers full\n", dev->name);
 911                         return result;
 912                 }
 913         }
 914
 915         rtx.txbd[txIdx].bufPtr = (uint) packet;
 916         rtx.txbd[txIdx].length = length;
 917         rtx.txbd[txIdx].status |=
 918             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 919
 920         /* Tell the DMA to go */
 921         regs->tstat = TSTAT_CLEAR_THALT;
 922
 923         /* Wait for buffer to be transmitted */
 924         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 925                 if (i >= TOUT_LOOP) {
 926                         debug("%s: tsec: tx error\n", dev->name);
 927                         return result;
 928                 }
 929         }
 930
 931         txIdx = (txIdx + 1) % TX_BUF_CNT;
 932         result = rtx.txbd[txIdx].status & TXBD_STATS;
 933
 934         return result;
 935 }
 936
 937 static int tsec_recv(struct eth_device *dev)
 938 {
 939         int length;
 940         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 941         volatile tsec_t *regs = priv->regs;
 942
 943         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 944
 945                 length = rtx.rxbd[rxIdx].length;
 946
 947                 /* Send the packet up if there were no errors */
 948                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 949                         NetReceive(NetRxPackets[rxIdx], length - 4);
 950                 } else {
 951                         printf("Got error %x\n",
 952                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 953                 }
 954
 955                 rtx.rxbd[rxIdx].length = 0;
 956
 957                 /* Set the wrap bit if this is the last element in the list */
 958                 rtx.rxbd[rxIdx].status =
 959                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 960
 961                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 962         }
 963
 964         if (regs->ievent & IEVENT_BSY) {
 965                 regs->ievent = IEVENT_BSY;
 966                 regs->rstat = RSTAT_CLEAR_RHALT;
 967         }
 968
 969         return -1;
 970
 971 }
 972
 973 /* Stop the interface */
 974 static void tsec_halt(struct eth_device *dev)
 975 {
 976         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 977         volatile tsec_t *regs = priv->regs;
 978
 979         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 980         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 981
 982         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 983
 984         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 985
 986         /* Shut down the PHY, as needed */
 987         if(priv->phyinfo)
 988                 phy_run_commands(priv, priv->phyinfo->shutdown);
 989 }
 990
 991 struct phy_info phy_info_M88E1149S = {
 992         0x1410ca,
 993         "Marvell 88E1149S",
 994         4,
 995         (struct phy_cmd[]){     /* config */
 996                 /* Reset and configure the PHY */
 997                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 998                 {0x1d, 0x1f, NULL},
 999                 {0x1e, 0x200c, NULL},
1000                 {0x1d, 0x5, NULL},
1001                 {0x1e, 0x0, NULL},
1002                 {0x1e, 0x100, NULL},
1003                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1004                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1005                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1006                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1007                 {miim_end,}
1008         },
1009         (struct phy_cmd[]){     /* startup */
1010                 /* Status is read once to clear old link state */
1011                 {MIIM_STATUS, miim_read, NULL},
1012                 /* Auto-negotiate */
1013                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1014                 /* Read the status */
1015                 {MIIM_88E1011_PHY_STATUS, miim_read,
1016                  &mii_parse_88E1011_psr},
1017                 {miim_end,}
1018         },
1019         (struct phy_cmd[]){     /* shutdown */
1020                 {miim_end,}
1021         },
1022 };
1023
1024 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1025 struct phy_info phy_info_BCM5461S = {
1026         0x02060c1,      /* 5461 ID */
1027         "Broadcom BCM5461S",
1028         0, /* not clear to me what minor revisions we can shift away */
1029         (struct phy_cmd[]) { /* config */
1030                 /* Reset and configure the PHY */
1031                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1032                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1033                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1034                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1035                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1036                 {miim_end,}
1037         },
1038         (struct phy_cmd[]) { /* startup */
1039                 /* Status is read once to clear old link state */
1040                 {MIIM_STATUS, miim_read, NULL},
1041                 /* Auto-negotiate */
1042                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1043                 /* Read the status */
1044                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1045                 {miim_end,}
1046         },
1047         (struct phy_cmd[]) { /* shutdown */
1048                 {miim_end,}
1049         },
1050 };
1051
1052 struct phy_info phy_info_BCM5464S = {
1053         0x02060b1,      /* 5464 ID */
1054         "Broadcom BCM5464S",
1055         0, /* not clear to me what minor revisions we can shift away */
1056         (struct phy_cmd[]) { /* config */
1057                 /* Reset and configure the PHY */
1058                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1059                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1060                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1061                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1062                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1063                 {miim_end,}
1064         },
1065         (struct phy_cmd[]) { /* startup */
1066                 /* Status is read once to clear old link state */
1067                 {MIIM_STATUS, miim_read, NULL},
1068                 /* Auto-negotiate */
1069                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1070                 /* Read the status */
1071                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1072                 {miim_end,}
1073         },
1074         (struct phy_cmd[]) { /* shutdown */
1075                 {miim_end,}
1076         },
1077 };
1078
1079 struct phy_info phy_info_BCM5482S =  {
1080         0x0143bcb,
1081         "Broadcom BCM5482S",
1082         4,
1083         (struct phy_cmd[]) { /* config */
1084                 /* Reset and configure the PHY */
1085                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1086                 /* Setup read from auxilary control shadow register 7 */
1087                 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1088                 /* Read Misc Control register and or in Ethernet@Wirespeed */
1089                 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1090                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1091                 {miim_end,}
1092         },
1093         (struct phy_cmd[]) { /* startup */
1094                 /* Status is read once to clear old link state */
1095                 {MIIM_STATUS, miim_read, NULL},
1096                 /* Auto-negotiate */
1097                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1098                 /* Read the status */
1099                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1100                 {miim_end,}
1101         },
1102         (struct phy_cmd[]) { /* shutdown */
1103                 {miim_end,}
1104         },
1105 };
1106
1107 struct phy_info phy_info_M88E1011S = {
1108         0x01410c6,
1109         "Marvell 88E1011S",
1110         4,
1111         (struct phy_cmd[]){     /* config */
1112                            /* Reset and configure the PHY */
1113                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1114                            {0x1d, 0x1f, NULL},
1115                            {0x1e, 0x200c, NULL},
1116                            {0x1d, 0x5, NULL},
1117                            {0x1e, 0x0, NULL},
1118                            {0x1e, 0x100, NULL},
1119                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1120                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1121                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1122                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1123                            {miim_end,}
1124                            },
1125         (struct phy_cmd[]){     /* startup */
1126                            /* Status is read once to clear old link state */
1127                            {MIIM_STATUS, miim_read, NULL},
1128                            /* Auto-negotiate */
1129                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1130                            /* Read the status */
1131                            {MIIM_88E1011_PHY_STATUS, miim_read,
1132                             &mii_parse_88E1011_psr},
1133                            {miim_end,}
1134                            },
1135         (struct phy_cmd[]){     /* shutdown */
1136                            {miim_end,}
1137                            },
1138 };
1139
1140 struct phy_info phy_info_M88E1111S = {
1141         0x01410cc,
1142         "Marvell 88E1111S",
1143         4,
1144         (struct phy_cmd[]){     /* config */
1145                            /* Reset and configure the PHY */
1146                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1147                            {0x1b, 0x848f, &mii_m88e1111s_setmode},
1148                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1149                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1150                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1151                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1152                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1153                            {miim_end,}
1154                            },
1155         (struct phy_cmd[]){     /* startup */
1156                            /* Status is read once to clear old link state */
1157                            {MIIM_STATUS, miim_read, NULL},
1158                            /* Auto-negotiate */
1159                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1160                            /* Read the status */
1161                            {MIIM_88E1011_PHY_STATUS, miim_read,
1162                             &mii_parse_88E1011_psr},
1163                            {miim_end,}
1164                            },
1165         (struct phy_cmd[]){     /* shutdown */
1166                            {miim_end,}
1167                            },
1168 };
1169
1170 struct phy_info phy_info_M88E1118 = {
1171         0x01410e1,
1172         "Marvell 88E1118",
1173         4,
1174         (struct phy_cmd[]){     /* config */
1175                 /* Reset and configure the PHY */
1176                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1177                 {0x16, 0x0002, NULL}, /* Change Page Number */
1178                 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1179                 {0x16, 0x0003, NULL}, /* Change Page Number */
1180                 {0x10, 0x021e, NULL}, /* Adjust LED control */
1181                 {0x16, 0x0000, NULL}, /* Change Page Number */
1182                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1183                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1184                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1185                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1186                 {miim_end,}
1187                 },
1188         (struct phy_cmd[]){     /* startup */
1189                 {0x16, 0x0000, NULL}, /* Change Page Number */
1190                 /* Status is read once to clear old link state */
1191                 {MIIM_STATUS, miim_read, NULL},
1192                 /* Auto-negotiate */
1193                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1194                 /* Read the status */
1195                 {MIIM_88E1011_PHY_STATUS, miim_read,
1196                  &mii_parse_88E1011_psr},
1197                 {miim_end,}
1198                 },
1199         (struct phy_cmd[]){     /* shutdown */
1200                 {miim_end,}
1201                 },
1202 };
1203
1204 /*
1205  *  Since to access LED register we need do switch the page, we
1206  * do LED configuring in the miim_read-like function as follows
1207  */
1208 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1209 {
1210         uint pg;
1211
1212         /* Switch the page to access the led register */
1213         pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1214         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1215
1216         /* Configure leds */
1217         write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1218                       MIIM_88E1121_PHY_LED_DEF);
1219
1220         /* Restore the page pointer */
1221         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1222         return 0;
1223 }
1224
1225 struct phy_info phy_info_M88E1121R = {
1226         0x01410cb,
1227         "Marvell 88E1121R",
1228         4,
1229         (struct phy_cmd[]){     /* config */
1230                            /* Reset and configure the PHY */
1231                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1232                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1233                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1234                            /* Configure leds */
1235                            {MIIM_88E1121_PHY_LED_CTRL, miim_read,
1236                             &mii_88E1121_set_led},
1237                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1238                            /* Disable IRQs and de-assert interrupt */
1239                            {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1240                            {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1241                            {miim_end,}
1242                            },
1243         (struct phy_cmd[]){     /* startup */
1244                            /* Status is read once to clear old link state */
1245                            {MIIM_STATUS, miim_read, NULL},
1246                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1247                            {MIIM_STATUS, miim_read, &mii_parse_link},
1248                            {miim_end,}
1249                            },
1250         (struct phy_cmd[]){     /* shutdown */
1251                            {miim_end,}
1252                            },
1253 };
1254
1255 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1256 {
1257         uint mii_data = read_phy_reg(priv, mii_reg);
1258
1259         /* Setting MIIM_88E1145_PHY_EXT_CR */
1260         if (priv->flags & TSEC_REDUCED)
1261                 return mii_data |
1262                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1263         else
1264                 return mii_data;
1265 }
1266
1267 static struct phy_info phy_info_M88E1145 = {
1268         0x01410cd,
1269         "Marvell 88E1145",
1270         4,
1271         (struct phy_cmd[]){     /* config */
1272                            /* Reset the PHY */
1273                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1274
1275                            /* Errata E0, E1 */
1276                            {29, 0x001b, NULL},
1277                            {30, 0x418f, NULL},
1278                            {29, 0x0016, NULL},
1279                            {30, 0xa2da, NULL},
1280
1281                            /* Configure the PHY */
1282                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1283                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1284                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1285                             NULL},
1286                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1287                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1288                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1289                            {miim_end,}
1290                            },
1291         (struct phy_cmd[]){     /* startup */
1292                            /* Status is read once to clear old link state */
1293                            {MIIM_STATUS, miim_read, NULL},
1294                            /* Auto-negotiate */
1295                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1296                            {MIIM_88E1111_PHY_LED_CONTROL,
1297                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1298                            /* Read the Status */
1299                            {MIIM_88E1011_PHY_STATUS, miim_read,
1300                             &mii_parse_88E1011_psr},
1301                            {miim_end,}
1302                            },
1303         (struct phy_cmd[]){     /* shutdown */
1304                            {miim_end,}
1305                            },
1306 };
1307
1308 struct phy_info phy_info_cis8204 = {
1309         0x3f11,
1310         "Cicada Cis8204",
1311         6,
1312         (struct phy_cmd[]){     /* config */
1313                            /* Override PHY config settings */
1314                            {MIIM_CIS8201_AUX_CONSTAT,
1315                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1316                            /* Configure some basic stuff */
1317                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1318                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1319                             &mii_cis8204_fixled},
1320                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1321                             &mii_cis8204_setmode},
1322                            {miim_end,}
1323                            },
1324         (struct phy_cmd[]){     /* startup */
1325                            /* Read the Status (2x to make sure link is right) */
1326                            {MIIM_STATUS, miim_read, NULL},
1327                            /* Auto-negotiate */
1328                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1329                            /* Read the status */
1330                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1331                             &mii_parse_cis8201},
1332                            {miim_end,}
1333                            },
1334         (struct phy_cmd[]){     /* shutdown */
1335                            {miim_end,}
1336                            },
1337 };
1338
1339 /* Cicada 8201 */
1340 struct phy_info phy_info_cis8201 = {
1341         0xfc41,
1342         "CIS8201",
1343         4,
1344         (struct phy_cmd[]){     /* config */
1345                            /* Override PHY config settings */
1346                            {MIIM_CIS8201_AUX_CONSTAT,
1347                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1348                            /* Set up the interface mode */
1349                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1350                             NULL},
1351                            /* Configure some basic stuff */
1352                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1353                            {miim_end,}
1354                            },
1355         (struct phy_cmd[]){     /* startup */
1356                            /* Read the Status (2x to make sure link is right) */
1357                            {MIIM_STATUS, miim_read, NULL},
1358                            /* Auto-negotiate */
1359                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1360                            /* Read the status */
1361                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1362                             &mii_parse_cis8201},
1363                            {miim_end,}
1364                            },
1365         (struct phy_cmd[]){     /* shutdown */
1366                            {miim_end,}
1367                            },
1368 };
1369 struct phy_info phy_info_VSC8211 = {
1370         0xfc4b,
1371         "Vitesse VSC8211",
1372         4,
1373         (struct phy_cmd[]) { /* config */
1374                            /* Override PHY config settings */
1375                            {MIIM_CIS8201_AUX_CONSTAT,
1376                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1377                            /* Set up the interface mode */
1378                            {MIIM_CIS8201_EXT_CON1,
1379                             MIIM_CIS8201_EXTCON1_INIT, NULL},
1380                            /* Configure some basic stuff */
1381                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1382                            {miim_end,}
1383                            },
1384         (struct phy_cmd[]) { /* startup */
1385                            /* Read the Status (2x to make sure link is right) */
1386                            {MIIM_STATUS, miim_read, NULL},
1387                            /* Auto-negotiate */
1388                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1389                            /* Read the status */
1390                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1391                             &mii_parse_cis8201},
1392                            {miim_end,}
1393                            },
1394         (struct phy_cmd[]) { /* shutdown */
1395                            {miim_end,}
1396         },
1397 };
1398 struct phy_info phy_info_VSC8244 = {
1399         0x3f1b,
1400         "Vitesse VSC8244",
1401         6,
1402         (struct phy_cmd[]){     /* config */
1403                            /* Override PHY config settings */
1404                            /* Configure some basic stuff */
1405                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1406                            {miim_end,}
1407                            },
1408         (struct phy_cmd[]){     /* startup */
1409                            /* Read the Status (2x to make sure link is right) */
1410                            {MIIM_STATUS, miim_read, NULL},
1411                            /* Auto-negotiate */
1412                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1413                            /* Read the status */
1414                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1415                             &mii_parse_vsc8244},
1416                            {miim_end,}
1417                            },
1418         (struct phy_cmd[]){     /* shutdown */
1419                            {miim_end,}
1420                            },
1421 };
1422
1423 struct phy_info phy_info_VSC8641 = {
1424         0x7043,
1425         "Vitesse VSC8641",
1426         4,
1427         (struct phy_cmd[]){     /* config */
1428                            /* Configure some basic stuff */
1429                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1430                            {miim_end,}
1431                            },
1432         (struct phy_cmd[]){     /* startup */
1433                            /* Read the Status (2x to make sure link is right) */
1434                            {MIIM_STATUS, miim_read, NULL},
1435                            /* Auto-negotiate */
1436                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1437                            /* Read the status */
1438                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1439                             &mii_parse_vsc8244},
1440                            {miim_end,}
1441                            },
1442         (struct phy_cmd[]){     /* shutdown */
1443                            {miim_end,}
1444                            },
1445 };
1446
1447 struct phy_info phy_info_VSC8221 = {
1448         0xfc55,
1449         "Vitesse VSC8221",
1450         4,
1451         (struct phy_cmd[]){     /* config */
1452                            /* Configure some basic stuff */
1453                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1454                            {miim_end,}
1455                            },
1456         (struct phy_cmd[]){     /* startup */
1457                            /* Read the Status (2x to make sure link is right) */
1458                            {MIIM_STATUS, miim_read, NULL},
1459                            /* Auto-negotiate */
1460                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1461                            /* Read the status */
1462                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1463                             &mii_parse_vsc8244},
1464                            {miim_end,}
1465                            },
1466         (struct phy_cmd[]){     /* shutdown */
1467                            {miim_end,}
1468                            },
1469 };
1470
1471 struct phy_info phy_info_VSC8601 = {
1472                 0x00007042,
1473                 "Vitesse VSC8601",
1474                 4,
1475                 (struct phy_cmd[]){     /* config */
1476                                 /* Override PHY config settings */
1477                                 /* Configure some basic stuff */
1478                                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1479 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1480                                 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1481 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1482                                 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1483 #define VSC8101_SKEW    (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
1484                                 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1485                                 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1486 #endif
1487 #endif
1488                                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1489                                 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1490                                 {miim_end,}
1491                                  },
1492                 (struct phy_cmd[]){     /* startup */
1493                                 /* Read the Status (2x to make sure link is right) */
1494                                 {MIIM_STATUS, miim_read, NULL},
1495                                 /* Auto-negotiate */
1496                                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1497                                 /* Read the status */
1498                                 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1499                                                 &mii_parse_vsc8244},
1500                                 {miim_end,}
1501                                 },
1502                 (struct phy_cmd[]){     /* shutdown */
1503                                 {miim_end,}
1504                                 },
1505 };
1506
1507
1508 struct phy_info phy_info_dm9161 = {
1509         0x0181b88,
1510         "Davicom DM9161E",
1511         4,
1512         (struct phy_cmd[]){     /* config */
1513                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1514                            /* Do not bypass the scrambler/descrambler */
1515                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1516                            /* Clear 10BTCSR to default */
1517                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1518                             NULL},
1519                            /* Configure some basic stuff */
1520                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1521                            /* Restart Auto Negotiation */
1522                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1523                            {miim_end,}
1524                            },
1525         (struct phy_cmd[]){     /* startup */
1526                            /* Status is read once to clear old link state */
1527                            {MIIM_STATUS, miim_read, NULL},
1528                            /* Auto-negotiate */
1529                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1530                            /* Read the status */
1531                            {MIIM_DM9161_SCSR, miim_read,
1532                             &mii_parse_dm9161_scsr},
1533                            {miim_end,}
1534                            },
1535         (struct phy_cmd[]){     /* shutdown */
1536                            {miim_end,}
1537                            },
1538 };
1539 /* a generic flavor.  */
1540 struct phy_info phy_info_generic =  {
1541         0,
1542         "Unknown/Generic PHY",
1543         32,
1544         (struct phy_cmd[]) { /* config */
1545                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1546                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1547                 {miim_end,}
1548         },
1549         (struct phy_cmd[]) { /* startup */
1550                 {PHY_BMSR, miim_read, NULL},
1551                 {PHY_BMSR, miim_read, &mii_parse_sr},
1552                 {PHY_BMSR, miim_read, &mii_parse_link},
1553                 {miim_end,}
1554         },
1555         (struct phy_cmd[]) { /* shutdown */
1556                 {miim_end,}
1557         }
1558 };
1559
1560
1561 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1562 {
1563         unsigned int speed;
1564         if (priv->link) {
1565                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1566
1567                 switch (speed) {
1568                 case MIIM_LXT971_SR2_10HDX:
1569                         priv->speed = 10;
1570                         priv->duplexity = 0;
1571                         break;
1572                 case MIIM_LXT971_SR2_10FDX:
1573                         priv->speed = 10;
1574                         priv->duplexity = 1;
1575                         break;
1576                 case MIIM_LXT971_SR2_100HDX:
1577                         priv->speed = 100;
1578                         priv->duplexity = 0;
1579                         break;
1580                 default:
1581                         priv->speed = 100;
1582                         priv->duplexity = 1;
1583                 }
1584         } else {
1585                 priv->speed = 0;
1586                 priv->duplexity = 0;
1587         }
1588
1589         return 0;
1590 }
1591
1592 static struct phy_info phy_info_lxt971 = {
1593         0x0001378e,
1594         "LXT971",
1595         4,
1596         (struct phy_cmd[]){     /* config */
1597                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1598                            {miim_end,}
1599                            },
1600         (struct phy_cmd[]){     /* startup - enable interrupts */
1601                            /* { 0x12, 0x00f2, NULL }, */
1602                            {MIIM_STATUS, miim_read, NULL},
1603                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1604                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1605                            {miim_end,}
1606                            },
1607         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1608                            {miim_end,}
1609                            },
1610 };
1611
1612 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1613  * information
1614  */
1615 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1616 {
1617         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1618
1619         case MIIM_DP83865_SPD_1000:
1620                 priv->speed = 1000;
1621                 break;
1622
1623         case MIIM_DP83865_SPD_100:
1624                 priv->speed = 100;
1625                 break;
1626
1627         default:
1628                 priv->speed = 10;
1629                 break;
1630
1631         }
1632
1633         if (mii_reg & MIIM_DP83865_DPX_FULL)
1634                 priv->duplexity = 1;
1635         else
1636                 priv->duplexity = 0;
1637
1638         return 0;
1639 }
1640
1641 struct phy_info phy_info_dp83865 = {
1642         0x20005c7,
1643         "NatSemi DP83865",
1644         4,
1645         (struct phy_cmd[]){     /* config */
1646                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1647                            {miim_end,}
1648                            },
1649         (struct phy_cmd[]){     /* startup */
1650                            /* Status is read once to clear old link state */
1651                            {MIIM_STATUS, miim_read, NULL},
1652                            /* Auto-negotiate */
1653                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1654                            /* Read the link and auto-neg status */
1655                            {MIIM_DP83865_LANR, miim_read,
1656                             &mii_parse_dp83865_lanr},
1657                            {miim_end,}
1658                            },
1659         (struct phy_cmd[]){     /* shutdown */
1660                            {miim_end,}
1661                            },
1662 };
1663
1664 struct phy_info phy_info_rtl8211b = {
1665         0x001cc91,
1666         "RealTek RTL8211B",
1667         4,
1668         (struct phy_cmd[]){     /* config */
1669                 /* Reset and configure the PHY */
1670                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1671                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1672                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1673                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1674                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1675                 {miim_end,}
1676         },
1677         (struct phy_cmd[]){     /* startup */
1678                 /* Status is read once to clear old link state */
1679                 {MIIM_STATUS, miim_read, NULL},
1680                 /* Auto-negotiate */
1681                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1682                 /* Read the status */
1683                 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1684                 {miim_end,}
1685         },
1686         (struct phy_cmd[]){     /* shutdown */
1687                 {miim_end,}
1688         },
1689 };
1690
1691 struct phy_info *phy_info[] = {
1692         &phy_info_cis8204,
1693         &phy_info_cis8201,
1694         &phy_info_BCM5461S,
1695         &phy_info_BCM5464S,
1696         &phy_info_BCM5482S,
1697         &phy_info_M88E1011S,
1698         &phy_info_M88E1111S,
1699         &phy_info_M88E1118,
1700         &phy_info_M88E1121R,
1701         &phy_info_M88E1145,
1702         &phy_info_M88E1149S,
1703         &phy_info_dm9161,
1704         &phy_info_lxt971,
1705         &phy_info_VSC8211,
1706         &phy_info_VSC8244,
1707         &phy_info_VSC8601,
1708         &phy_info_VSC8641,
1709         &phy_info_VSC8221,
1710         &phy_info_dp83865,
1711         &phy_info_rtl8211b,
1712         &phy_info_generic,      /* must be last; has ID 0 and 32 bit mask */
1713         NULL
1714 };
1715
1716 /* Grab the identifier of the device's PHY, and search through
1717  * all of the known PHYs to see if one matches.  If so, return
1718  * it, if not, return NULL
1719  */
1720 struct phy_info *get_phy_info(struct eth_device *dev)
1721 {
1722         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1723         uint phy_reg, phy_ID;
1724         int i;
1725         struct phy_info *theInfo = NULL;
1726
1727         /* Grab the bits from PHYIR1, and put them in the upper half */
1728         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1729         phy_ID = (phy_reg & 0xffff) << 16;
1730
1731         /* Grab the bits from PHYIR2, and put them in the lower half */
1732         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1733         phy_ID |= (phy_reg & 0xffff);
1734
1735         /* loop through all the known PHY types, and find one that */
1736         /* matches the ID we read from the PHY. */
1737         for (i = 0; phy_info[i]; i++) {
1738                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1739                         theInfo = phy_info[i];
1740                         break;
1741                 }
1742         }
1743
1744         if (theInfo == &phy_info_generic) {
1745                 printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
1746         } else {
1747                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1748         }
1749
1750         return theInfo;
1751 }
1752
1753 /* Execute the given series of commands on the given device's
1754  * PHY, running functions as necessary
1755  */
1756 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1757 {
1758         int i;
1759         uint result;
1760         volatile tsec_mdio_t *phyregs = priv->phyregs;
1761
1762         phyregs->miimcfg = MIIMCFG_RESET;
1763
1764         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1765
1766         while (phyregs->miimind & MIIMIND_BUSY) ;
1767
1768         for (i = 0; cmd->mii_reg != miim_end; i++) {
1769                 if (cmd->mii_data == miim_read) {
1770                         result = read_phy_reg(priv, cmd->mii_reg);
1771
1772                         if (cmd->funct != NULL)
1773                                 (*(cmd->funct)) (result, priv);
1774
1775                 } else {
1776                         if (cmd->funct != NULL)
1777                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1778                         else
1779                                 result = cmd->mii_data;
1780
1781                         write_phy_reg(priv, cmd->mii_reg, result);
1782
1783                 }
1784                 cmd++;
1785         }
1786 }
1787
1788 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1789         && !defined(BITBANGMII)
1790
1791 /*
1792  * Read a MII PHY register.
1793  *
1794  * Returns:
1795  *  0 on success
1796  */
1797 static int tsec_miiphy_read(char *devname, unsigned char addr,
1798                             unsigned char reg, unsigned short *value)
1799 {
1800         unsigned short ret;
1801         struct tsec_private *priv = privlist[0];
1802
1803         if (NULL == priv) {
1804                 printf("Can't read PHY at address %d\n", addr);
1805                 return -1;
1806         }
1807
1808         ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1809         *value = ret;
1810
1811         return 0;
1812 }
1813
1814 /*
1815  * Write a MII PHY register.
1816  *
1817  * Returns:
1818  *  0 on success
1819  */
1820 static int tsec_miiphy_write(char *devname, unsigned char addr,
1821                              unsigned char reg, unsigned short value)
1822 {
1823         struct tsec_private *priv = privlist[0];
1824
1825         if (NULL == priv) {
1826                 printf("Can't write PHY at address %d\n", addr);
1827                 return -1;
1828         }
1829
1830         tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1831
1832         return 0;
1833 }
1834
1835 #endif
1836
1837 #ifdef CONFIG_MCAST_TFTP
1838
1839 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1840
1841 /* Set the appropriate hash bit for the given addr */
1842
1843 /* The algorithm works like so:
1844  * 1) Take the Destination Address (ie the multicast address), and
1845  * do a CRC on it (little endian), and reverse the bits of the
1846  * result.
1847  * 2) Use the 8 most significant bits as a hash into a 256-entry
1848  * table.  The table is controlled through 8 32-bit registers:
1849  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1850  * gaddr7.  This means that the 3 most significant bits in the
1851  * hash index which gaddr register to use, and the 5 other bits
1852  * indicate which bit (assuming an IBM numbering scheme, which
1853  * for PowerPC (tm) is usually the case) in the tregister holds
1854  * the entry. */
1855 static int
1856 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1857 {
1858  struct tsec_private *priv = privlist[1];
1859  volatile tsec_t *regs = priv->regs;
1860  volatile u32  *reg_array, value;
1861  u8 result, whichbit, whichreg;
1862
1863         result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1864         whichbit = result & 0x1f;       /* the 5 LSB = which bit to set */
1865         whichreg = result >> 5;         /* the 3 MSB = which reg to set it in */
1866         value = (1 << (31-whichbit));
1867
1868         reg_array = &(regs->hash.gaddr0);
1869
1870         if (set) {
1871                 reg_array[whichreg] |= value;
1872         } else {
1873                 reg_array[whichreg] &= ~value;
1874         }
1875         return 0;
1876 }
1877 #endif /* Multicast TFTP ? */