drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #ifdef CONFIG_PCI
  34
  35 #include <command.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <pci.h>
  39
  40 #define PCI_HOSE_OP(rw, size, type)                                     \
  41 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  42                                   pci_dev_t dev,                        \
  43                                   int offset, type value)               \
  44 {                                                                       \
  45         return hose->rw##_##size(hose, dev, offset, value);             \
  46 }
  47
  48 PCI_HOSE_OP(read, byte, u8 *)
  49 PCI_HOSE_OP(read, word, u16 *)
  50 PCI_HOSE_OP(read, dword, u32 *)
  51 PCI_HOSE_OP(write, byte, u8)
  52 PCI_HOSE_OP(write, word, u16)
  53 PCI_HOSE_OP(write, dword, u32)
  54
  55 #ifndef CONFIG_IXP425
  56 #define PCI_OP(rw, size, type, error_code)                              \
  57 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  58 {                                                                       \
  59         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  60                                                                         \
  61         if (!hose)                                                      \
  62         {                                                               \
  63                 error_code;                                             \
  64                 return -1;                                              \
  65         }                                                               \
  66                                                                         \
  67         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  68 }
  69
  70 PCI_OP(read, byte, u8 *, *value = 0xff)
  71 PCI_OP(read, word, u16 *, *value = 0xffff)
  72 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  73 PCI_OP(write, byte, u8, )
  74 PCI_OP(write, word, u16, )
  75 PCI_OP(write, dword, u32, )
  76 #endif  /* CONFIG_IXP425 */
  77
  78 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  79 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  80                                         pci_dev_t dev,                  \
  81                                         int offset, type val)           \
  82 {                                                                       \
  83         u32 val32;                                                      \
  84                                                                         \
  85         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  86                 *val = -1;                                              \
  87                 return -1;                                              \
  88         }                                                               \
  89                                                                         \
  90         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  91                                                                         \
  92         return 0;                                                       \
  93 }
  94
  95 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  96 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  97                                              pci_dev_t dev,             \
  98                                              int offset, type val)      \
  99 {                                                                       \
 100         u32 val32, mask, ldata, shift;                                  \
 101                                                                         \
 102         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 103                 return -1;                                              \
 104                                                                         \
 105         shift = ((offset & (int)off_mask) * 8);                         \
 106         ldata = (((unsigned long)val) & val_mask) << shift;             \
 107         mask = val_mask << shift;                                       \
 108         val32 = (val32 & ~mask) | ldata;                                \
 109                                                                         \
 110         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 111                 return -1;                                              \
 112                                                                         \
 113         return 0;                                                       \
 114 }
 115
 116 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 117 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 118 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 119 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 120
 121 /*
 122  *
 123  */
 124
 125 static struct pci_controller* hose_head = NULL;
 126
 127 void pci_register_hose(struct pci_controller* hose)
 128 {
 129         struct pci_controller **phose = &hose_head;
 130
 131         while(*phose)
 132                 phose = &(*phose)->next;
 133
 134         hose->next = NULL;
 135
 136         *phose = hose;
 137 }
 138
 139 struct pci_controller *pci_bus_to_hose (int bus)
 140 {
 141         struct pci_controller *hose;
 142
 143         for (hose = hose_head; hose; hose = hose->next)
 144                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 145                         return hose;
 146
 147         printf("pci_bus_to_hose() failed\n");
 148         return NULL;
 149 }
 150
 151 #ifndef CONFIG_IXP425
 152 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 153 {
 154         struct pci_controller * hose;
 155         u16 vendor, device;
 156         u8 header_type;
 157         pci_dev_t bdf;
 158         int i, bus, found_multi = 0;
 159
 160         for (hose = hose_head; hose; hose = hose->next)
 161         {
 162 #ifdef CFG_SCSI_SCAN_BUS_REVERSE
 163                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 164 #else
 165                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 166 #endif
 167                         for (bdf = PCI_BDF(bus,0,0);
 168 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 169                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 170 #else
 171                              bdf < PCI_BDF(bus+1,0,0);
 172 #endif
 173                              bdf += PCI_BDF(0,0,1))
 174                         {
 175                                 if (!PCI_FUNC(bdf)) {
 176                                         pci_read_config_byte(bdf,
 177                                                              PCI_HEADER_TYPE,
 178                                                              &header_type);
 179
 180                                         found_multi = header_type & 0x80;
 181                                 } else {
 182                                         if (!found_multi)
 183                                                 continue;
 184                                 }
 185
 186                                 pci_read_config_word(bdf,
 187                                                      PCI_VENDOR_ID,
 188                                                      &vendor);
 189                                 pci_read_config_word(bdf,
 190                                                      PCI_DEVICE_ID,
 191                                                      &device);
 192
 193                                 for (i=0; ids[i].vendor != 0; i++)
 194                                         if (vendor == ids[i].vendor &&
 195                                             device == ids[i].device)
 196                                         {
 197                                                 if (index <= 0)
 198                                                         return bdf;
 199
 200                                                 index--;
 201                                         }
 202                         }
 203         }
 204
 205         return (-1);
 206 }
 207 #endif  /* CONFIG_IXP425 */
 208
 209 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 210 {
 211         static struct pci_device_id ids[2] = {{}, {0, 0}};
 212
 213         ids[0].vendor = vendor;
 214         ids[0].device = device;
 215
 216         return pci_find_devices(ids, index);
 217 }
 218
 219 /*
 220  *
 221  */
 222
 223 unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
 224                                     phys_addr_t phys_addr,
 225                                     unsigned long flags)
 226 {
 227         struct pci_region *res;
 228         unsigned long bus_addr;
 229         int i;
 230
 231         if (!hose) {
 232                 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
 233                 goto Done;
 234         }
 235
 236         for (i = 0; i < hose->region_count; i++) {
 237                 res = &hose->regions[i];
 238
 239                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 240                         continue;
 241
 242                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 243
 244                 if (bus_addr >= res->bus_start &&
 245                         bus_addr < res->bus_start + res->size) {
 246                         return bus_addr;
 247                 }
 248         }
 249
 250         printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
 251
 252 Done:
 253         return 0;
 254 }
 255
 256 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 257                                  unsigned long bus_addr,
 258                                  unsigned long flags)
 259 {
 260         struct pci_region *res;
 261         int i;
 262
 263         if (!hose) {
 264                 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
 265                 goto Done;
 266         }
 267
 268         for (i = 0; i < hose->region_count; i++) {
 269                 res = &hose->regions[i];
 270
 271                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 272                         continue;
 273
 274                 if (bus_addr >= res->bus_start &&
 275                         bus_addr < res->bus_start + res->size) {
 276                         return bus_addr - res->bus_start + res->phys_start;
 277                 }
 278         }
 279
 280         printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
 281
 282 Done:
 283         return 0;
 284 }
 285
 286 /*
 287  *
 288  */
 289
 290 int pci_hose_config_device(struct pci_controller *hose,
 291                            pci_dev_t dev,
 292                            unsigned long io,
 293                            unsigned long mem,
 294                            unsigned long command)
 295 {
 296         unsigned int bar_response, bar_size, bar_value, old_command;
 297         unsigned char pin;
 298         int bar, found_mem64;
 299
 300         debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
 301                 io, mem, command);
 302
 303         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 304
 305         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
 306                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 307                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 308
 309                 if (!bar_response)
 310                         continue;
 311
 312                 found_mem64 = 0;
 313
 314                 /* Check the BAR type and set our address mask */
 315                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 316                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 317                         /* round up region base address to a multiple of size */
 318                         io = ((io - 1) | (bar_size - 1)) + 1;
 319                         bar_value = io;
 320                         /* compute new region base address */
 321                         io = io + bar_size;
 322                 } else {
 323                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 324                                 PCI_BASE_ADDRESS_MEM_TYPE_64)
 325                                 found_mem64 = 1;
 326
 327                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 328
 329                         /* round up region base address to multiple of size */
 330                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 331                         bar_value = mem;
 332                         /* compute new region base address */
 333                         mem = mem + bar_size;
 334                 }
 335
 336                 /* Write it out and update our limit */
 337                 pci_hose_write_config_dword (hose, dev, bar, bar_value);
 338
 339                 if (found_mem64) {
 340                         bar += 4;
 341                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 342                 }
 343         }
 344
 345         /* Configure Cache Line Size Register */
 346         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 347
 348         /* Configure Latency Timer */
 349         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 350
 351         /* Disable interrupt line, if device says it wants to use interrupts */
 352         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 353         if (pin != 0) {
 354                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 355         }
 356
 357         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 358         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 359                                      (old_command & 0xffff0000) | command);
 360
 361         return 0;
 362 }
 363
 364 /*
 365  *
 366  */
 367
 368 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 369                                          unsigned short class,
 370                                          unsigned int vendor,
 371                                          unsigned int device,
 372                                          unsigned int bus,
 373                                          unsigned int dev,
 374                                          unsigned int func)
 375 {
 376         struct pci_config_table *table;
 377
 378         for (table = hose->config_table; table && table->vendor; table++) {
 379                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 380                     (table->device == PCI_ANY_ID || table->device == device) &&
 381                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 382                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 383                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 384                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 385                         return table;
 386                 }
 387         }
 388
 389         return NULL;
 390 }
 391
 392 void pci_cfgfunc_config_device(struct pci_controller *hose,
 393                                pci_dev_t dev,
 394                                struct pci_config_table *entry)
 395 {
 396         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 397 }
 398
 399 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 400                             pci_dev_t dev, struct pci_config_table *entry)
 401 {
 402 }
 403
 404 /*
 405  *
 406  */
 407
 408 /* HJF: Changed this to return int. I think this is required
 409  * to get the correct result when scanning bridges
 410  */
 411 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 412 extern void pciauto_config_init(struct pci_controller *hose);
 413
 414 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 415 {
 416         unsigned int sub_bus, found_multi=0;
 417         unsigned short vendor, device, class;
 418         unsigned char header_type;
 419         struct pci_config_table *cfg;
 420         pci_dev_t dev;
 421
 422         sub_bus = bus;
 423
 424         for (dev =  PCI_BDF(bus,0,0);
 425              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 426              dev += PCI_BDF(0,0,1))
 427         {
 428
 429         /* Bus 0 is not necessarily PCI bridge. */
 430 #if defined(CONFIG_PCI_SKIP_HOST_BRIDGE)
 431                 /* Skip our host bridge */
 432                 if ( dev == PCI_BDF(hose->first_busno,0,0) ) {
 433 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE)              /* don't skip host bridge */
 434                         /*
 435                          * Only skip hostbridge configuration if "pciconfighost" is not set
 436                          */
 437                         if (getenv("pciconfighost") == NULL) {
 438                                 continue; /* Skip our host bridge */
 439                         }
 440 #else /* CONFIG_PCI_CONFIG_HOST_BRIDGE */
 441                         continue; /* Skip our host bridge */
 442 #endif /* CONFIG_PCI_CONFIG_HOST_BRIDGE */
 443                 }
 444 #endif /* CONFIG_PCI_SKIP_HOST_BRIDGE */
 445
 446                 if (PCI_FUNC(dev) && !found_multi)
 447                         continue;
 448
 449                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 450
 451                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 452
 453                 if (vendor != 0xffff && vendor != 0x0000) {
 454
 455                         if (!PCI_FUNC(dev))
 456                                 found_multi = header_type & 0x80;
 457
 458                         debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 459                                 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 460
 461                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 462                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 463
 464                         cfg = pci_find_config(hose, class, vendor, device,
 465                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 466                         if (cfg) {
 467                                 cfg->config_device(hose, dev, cfg);
 468                                 sub_bus = max(sub_bus, hose->current_busno);
 469 #ifdef CONFIG_PCI_PNP
 470                         } else {
 471                                 int n = pciauto_config_device(hose, dev);
 472
 473                                 sub_bus = max(sub_bus, n);
 474 #endif
 475                         }
 476                         if (hose->fixup_irq)
 477                                 hose->fixup_irq(hose, dev);
 478
 479 #ifdef CONFIG_PCI_SCAN_SHOW
 480 #if defined(CONFIG_PCI_SKIP_HOST_BRIDGE)
 481                         /* Skip our host bridge */
 482                         if ( dev != PCI_BDF(hose->first_busno,0,0) )
 483 #endif
 484                         {
 485                             unsigned char int_line;
 486
 487                             pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 488                                                       &int_line);
 489                             printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
 490                                    PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 491                                    int_line);
 492                         }
 493 #endif
 494                 }
 495         }
 496
 497         return sub_bus;
 498 }
 499
 500 int pci_hose_scan(struct pci_controller *hose)
 501 {
 502         /* Start scan at current_busno.
 503          * PCIe will start scan at first_busno+1.
 504          */
 505         /* For legacy support, ensure current>=first */
 506         if (hose->first_busno > hose->current_busno)
 507                 hose->current_busno = hose->first_busno;
 508 #ifdef CONFIG_PCI_PNP
 509         pciauto_config_init(hose);
 510 #endif
 511         return pci_hose_scan_bus(hose, hose->current_busno);
 512 }
 513
 514 void pci_init(void)
 515 {
 516 #if defined(CONFIG_PCI_BOOTDELAY)
 517         char *s;
 518         int i;
 519
 520         /* wait "pcidelay" ms (if defined)... */
 521         s = getenv ("pcidelay");
 522         if (s) {
 523                 int val = simple_strtoul (s, NULL, 10);
 524                 for (i=0; i<val; i++)
 525                         udelay (1000);
 526         }
 527 #endif /* CONFIG_PCI_BOOTDELAY */
 528
 529         /* now call board specific pci_init()... */
 530         pci_init_board();
 531 }
 532
 533 #endif /* CONFIG_PCI */