drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <phys2bus.h>
  14 #include <usbroothubdes.h>
  15 #include <asm/io.h>
  16
  17 #include "dwc2.h"
  18
  19 /* Use only HC channel 0. */
  20 #define DWC2_HC_CHANNEL                 0
  21
  22 #define DWC2_STATUS_BUF_SIZE            64
  23 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  24
  25 #define MAX_DEVICE                      16
  26 #define MAX_ENDPOINT                    16
  27
  28 struct dwc2_priv {
  29 #ifdef CONFIG_DM_USB
  30         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(8);
  31         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(8);
  32 #else
  33         uint8_t *aligned_buffer;
  34         uint8_t *status_buffer;
  35 #endif
  36         int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  37         struct dwc2_core_regs *regs;
  38         int root_hub_devnum;
  39 };
  40
  41 #ifndef CONFIG_DM_USB
  42 /* We need doubleword-aligned buffers for DMA transfers */
  43 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 8);
  44 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 8);
  45
  46 static struct dwc2_priv local;
  47 #endif
  48
  49 /*
  50  * DWC2 IP interface
  51  */
  52 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  53 {
  54         unsigned int timeout = 1000000;
  55         uint32_t val;
  56
  57         while (--timeout) {
  58                 val = readl(reg);
  59                 if (!set)
  60                         val = ~val;
  61
  62                 if ((val & mask) == mask)
  63                         return 0;
  64
  65                 udelay(1);
  66         }
  67
  68         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  69               __func__, reg, mask, set);
  70
  71         return -ETIMEDOUT;
  72 }
  73
  74 /*
  75  * Initializes the FSLSPClkSel field of the HCFG register
  76  * depending on the PHY type.
  77  */
  78 static void init_fslspclksel(struct dwc2_core_regs *regs)
  79 {
  80         uint32_t phyclk;
  81
  82 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  83         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  84 #else
  85         /* High speed PHY running at full speed or high speed */
  86         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  87 #endif
  88
  89 #ifdef CONFIG_DWC2_ULPI_FS_LS
  90         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  91         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  92                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  93         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  94                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  95
  96         if (hval == 2 && fval == 1)
  97                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  98 #endif
  99
 100         clrsetbits_le32(&regs->host_regs.hcfg,
 101                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 102                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 103 }
 104
 105 /*
 106  * Flush a Tx FIFO.
 107  *
 108  * @param regs Programming view of DWC_otg controller.
 109  * @param num Tx FIFO to flush.
 110  */
 111 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 112 {
 113         int ret;
 114
 115         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 116                &regs->grstctl);
 117         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 118         if (ret)
 119                 printf("%s: Timeout!\n", __func__);
 120
 121         /* Wait for 3 PHY Clocks */
 122         udelay(1);
 123 }
 124
 125 /*
 126  * Flush Rx FIFO.
 127  *
 128  * @param regs Programming view of DWC_otg controller.
 129  */
 130 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 131 {
 132         int ret;
 133
 134         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 135         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 136         if (ret)
 137                 printf("%s: Timeout!\n", __func__);
 138
 139         /* Wait for 3 PHY Clocks */
 140         udelay(1);
 141 }
 142
 143 /*
 144  * Do core a soft reset of the core.  Be careful with this because it
 145  * resets all the internal state machines of the core.
 146  */
 147 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 148 {
 149         int ret;
 150
 151         /* Wait for AHB master IDLE state. */
 152         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 153         if (ret)
 154                 printf("%s: Timeout!\n", __func__);
 155
 156         /* Core Soft Reset */
 157         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 158         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 159         if (ret)
 160                 printf("%s: Timeout!\n", __func__);
 161
 162         /*
 163          * Wait for core to come out of reset.
 164          * NOTE: This long sleep is _very_ important, otherwise the core will
 165          *       not stay in host mode after a connector ID change!
 166          */
 167         mdelay(100);
 168 }
 169
 170 /*
 171  * This function initializes the DWC_otg controller registers for
 172  * host mode.
 173  *
 174  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 175  * request queues. Host channels are reset to ensure that they are ready for
 176  * performing transfers.
 177  *
 178  * @param regs Programming view of DWC_otg controller
 179  *
 180  */
 181 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 182 {
 183         uint32_t nptxfifosize = 0;
 184         uint32_t ptxfifosize = 0;
 185         uint32_t hprt0 = 0;
 186         int i, ret, num_channels;
 187
 188         /* Restart the Phy Clock */
 189         writel(0, &regs->pcgcctl);
 190
 191         /* Initialize Host Configuration Register */
 192         init_fslspclksel(regs);
 193 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 194         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 195 #endif
 196
 197         /* Configure data FIFO sizes */
 198 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 199         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 200                 /* Rx FIFO */
 201                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 202
 203                 /* Non-periodic Tx FIFO */
 204                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 205                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 206                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 207                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 208                 writel(nptxfifosize, &regs->gnptxfsiz);
 209
 210                 /* Periodic Tx FIFO */
 211                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 212                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 213                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 214                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 215                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 216                 writel(ptxfifosize, &regs->hptxfsiz);
 217         }
 218 #endif
 219
 220         /* Clear Host Set HNP Enable in the OTG Control Register */
 221         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 222
 223         /* Make sure the FIFOs are flushed. */
 224         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 225         dwc_otg_flush_rx_fifo(regs);
 226
 227         /* Flush out any leftover queued requests. */
 228         num_channels = readl(&regs->ghwcfg2);
 229         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 230         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 231         num_channels += 1;
 232
 233         for (i = 0; i < num_channels; i++)
 234                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 235                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 236                                 DWC2_HCCHAR_CHDIS);
 237
 238         /* Halt all channels to put them into a known state. */
 239         for (i = 0; i < num_channels; i++) {
 240                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 241                                 DWC2_HCCHAR_EPDIR,
 242                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 243                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 244                                    DWC2_HCCHAR_CHEN, 0);
 245                 if (ret)
 246                         printf("%s: Timeout!\n", __func__);
 247         }
 248
 249         /* Turn on the vbus power. */
 250         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 251                 hprt0 = readl(&regs->hprt0);
 252                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 253                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 254                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 255                         hprt0 |= DWC2_HPRT0_PRTPWR;
 256                         writel(hprt0, &regs->hprt0);
 257                 }
 258         }
 259 }
 260
 261 /*
 262  * This function initializes the DWC_otg controller registers and
 263  * prepares the core for device mode or host mode operation.
 264  *
 265  * @param regs Programming view of the DWC_otg controller
 266  */
 267 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 268 {
 269         uint32_t ahbcfg = 0;
 270         uint32_t usbcfg = 0;
 271         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 272
 273         /* Common Initialization */
 274         usbcfg = readl(&regs->gusbcfg);
 275
 276         /* Program the ULPI External VBUS bit if needed */
 277 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 278         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 279 #else
 280         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 281 #endif
 282
 283         /* Set external TS Dline pulsing */
 284 #ifdef CONFIG_DWC2_TS_DLINE
 285         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 286 #else
 287         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 288 #endif
 289         writel(usbcfg, &regs->gusbcfg);
 290
 291         /* Reset the Controller */
 292         dwc_otg_core_reset(regs);
 293
 294         /*
 295          * This programming sequence needs to happen in FS mode before
 296          * any other programming occurs
 297          */
 298 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 299         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 300         /* If FS mode with FS PHY */
 301         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 302
 303         /* Reset after a PHY select */
 304         dwc_otg_core_reset(regs);
 305
 306         /*
 307          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 308          * Also do this on HNP Dev/Host mode switches (done in dev_init
 309          * and host_init).
 310          */
 311         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 312                 init_fslspclksel(regs);
 313
 314 #ifdef CONFIG_DWC2_I2C_ENABLE
 315         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 316         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 317
 318         /* Program GI2CCTL.I2CEn */
 319         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 320                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 321                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 322         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 323 #endif
 324
 325 #else
 326         /* High speed PHY. */
 327
 328         /*
 329          * HS PHY parameters. These parameters are preserved during
 330          * soft reset so only program the first time. Do a soft reset
 331          * immediately after setting phyif.
 332          */
 333         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 334         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 335
 336         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 337 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 338                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 339 #else
 340                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 341 #endif
 342         } else {        /* UTMI+ interface */
 343 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 344                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 345 #endif
 346         }
 347
 348         writel(usbcfg, &regs->gusbcfg);
 349
 350         /* Reset after setting the PHY parameters */
 351         dwc_otg_core_reset(regs);
 352 #endif
 353
 354         usbcfg = readl(&regs->gusbcfg);
 355         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 356 #ifdef CONFIG_DWC2_ULPI_FS_LS
 357         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 358         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 359                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 360         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 361                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 362         if (hval == 2 && fval == 1) {
 363                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 364                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 365         }
 366 #endif
 367         writel(usbcfg, &regs->gusbcfg);
 368
 369         /* Program the GAHBCFG Register. */
 370         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 371         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 372                 break;
 373         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 374                 while (brst_sz > 1) {
 375                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 376                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 377                         brst_sz >>= 1;
 378                 }
 379
 380 #ifdef CONFIG_DWC2_DMA_ENABLE
 381                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 382 #endif
 383                 break;
 384
 385         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 386                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 387 #ifdef CONFIG_DWC2_DMA_ENABLE
 388                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 389 #endif
 390                 break;
 391         }
 392
 393         writel(ahbcfg, &regs->gahbcfg);
 394
 395         /* Program the GUSBCFG register for HNP/SRP. */
 396         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 397
 398 #ifdef CONFIG_DWC2_IC_USB_CAP
 399         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 400 #endif
 401 }
 402
 403 /*
 404  * Prepares a host channel for transferring packets to/from a specific
 405  * endpoint. The HCCHARn register is set up with the characteristics specified
 406  * in _hc. Host channel interrupts that may need to be serviced while this
 407  * transfer is in progress are enabled.
 408  *
 409  * @param regs Programming view of DWC_otg controller
 410  * @param hc Information needed to initialize the host channel
 411  */
 412 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 413                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 414                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 415 {
 416         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 417         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 418                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 419                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 420                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 421                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 422
 423         if (dev->speed == USB_SPEED_LOW)
 424                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 425
 426         /* Clear old interrupt conditions for this host channel. */
 427         writel(0x3fff, &hc_regs->hcint);
 428
 429         /*
 430          * Program the HCCHARn register with the endpoint characteristics
 431          * for the current transfer.
 432          */
 433         writel(hcchar, &hc_regs->hcchar);
 434
 435         /* Program the HCSPLIT register for SPLITs */
 436         writel(0, &hc_regs->hcsplt);
 437 }
 438
 439 /*
 440  * DWC2 to USB API interface
 441  */
 442 /* Direction: In ; Request: Status */
 443 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 444                                            struct usb_device *dev, void *buffer,
 445                                            int txlen, struct devrequest *cmd)
 446 {
 447         uint32_t hprt0 = 0;
 448         uint32_t port_status = 0;
 449         uint32_t port_change = 0;
 450         int len = 0;
 451         int stat = 0;
 452
 453         switch (cmd->requesttype & ~USB_DIR_IN) {
 454         case 0:
 455                 *(uint16_t *)buffer = cpu_to_le16(1);
 456                 len = 2;
 457                 break;
 458         case USB_RECIP_INTERFACE:
 459         case USB_RECIP_ENDPOINT:
 460                 *(uint16_t *)buffer = cpu_to_le16(0);
 461                 len = 2;
 462                 break;
 463         case USB_TYPE_CLASS:
 464                 *(uint32_t *)buffer = cpu_to_le32(0);
 465                 len = 4;
 466                 break;
 467         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 468                 hprt0 = readl(&regs->hprt0);
 469                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 470                         port_status |= USB_PORT_STAT_CONNECTION;
 471                 if (hprt0 & DWC2_HPRT0_PRTENA)
 472                         port_status |= USB_PORT_STAT_ENABLE;
 473                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 474                         port_status |= USB_PORT_STAT_SUSPEND;
 475                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 476                         port_status |= USB_PORT_STAT_OVERCURRENT;
 477                 if (hprt0 & DWC2_HPRT0_PRTRST)
 478                         port_status |= USB_PORT_STAT_RESET;
 479                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 480                         port_status |= USB_PORT_STAT_POWER;
 481
 482                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 483                         port_status |= USB_PORT_STAT_LOW_SPEED;
 484                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 485                          DWC2_HPRT0_PRTSPD_HIGH)
 486                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 487
 488                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 489                         port_change |= USB_PORT_STAT_C_ENABLE;
 490                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 491                         port_change |= USB_PORT_STAT_C_CONNECTION;
 492                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 493                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 494
 495                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 496                                         (port_change << 16));
 497                 len = 4;
 498                 break;
 499         default:
 500                 puts("unsupported root hub command\n");
 501                 stat = USB_ST_STALLED;
 502         }
 503
 504         dev->act_len = min(len, txlen);
 505         dev->status = stat;
 506
 507         return stat;
 508 }
 509
 510 /* Direction: In ; Request: Descriptor */
 511 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 512                                                void *buffer, int txlen,
 513                                                struct devrequest *cmd)
 514 {
 515         unsigned char data[32];
 516         uint32_t dsc;
 517         int len = 0;
 518         int stat = 0;
 519         uint16_t wValue = cpu_to_le16(cmd->value);
 520         uint16_t wLength = cpu_to_le16(cmd->length);
 521
 522         switch (cmd->requesttype & ~USB_DIR_IN) {
 523         case 0:
 524                 switch (wValue & 0xff00) {
 525                 case 0x0100:    /* device descriptor */
 526                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 527                         memcpy(buffer, root_hub_dev_des, len);
 528                         break;
 529                 case 0x0200:    /* configuration descriptor */
 530                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 531                         memcpy(buffer, root_hub_config_des, len);
 532                         break;
 533                 case 0x0300:    /* string descriptors */
 534                         switch (wValue & 0xff) {
 535                         case 0x00:
 536                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 537                                            (int)wLength);
 538                                 memcpy(buffer, root_hub_str_index0, len);
 539                                 break;
 540                         case 0x01:
 541                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 542                                            (int)wLength);
 543                                 memcpy(buffer, root_hub_str_index1, len);
 544                                 break;
 545                         }
 546                         break;
 547                 default:
 548                         stat = USB_ST_STALLED;
 549                 }
 550                 break;
 551
 552         case USB_TYPE_CLASS:
 553                 /* Root port config, set 1 port and nothing else. */
 554                 dsc = 0x00000001;
 555
 556                 data[0] = 9;            /* min length; */
 557                 data[1] = 0x29;
 558                 data[2] = dsc & RH_A_NDP;
 559                 data[3] = 0;
 560                 if (dsc & RH_A_PSM)
 561                         data[3] |= 0x1;
 562                 if (dsc & RH_A_NOCP)
 563                         data[3] |= 0x10;
 564                 else if (dsc & RH_A_OCPM)
 565                         data[3] |= 0x8;
 566
 567                 /* corresponds to data[4-7] */
 568                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 569                 data[7] = dsc & RH_B_DR;
 570                 if (data[2] < 7) {
 571                         data[8] = 0xff;
 572                 } else {
 573                         data[0] += 2;
 574                         data[8] = (dsc & RH_B_DR) >> 8;
 575                         data[9] = 0xff;
 576                         data[10] = data[9];
 577                 }
 578
 579                 len = min3(txlen, (int)data[0], (int)wLength);
 580                 memcpy(buffer, data, len);
 581                 break;
 582         default:
 583                 puts("unsupported root hub command\n");
 584                 stat = USB_ST_STALLED;
 585         }
 586
 587         dev->act_len = min(len, txlen);
 588         dev->status = stat;
 589
 590         return stat;
 591 }
 592
 593 /* Direction: In ; Request: Configuration */
 594 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 595                                                   void *buffer, int txlen,
 596                                                   struct devrequest *cmd)
 597 {
 598         int len = 0;
 599         int stat = 0;
 600
 601         switch (cmd->requesttype & ~USB_DIR_IN) {
 602         case 0:
 603                 *(uint8_t *)buffer = 0x01;
 604                 len = 1;
 605                 break;
 606         default:
 607                 puts("unsupported root hub command\n");
 608                 stat = USB_ST_STALLED;
 609         }
 610
 611         dev->act_len = min(len, txlen);
 612         dev->status = stat;
 613
 614         return stat;
 615 }
 616
 617 /* Direction: In */
 618 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 619                                     struct usb_device *dev, void *buffer,
 620                                     int txlen, struct devrequest *cmd)
 621 {
 622         switch (cmd->request) {
 623         case USB_REQ_GET_STATUS:
 624                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 625                                                        txlen, cmd);
 626         case USB_REQ_GET_DESCRIPTOR:
 627                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 628                                                            txlen, cmd);
 629         case USB_REQ_GET_CONFIGURATION:
 630                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 631                                                               txlen, cmd);
 632         default:
 633                 puts("unsupported root hub command\n");
 634                 return USB_ST_STALLED;
 635         }
 636 }
 637
 638 /* Direction: Out */
 639 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 640                                      struct usb_device *dev,
 641                                      void *buffer, int txlen,
 642                                      struct devrequest *cmd)
 643 {
 644         struct dwc2_core_regs *regs = priv->regs;
 645         int len = 0;
 646         int stat = 0;
 647         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 648         uint16_t wValue = cpu_to_le16(cmd->value);
 649
 650         switch (bmrtype_breq & ~USB_DIR_IN) {
 651         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 652         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 653                 break;
 654
 655         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 656                 switch (wValue) {
 657                 case USB_PORT_FEAT_C_CONNECTION:
 658                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 659                         break;
 660                 }
 661                 break;
 662
 663         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 664                 switch (wValue) {
 665                 case USB_PORT_FEAT_SUSPEND:
 666                         break;
 667
 668                 case USB_PORT_FEAT_RESET:
 669                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 670                                         DWC2_HPRT0_PRTCONNDET |
 671                                         DWC2_HPRT0_PRTENCHNG |
 672                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 673                                         DWC2_HPRT0_PRTRST);
 674                         mdelay(50);
 675                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 676                         break;
 677
 678                 case USB_PORT_FEAT_POWER:
 679                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 680                                         DWC2_HPRT0_PRTCONNDET |
 681                                         DWC2_HPRT0_PRTENCHNG |
 682                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 683                                         DWC2_HPRT0_PRTRST);
 684                         break;
 685
 686                 case USB_PORT_FEAT_ENABLE:
 687                         break;
 688                 }
 689                 break;
 690         case (USB_REQ_SET_ADDRESS << 8):
 691                 priv->root_hub_devnum = wValue;
 692                 break;
 693         case (USB_REQ_SET_CONFIGURATION << 8):
 694                 break;
 695         default:
 696                 puts("unsupported root hub command\n");
 697                 stat = USB_ST_STALLED;
 698         }
 699
 700         len = min(len, txlen);
 701
 702         dev->act_len = len;
 703         dev->status = stat;
 704
 705         return stat;
 706 }
 707
 708 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 709                                  unsigned long pipe, void *buffer, int txlen,
 710                                  struct devrequest *cmd)
 711 {
 712         int stat = 0;
 713
 714         if (usb_pipeint(pipe)) {
 715                 puts("Root-Hub submit IRQ: NOT implemented\n");
 716                 return 0;
 717         }
 718
 719         if (cmd->requesttype & USB_DIR_IN)
 720                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 721         else
 722                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 723
 724         mdelay(1);
 725
 726         return stat;
 727 }
 728
 729 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
 730                     bool ignore_ack)
 731 {
 732         uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
 733         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 734         int ret;
 735         uint32_t hcint, hctsiz;
 736
 737         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 738         if (ret)
 739                 return ret;
 740
 741         hcint = readl(&hc_regs->hcint);
 742         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 743                 return -EAGAIN;
 744         if (ignore_ack)
 745                 hcint &= ~DWC2_HCINT_ACK;
 746         else
 747                 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
 748         if (hcint != hcint_comp_hlt_ack) {
 749                 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 750                 return -EINVAL;
 751         }
 752
 753         hctsiz = readl(&hc_regs->hctsiz);
 754         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 755                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 756         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 757
 758         debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
 759
 760         return 0;
 761 }
 762
 763 static int dwc2_eptype[] = {
 764         DWC2_HCCHAR_EPTYPE_ISOC,
 765         DWC2_HCCHAR_EPTYPE_INTR,
 766         DWC2_HCCHAR_EPTYPE_CONTROL,
 767         DWC2_HCCHAR_EPTYPE_BULK,
 768 };
 769
 770 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 771               unsigned long pipe, int *pid, int in, void *buffer, int len,
 772               bool ignore_ack)
 773 {
 774         struct dwc2_core_regs *regs = priv->regs;
 775         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 776         int devnum = usb_pipedevice(pipe);
 777         int ep = usb_pipeendpoint(pipe);
 778         int max = usb_maxpacket(dev, pipe);
 779         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 780         int done = 0;
 781         int ret = 0;
 782         uint32_t sub;
 783         uint32_t xfer_len;
 784         uint32_t num_packets;
 785         int stop_transfer = 0;
 786
 787         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 788               in, len);
 789
 790         do {
 791                 /* Initialize channel */
 792                 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 793                                 eptype, max);
 794
 795                 xfer_len = len - done;
 796                 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 797                         xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
 798                 if (xfer_len > DWC2_DATA_BUF_SIZE)
 799                         xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 800
 801                 /* Make sure that xfer_len is a multiple of max packet size. */
 802                 if (xfer_len > 0) {
 803                         num_packets = (xfer_len + max - 1) / max;
 804                         if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
 805                                 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
 806                                 xfer_len = num_packets * max;
 807                         }
 808                 } else {
 809                         num_packets = 1;
 810                 }
 811
 812                 if (in)
 813                         xfer_len = num_packets * max;
 814
 815                 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 816                       *pid, xfer_len, num_packets);
 817
 818                 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 819                        (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 820                        (*pid << DWC2_HCTSIZ_PID_OFFSET),
 821                        &hc_regs->hctsiz);
 822
 823                 if (!in) {
 824                         memcpy(priv->aligned_buffer, (char *)buffer + done,
 825                                len);
 826                 }
 827
 828                 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
 829                        &hc_regs->hcdma);
 830
 831                 /* Set host channel enable after all other setup is complete. */
 832                 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 833                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 834                                 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 835                                 DWC2_HCCHAR_CHEN);
 836
 837                 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
 838                 if (ret)
 839                         break;
 840
 841                 if (in) {
 842                         xfer_len -= sub;
 843                         memcpy(buffer + done, priv->aligned_buffer, xfer_len);
 844                         if (sub)
 845                                 stop_transfer = 1;
 846                 }
 847
 848                 done += xfer_len;
 849
 850         } while ((done < len) && !stop_transfer);
 851
 852         writel(0, &hc_regs->hcintmsk);
 853         writel(0xFFFFFFFF, &hc_regs->hcint);
 854
 855         dev->status = 0;
 856         dev->act_len = done;
 857
 858         return ret;
 859 }
 860
 861 /* U-Boot USB transmission interface */
 862 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 863                      unsigned long pipe, void *buffer, int len)
 864 {
 865         int devnum = usb_pipedevice(pipe);
 866         int ep = usb_pipeendpoint(pipe);
 867
 868         if (devnum == priv->root_hub_devnum) {
 869                 dev->status = 0;
 870                 return -EINVAL;
 871         }
 872
 873         return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
 874                          usb_pipein(pipe), buffer, len, true);
 875 }
 876
 877 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
 878                                unsigned long pipe, void *buffer, int len,
 879                                struct devrequest *setup)
 880 {
 881         int devnum = usb_pipedevice(pipe);
 882         int pid, ret, act_len;
 883         /* For CONTROL endpoint pid should start with DATA1 */
 884         int status_direction;
 885
 886         if (devnum == priv->root_hub_devnum) {
 887                 dev->status = 0;
 888                 dev->speed = USB_SPEED_HIGH;
 889                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
 890                                              setup);
 891         }
 892
 893         pid = DWC2_HC_PID_SETUP;
 894         ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
 895         if (ret)
 896                 return ret;
 897
 898         if (buffer) {
 899                 pid = DWC2_HC_PID_DATA1;
 900                 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
 901                                 len, false);
 902                 if (ret)
 903                         return ret;
 904                 act_len = dev->act_len;
 905         } /* End of DATA stage */
 906         else
 907                 act_len = 0;
 908
 909         /* STATUS stage */
 910         if ((len == 0) || usb_pipeout(pipe))
 911                 status_direction = 1;
 912         else
 913                 status_direction = 0;
 914
 915         pid = DWC2_HC_PID_DATA1;
 916         ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
 917                         priv->status_buffer, 0, false);
 918         if (ret)
 919                 return ret;
 920
 921         dev->act_len = act_len;
 922
 923         return 0;
 924 }
 925
 926 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
 927                     unsigned long pipe, void *buffer, int len, int interval)
 928 {
 929         unsigned long timeout;
 930         int ret;
 931
 932         /* FIXME: what is interval? */
 933
 934         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 935         for (;;) {
 936                 if (get_timer(0) > timeout) {
 937                         printf("Timeout poll on interrupt endpoint\n");
 938                         return -ETIMEDOUT;
 939                 }
 940                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
 941                 if (ret != -EAGAIN)
 942                         return ret;
 943         }
 944 }
 945
 946 static int dwc2_init_common(struct dwc2_priv *priv)
 947 {
 948         struct dwc2_core_regs *regs = priv->regs;
 949         uint32_t snpsid;
 950         int i, j;
 951
 952         snpsid = readl(&regs->gsnpsid);
 953         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
 954
 955         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
 956             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
 957                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
 958                 return -ENODEV;
 959         }
 960
 961         dwc_otg_core_init(regs);
 962         dwc_otg_core_host_init(regs);
 963
 964         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 965                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 966                         DWC2_HPRT0_PRTOVRCURRCHNG,
 967                         DWC2_HPRT0_PRTRST);
 968         mdelay(50);
 969         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
 970                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
 971                      DWC2_HPRT0_PRTRST);
 972
 973         for (i = 0; i < MAX_DEVICE; i++) {
 974                 for (j = 0; j < MAX_ENDPOINT; j++)
 975                         priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
 976         }
 977
 978         return 0;
 979 }
 980
 981 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
 982 {
 983         /* Put everything in reset. */
 984         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 985                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 986                         DWC2_HPRT0_PRTOVRCURRCHNG,
 987                         DWC2_HPRT0_PRTRST);
 988 }
 989
 990 #ifndef CONFIG_DM_USB
 991 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 992                        int len, struct devrequest *setup)
 993 {
 994         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
 995 }
 996
 997 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 998                     int len)
 999 {
1000         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1001 }
1002
1003 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1004                    int len, int interval)
1005 {
1006         return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1007 }
1008
1009 /* U-Boot USB control interface */
1010 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1011 {
1012         struct dwc2_priv *priv = &local;
1013
1014         memset(priv, '\0', sizeof(*priv));
1015         priv->root_hub_devnum = 0;
1016         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1017         priv->aligned_buffer = aligned_buffer_addr;
1018         priv->status_buffer = status_buffer_addr;
1019
1020         /* board-dependant init */
1021         if (board_usb_init(index, USB_INIT_HOST))
1022                 return -1;
1023
1024         return dwc2_init_common(priv);
1025 }
1026
1027 int usb_lowlevel_stop(int index)
1028 {
1029         dwc2_uninit_common(local.regs);
1030
1031         return 0;
1032 }
1033 #endif
1034
1035 #ifdef CONFIG_DM_USB
1036 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1037                                    unsigned long pipe, void *buffer, int length,
1038                                    struct devrequest *setup)
1039 {
1040         struct dwc2_priv *priv = dev_get_priv(dev);
1041
1042         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1043               dev->name, udev, udev->dev->name, udev->portnr);
1044
1045         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1046 }
1047
1048 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1049                                 unsigned long pipe, void *buffer, int length)
1050 {
1051         struct dwc2_priv *priv = dev_get_priv(dev);
1052
1053         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1054
1055         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1056 }
1057
1058 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1059                                unsigned long pipe, void *buffer, int length,
1060                                int interval)
1061 {
1062         struct dwc2_priv *priv = dev_get_priv(dev);
1063
1064         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1065
1066         return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1067 }
1068
1069 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1070 {
1071         struct dwc2_priv *priv = dev_get_priv(dev);
1072         fdt_addr_t addr;
1073
1074         addr = dev_get_addr(dev);
1075         if (addr == FDT_ADDR_T_NONE)
1076                 return -EINVAL;
1077         priv->regs = (struct dwc2_core_regs *)addr;
1078
1079         return 0;
1080 }
1081
1082 static int dwc2_usb_probe(struct udevice *dev)
1083 {
1084         struct dwc2_priv *priv = dev_get_priv(dev);
1085
1086         return dwc2_init_common(priv);
1087 }
1088
1089 static int dwc2_usb_remove(struct udevice *dev)
1090 {
1091         struct dwc2_priv *priv = dev_get_priv(dev);
1092
1093         dwc2_uninit_common(priv->regs);
1094
1095         return 0;
1096 }
1097
1098 struct dm_usb_ops dwc2_usb_ops = {
1099         .control = dwc2_submit_control_msg,
1100         .bulk = dwc2_submit_bulk_msg,
1101         .interrupt = dwc2_submit_int_msg,
1102 };
1103
1104 static const struct udevice_id dwc2_usb_ids[] = {
1105         { .compatible = "brcm,bcm2835-usb" },
1106         { }
1107 };
1108
1109 U_BOOT_DRIVER(usb_dwc2) = {
1110         .name   = "dwc2_exynos",
1111         .id     = UCLASS_USB,
1112         .of_match = dwc2_usb_ids,
1113         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1114         .probe  = dwc2_usb_probe,
1115         .remove = dwc2_usb_remove,
1116         .ops    = &dwc2_usb_ops,
1117         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1118         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1119 };
1120 #endif