2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
14 * Added include for hardware.h (for __REG definition)
22 /* FIXME hack so that SA-1111.h will work [cb] */
25 typedef unsigned short Word16 ;
26 typedef unsigned int Word32 ;
28 typedef Word Quad [4] ;
29 typedef void *Address ;
30 typedef void (*ExcpHndlr) (void) ;
36 #define PXA_CS0_PHYS 0x00000000
37 #define PXA_CS1_PHYS 0x04000000
38 #define PXA_CS2_PHYS 0x08000000
39 #define PXA_CS3_PHYS 0x0C000000
40 #define PXA_CS4_PHYS 0x10000000
41 #define PXA_CS5_PHYS 0x14000000
44 * Personal Computer Memory Card International Association (PCMCIA) sockets
46 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
47 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
48 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
49 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
50 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
52 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
53 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
54 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
55 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
57 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
58 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
59 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
60 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
62 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
63 (0x20000000 + (Nb)*PCMCIASp)
64 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
65 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
66 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
67 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
68 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
70 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
71 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
72 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
73 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
75 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
76 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
77 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
78 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
83 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
84 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
85 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
86 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
87 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
88 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
89 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
90 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
91 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
92 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
93 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
94 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
95 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
96 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
97 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
98 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
100 #define DCSR(x) __REG2(0x40000000, (x) << 2)
102 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
103 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
104 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
106 #if defined(CONFIG_PXA27X)
107 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
108 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
109 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
110 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
111 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
112 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
113 #define DCSR_ENRINTR (1 << 9) /* The end of Receive */
116 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
117 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
118 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
119 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
120 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
122 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
124 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
125 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
126 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
127 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
128 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
129 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
130 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
131 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
132 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
133 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
134 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
135 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
136 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
137 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
138 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
139 #define DRCMR15 __REG(0x4000013c) /* Reserved */
140 #define DRCMR16 __REG(0x40000140) /* Reserved */
141 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
142 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
143 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
144 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
145 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
146 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
147 #define DRCMR23 __REG(0x4000015c) /* Reserved */
148 #define DRCMR24 __REG(0x40000160) /* Reserved */
149 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
150 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
151 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
152 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
153 #define DRCMR29 __REG(0x40000174) /* Reserved */
154 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
155 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
156 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
157 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
158 #define DRCMR34 __REG(0x40000188) /* Reserved */
159 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
160 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
161 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
162 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
163 #define DRCMR39 __REG(0x4000019C) /* Reserved */
165 #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
166 #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
167 #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
169 #define DRCMRRXSADR DRCMR2
170 #define DRCMRTXSADR DRCMR3
171 #define DRCMRRXBTRBR DRCMR4
172 #define DRCMRTXBTTHR DRCMR5
173 #define DRCMRRXFFRBR DRCMR6
174 #define DRCMRTXFFTHR DRCMR7
175 #define DRCMRRXMCDR DRCMR8
176 #define DRCMRRXMODR DRCMR9
177 #define DRCMRTXMODR DRCMR10
178 #define DRCMRRXPCDR DRCMR11
179 #define DRCMRTXPCDR DRCMR12
180 #define DRCMRRXSSDR DRCMR13
181 #define DRCMRTXSSDR DRCMR14
182 #define DRCMRRXICDR DRCMR17
183 #define DRCMRTXICDR DRCMR18
184 #define DRCMRRXSTRBR DRCMR19
185 #define DRCMRTXSTTHR DRCMR20
186 #define DRCMRRXMMC DRCMR21
187 #define DRCMRTXMMC DRCMR22
189 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
190 #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
192 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
193 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
194 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
195 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
196 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
197 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
198 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
199 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
200 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
201 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
202 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
203 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
204 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
205 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
206 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
207 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
208 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
209 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
210 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
211 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
212 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
213 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
214 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
215 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
216 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
217 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
218 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
219 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
220 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
221 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
222 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
223 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
224 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
225 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
226 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
227 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
228 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
229 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
230 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
231 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
232 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
233 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
234 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
235 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
236 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
237 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
238 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
239 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
240 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
241 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
242 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
243 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
244 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
245 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
246 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
247 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
248 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
249 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
250 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
251 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
252 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
253 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
254 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
255 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
257 #define DDADR(x) __REG2(0x40000200, (x) << 4)
258 #define DSADR(x) __REG2(0x40000204, (x) << 4)
259 #define DTADR(x) __REG2(0x40000208, (x) << 4)
260 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
262 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
263 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
265 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
266 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
267 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
268 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
269 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
270 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
271 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
272 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
273 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
274 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
275 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
276 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
277 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
278 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
280 /* default combinations */
281 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
282 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
283 #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
288 /* Full Function UART (FFUART) */
290 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
291 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
292 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
293 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
294 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
295 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
296 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
297 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
298 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
299 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
300 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
301 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
302 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
304 /* Bluetooth UART (BTUART) */
306 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
307 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
308 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
309 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
310 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
311 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
312 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
313 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
314 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
315 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
316 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
317 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
318 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
320 /* Standard UART (STUART) */
322 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
323 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
324 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
325 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
326 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
327 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
328 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
329 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
330 #define STMSR __REG(0x40700018) /* Reserved */
331 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
332 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
333 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
334 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
336 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
337 #define IER_UUE (1 << 6) /* UART Unit Enable */
338 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
339 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
340 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
341 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
342 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
343 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
345 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
346 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
347 #define IIR_TOD (1 << 3) /* Time Out Detected */
348 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
349 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
350 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
352 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
353 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
354 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
355 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
356 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
357 #define FCR_ITL_1 (0)
358 #define FCR_ITL_8 (FCR_ITL1)
359 #define FCR_ITL_16 (FCR_ITL2)
360 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
362 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
363 #define LCR_SB (1 << 6) /* Set Break */
364 #define LCR_STKYP (1 << 5) /* Sticky Parity */
365 #define LCR_EPS (1 << 4) /* Even Parity Select */
366 #define LCR_PEN (1 << 3) /* Parity Enable */
367 #define LCR_STB (1 << 2) /* Stop Bit */
368 #define LCR_WLS1 (1 << 1) /* Word Length Select */
369 #define LCR_WLS0 (1 << 0) /* Word Length Select */
371 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
372 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
373 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
374 #define LSR_BI (1 << 4) /* Break Interrupt */
375 #define LSR_FE (1 << 3) /* Framing Error */
376 #define LSR_PE (1 << 2) /* Parity Error */
377 #define LSR_OE (1 << 1) /* Overrun Error */
378 #define LSR_DR (1 << 0) /* Data Ready */
380 #define MCR_LOOP (1 << 4) */
381 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
382 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
383 #define MCR_RTS (1 << 1) /* Request to Send */
384 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
386 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
387 #define MSR_RI (1 << 6) /* Ring Indicator */
388 #define MSR_DSR (1 << 5) /* Data Set Ready */
389 #define MSR_CTS (1 << 4) /* Clear To Send */
390 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
391 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
392 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
393 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
396 * IrSR (Infrared Selection Register)
398 #define IrSR_OFFSET 0x20
400 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
401 #define IrSR_RXPL_POS_IS_ZERO 0x0
402 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
403 #define IrSR_TXPL_POS_IS_ZERO 0x0
404 #define IrSR_XMODE_PULSE_1_6 (1<<2)
405 #define IrSR_XMODE_PULSE_3_16 0x0
406 #define IrSR_RCVEIR_IR_MODE (1<<1)
407 #define IrSR_RCVEIR_UART_MODE 0x0
408 #define IrSR_XMITIR_IR_MODE (1<<0)
409 #define IrSR_XMITIR_UART_MODE 0x0
411 #define IrSR_IR_RECEIVE_ON (\
412 IrSR_RXPL_NEG_IS_ZERO | \
413 IrSR_TXPL_POS_IS_ZERO | \
414 IrSR_XMODE_PULSE_3_16 | \
415 IrSR_RCVEIR_IR_MODE | \
416 IrSR_XMITIR_UART_MODE)
418 #define IrSR_IR_TRANSMIT_ON (\
419 IrSR_RXPL_NEG_IS_ZERO | \
420 IrSR_TXPL_POS_IS_ZERO | \
421 IrSR_XMODE_PULSE_3_16 | \
422 IrSR_RCVEIR_UART_MODE | \
428 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
429 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
430 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
431 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
432 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
434 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
435 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
436 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
437 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
438 #define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */
440 /* ----- Control register bits ---------------------------------------- */
442 #define ICR_START 0x1 /* start bit */
443 #define ICR_STOP 0x2 /* stop bit */
444 #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
445 #define ICR_TB 0x8 /* transfer byte bit */
446 #define ICR_MA 0x10 /* master abort */
447 #define ICR_SCLE 0x20 /* master clock enable */
448 #define ICR_IUE 0x40 /* unit enable */
449 #define ICR_GCD 0x80 /* general call disable */
450 #define ICR_ITEIE 0x100 /* enable tx interrupts */
451 #define ICR_IRFIE 0x200 /* enable rx interrupts */
452 #define ICR_BEIE 0x400 /* enable bus error ints */
453 #define ICR_SSDIE 0x800 /* slave STOP detected int enable */
454 #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
455 #define ICR_SADIE 0x2000 /* slave address detected int enable */
456 #define ICR_UR 0x4000 /* unit reset */
457 #define ICR_FM 0x8000 /* Fast Mode */
459 /* ----- Status register bits ----------------------------------------- */
461 #define ISR_RWM 0x1 /* read/write mode */
462 #define ISR_ACKNAK 0x2 /* ack/nak status */
463 #define ISR_UB 0x4 /* unit busy */
464 #define ISR_IBB 0x8 /* bus busy */
465 #define ISR_SSD 0x10 /* slave stop detected */
466 #define ISR_ALD 0x20 /* arbitration loss detected */
467 #define ISR_ITE 0x40 /* tx buffer empty */
468 #define ISR_IRF 0x80 /* rx buffer full */
469 #define ISR_GCAD 0x100 /* general call address detected */
470 #define ISR_SAD 0x200 /* slave address detected */
471 #define ISR_BED 0x400 /* bus error no ACK/NAK */
474 * Serial Audio Controller
476 /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
477 * short defines because there is too much chance of namespace collision
479 /*#define SACR0 __REG(0x40400000) / Global Control Register */
480 /*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
481 /*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
482 /*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */
483 /*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */
484 /*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */
485 /*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */
489 * AC97 Controller registers
491 #define POCR __REG(0x40500000) /* PCM Out Control Register */
492 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
494 #define PICR __REG(0x40500004) /* PCM In Control Register */
495 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
497 #define MCCR __REG(0x40500008) /* Mic In Control Register */
498 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
500 #define GCR __REG(0x4050000C) /* Global Control Register */
501 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
502 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
503 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
504 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
505 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
506 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
507 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
508 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
509 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
510 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
512 #define POSR __REG(0x40500010) /* PCM Out Status Register */
513 #define POSR_FIFOE (1 << 4) /* FIFO error */
515 #define PISR __REG(0x40500014) /* PCM In Status Register */
516 #define PISR_FIFOE (1 << 4) /* FIFO error */
518 #define MCSR __REG(0x40500018) /* Mic In Status Register */
519 #define MCSR_FIFOE (1 << 4) /* FIFO error */
521 #define GSR __REG(0x4050001C) /* Global Status Register */
522 #define GSR_CDONE (1 << 19) /* Command Done */
523 #define GSR_SDONE (1 << 18) /* Status Done */
524 #define GSR_RDCS (1 << 15) /* Read Completion Status */
525 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
526 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
527 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
528 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
529 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
530 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
531 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
532 #define GSR_MINT (1 << 7) /* Mic In Interrupt */
533 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
534 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
535 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
536 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
537 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
539 #define CAR __REG(0x40500020) /* CODEC Access Register */
540 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
542 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
543 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
545 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
546 #define MOCR_FEIE (1 << 3) /* FIFO Error */
548 #define MICR __REG(0x40500108) /* Modem In Control Register */
549 #define MICR_FEIE (1 << 3) /* FIFO Error */
551 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
552 #define MOSR_FIFOE (1 << 4) /* FIFO error */
554 #define MISR __REG(0x40500118) /* Modem In Status Register */
555 #define MISR_FIFOE (1 << 4) /* FIFO error */
557 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
559 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
560 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
561 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
562 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
565 * USB Device Controller
567 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
568 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
569 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
571 #define UDCCR __REG(0x40600000) /* UDC Control Register */
572 #define UDCCR_UDE (1 << 0) /* UDC enable */
573 #define UDCCR_UDA (1 << 1) /* UDC active */
574 #define UDCCR_RSM (1 << 2) /* Device resume */
575 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
576 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
577 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
578 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
579 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */
581 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
582 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
583 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
584 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
585 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
586 #define UDCCS0_SST (1 << 4) /* Sent stall */
587 #define UDCCS0_FST (1 << 5) /* Force stall */
588 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
589 #define UDCCS0_SA (1 << 7) /* Setup active */
591 /* Bulk IN - Endpoint 1,6,11 */
592 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
593 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
594 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
596 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
597 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
598 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
599 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
600 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
601 #define UDCCS_BI_FST (1 << 5) /* Force stall */
602 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
604 /* Bulk OUT - Endpoint 2,7,12 */
605 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
606 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
607 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
609 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
610 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
611 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
612 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
613 #define UDCCS_BO_FST (1 << 5) /* Force stall */
614 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
615 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
617 /* Isochronous IN - Endpoint 3,8,13 */
618 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
619 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
620 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
622 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
623 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
624 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
625 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
626 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
628 /* Isochronous OUT - Endpoint 4,9,14 */
629 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
630 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
631 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
633 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
634 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
635 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
636 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
637 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
638 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
640 /* Interrupt IN - Endpoint 5,10,15 */
641 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
642 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
643 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
645 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
646 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
647 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
648 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
649 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
650 #define UDCCS_INT_FST (1 << 5) /* Force stall */
651 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
653 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
654 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
655 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
656 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
657 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
658 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
659 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
660 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
661 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
662 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
663 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
664 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
665 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
666 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
667 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
668 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
669 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
670 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
671 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
672 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
673 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
674 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
675 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
676 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
678 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
680 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
681 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
682 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
683 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
684 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
685 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
686 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
687 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
689 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
691 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
692 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
693 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
694 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
695 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
696 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
697 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
698 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
700 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
702 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
703 #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
704 #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
705 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
706 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
707 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
708 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
709 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
711 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
713 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
714 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
715 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
716 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
717 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
718 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
719 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
720 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
722 #if defined(CONFIG_PXA27X)
724 * USB Host Controller
726 #define UHCREV __REG(0x4C000000)
727 #define UHCHCON __REG(0x4C000004)
728 #define UHCCOMS __REG(0x4C000008)
729 #define UHCINTS __REG(0x4C00000C)
730 #define UHCINTE __REG(0x4C000010)
731 #define UHCINTD __REG(0x4C000014)
732 #define UHCHCCA __REG(0x4C000018)
733 #define UHCPCED __REG(0x4C00001C)
734 #define UHCCHED __REG(0x4C000020)
735 #define UHCCCED __REG(0x4C000024)
736 #define UHCBHED __REG(0x4C000028)
737 #define UHCBCED __REG(0x4C00002C)
738 #define UHCDHEAD __REG(0x4C000030)
739 #define UHCFMI __REG(0x4C000034)
740 #define UHCFMR __REG(0x4C000038)
741 #define UHCFMN __REG(0x4C00003C)
742 #define UHCPERS __REG(0x4C000040)
743 #define UHCLST __REG(0x4C000044)
744 #define UHCRHDA __REG(0x4C000048)
745 #define UHCRHDB __REG(0x4C00004C)
746 #define UHCRHS __REG(0x4C000050)
747 #define UHCRHPS1 __REG(0x4C000054)
748 #define UHCRHPS2 __REG(0x4C000058)
749 #define UHCRHPS3 __REG(0x4C00005C)
750 #define UHCSTAT __REG(0x4C000060)
751 #define UHCHR __REG(0x4C000064)
752 #define UHCHIE __REG(0x4C000068)
753 #define UHCHIT __REG(0x4C00006C)
755 #define UHCHR_FSBIR (1<<0)
756 #define UHCHR_FHR (1<<1)
757 #define UHCHR_CGR (1<<2)
758 #define UHCHR_SSDC (1<<3)
759 #define UHCHR_UIT (1<<4)
760 #define UHCHR_SSE (1<<5)
761 #define UHCHR_PSPL (1<<6)
762 #define UHCHR_PCPL (1<<7)
763 #define UHCHR_SSEP0 (1<<9)
764 #define UHCHR_SSEP1 (1<<10)
765 #define UHCHR_SSEP2 (1<<11)
767 #define UHCHIE_UPRIE (1<<13)
768 #define UHCHIE_UPS2IE (1<<12)
769 #define UHCHIE_UPS1IE (1<<11)
770 #define UHCHIE_TAIE (1<<10)
771 #define UHCHIE_HBAIE (1<<8)
772 #define UHCHIE_RWIE (1<<7)
777 * Fast Infrared Communication Port
779 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
780 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
781 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
782 #define ICDR __REG(0x4080000c) /* ICP Data Register */
783 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
784 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
789 #define RCNR __REG(0x40900000) /* RTC Count Register */
790 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
791 #define RTSR __REG(0x40900008) /* RTC Status Register */
792 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
793 #define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
794 #define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
795 #define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
796 #define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
797 #define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
798 #define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
799 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
800 #define RDCR __REG(0x40900010) /* RTC Day Count Register. */
801 #define RYCR __REG(0x40900014) /* RTC Year Count Register. */
802 #define SWCR __REG(0x40900028) /* Stopwatch Count Register */
803 #define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
805 #define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
806 #define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
807 #define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
808 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
809 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
810 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
811 #define RTSR_AL (1 << 0) /* RTC alarm detected */
814 * OS Timer & Match Registers
816 #define OSMR0 __REG(0x40A00000) /* */
817 #define OSMR1 __REG(0x40A00004) /* */
818 #define OSMR2 __REG(0x40A00008) /* */
819 #define OSMR3 __REG(0x40A0000C) /* */
820 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
821 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
822 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
823 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
825 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
826 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
827 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
828 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
830 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
832 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
833 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
834 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
835 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
838 * Pulse Width Modulator
840 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
841 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
842 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
844 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
845 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
846 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
849 * Interrupt Controller
851 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
852 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
853 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
854 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
855 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
856 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
859 * General Purpose I/O
861 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
862 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
863 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
865 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
866 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
867 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
869 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
870 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
871 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
873 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
874 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
875 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
877 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
878 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
879 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
881 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
882 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
883 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
885 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
886 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
887 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
889 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
890 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
891 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
892 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
893 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
894 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
896 /* More handy macros. The argument is a literal GPIO number. */
898 #define GPIO_bit(x) (1 << ((x) & 0x1f))
902 /* Interrupt Controller */
904 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
905 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
906 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
907 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
908 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
910 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
911 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
912 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
913 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
914 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
915 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
916 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
917 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
919 #define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
920 #define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
921 #define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
922 #define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
923 #define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
924 #define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
925 #define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
926 #define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
927 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
930 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
931 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
932 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
933 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
934 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
935 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
936 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
937 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
941 /* GPIO alternate function assignments */
943 #define GPIO1_RST 1 /* reset */
944 #define GPIO6_MMCCLK 6 /* MMC Clock */
945 #define GPIO8_48MHz 7 /* 48 MHz clock output */
946 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
947 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
948 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
949 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
950 #define GPIO12_32KHz 12 /* 32 kHz out */
951 #define GPIO13_MBGNT 13 /* memory controller grant */
952 #define GPIO14_MBREQ 14 /* alternate bus master request */
953 #define GPIO15_nCS_1 15 /* chip select 1 */
954 #define GPIO16_PWM0 16 /* PWM0 output */
955 #define GPIO17_PWM1 17 /* PWM1 output */
956 #define GPIO18_RDY 18 /* Ext. Bus Ready */
957 #define GPIO19_DREQ1 19 /* External DMA Request */
958 #define GPIO20_DREQ0 20 /* External DMA Request */
959 #define GPIO23_SCLK 23 /* SSP clock */
960 #define GPIO24_SFRM 24 /* SSP Frame */
961 #define GPIO25_STXD 25 /* SSP transmit */
962 #define GPIO26_SRXD 26 /* SSP receive */
963 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
964 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
965 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
966 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
967 #define GPIO31_SYNC 31 /* AC97/I2S sync */
968 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
969 #define GPIO33_nCS_5 33 /* chip select 5 */
970 #define GPIO34_FFRXD 34 /* FFUART receive */
971 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
972 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
973 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
974 #define GPIO37_FFDSR 37 /* FFUART data set ready */
975 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
976 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
977 #define GPIO39_FFTXD 39 /* FFUART transmit data */
978 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
979 #define GPIO41_FFRTS 41 /* FFUART request to send */
980 #define GPIO42_BTRXD 42 /* BTUART receive data */
981 #define GPIO43_BTTXD 43 /* BTUART transmit data */
982 #define GPIO44_BTCTS 44 /* BTUART clear to send */
983 #define GPIO45_BTRTS 45 /* BTUART request to send */
984 #define GPIO46_ICPRXD 46 /* ICP receive data */
985 #define GPIO46_STRXD 46 /* STD_UART receive data */
986 #define GPIO47_ICPTXD 47 /* ICP transmit data */
987 #define GPIO47_STTXD 47 /* STD_UART transmit data */
988 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
989 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
990 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
991 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
992 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
993 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
994 #define GPIO53_MMCCLK 53 /* MMC Clock */
995 #define GPIO54_MMCCLK 54 /* MMC Clock */
996 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
997 #define GPIO55_nPREG 55 /* Card Address bit 26 */
998 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
999 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1000 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
1001 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
1002 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
1003 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
1004 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
1005 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
1006 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
1007 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
1008 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
1009 #define GPIO66_MBREQ 66 /* alternate bus master req */
1010 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
1011 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1012 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
1013 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1014 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
1015 #define GPIO69_MMCCLK 69 /* MMC_CLK */
1016 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
1017 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1018 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
1019 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1020 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
1021 #define GPIO72_32kHz 72 /* 32 kHz clock */
1022 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
1023 #define GPIO73_MBGNT 73 /* Memory controller grant */
1024 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1025 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
1026 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1027 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1028 #define GPIO78_nCS_2 78 /* chip select 2 */
1029 #define GPIO79_nCS_3 79 /* chip select 3 */
1030 #define GPIO80_nCS_4 80 /* chip select 4 */
1032 /* GPIO alternate function mode & direction */
1034 #define GPIO_IN 0x000
1035 #define GPIO_OUT 0x080
1036 #define GPIO_ALT_FN_1_IN 0x100
1037 #define GPIO_ALT_FN_1_OUT 0x180
1038 #define GPIO_ALT_FN_2_IN 0x200
1039 #define GPIO_ALT_FN_2_OUT 0x280
1040 #define GPIO_ALT_FN_3_IN 0x300
1041 #define GPIO_ALT_FN_3_OUT 0x380
1042 #define GPIO_MD_MASK_NR 0x07f
1043 #define GPIO_MD_MASK_DIR 0x080
1044 #define GPIO_MD_MASK_FN 0x300
1046 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1047 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1048 #define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT)
1049 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1050 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1051 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1052 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1053 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1054 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1055 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1056 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1057 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1058 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1059 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1060 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1061 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1062 #define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
1063 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1064 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1065 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1066 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1067 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1068 #define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1069 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1070 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1071 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1072 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1073 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1074 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1075 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1076 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1077 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1078 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1079 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1080 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1081 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1082 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1083 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1084 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1085 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1086 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1087 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1088 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1089 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1090 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1091 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1092 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1093 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1094 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1095 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1096 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1097 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1098 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1099 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1100 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1101 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1102 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1103 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1104 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1105 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1106 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1107 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1108 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1109 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1110 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1111 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1112 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1113 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1114 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1115 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1116 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1117 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1118 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1119 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1120 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1121 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1122 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1123 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1124 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1125 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1126 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1127 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1128 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1129 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1130 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1131 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1132 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1133 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1134 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1135 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1136 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1137 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
1139 #define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
1140 #define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
1145 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1146 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1147 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1148 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1149 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1150 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1151 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1152 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1153 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1154 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1155 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1156 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1157 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1159 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1160 #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
1161 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
1162 #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
1163 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1164 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1165 #define PCMD(x) __REG(0x40F00080 + x*4)
1166 #define PCMD0 __REG(0x40F00080 + 0 * 4)
1167 #define PCMD1 __REG(0x40F00080 + 1 * 4)
1168 #define PCMD2 __REG(0x40F00080 + 2 * 4)
1169 #define PCMD3 __REG(0x40F00080 + 3 * 4)
1170 #define PCMD4 __REG(0x40F00080 + 4 * 4)
1171 #define PCMD5 __REG(0x40F00080 + 5 * 4)
1172 #define PCMD6 __REG(0x40F00080 + 6 * 4)
1173 #define PCMD7 __REG(0x40F00080 + 7 * 4)
1174 #define PCMD8 __REG(0x40F00080 + 8 * 4)
1175 #define PCMD9 __REG(0x40F00080 + 9 * 4)
1176 #define PCMD10 __REG(0x40F00080 + 10 * 4)
1177 #define PCMD11 __REG(0x40F00080 + 11 * 4)
1178 #define PCMD12 __REG(0x40F00080 + 12 * 4)
1179 #define PCMD13 __REG(0x40F00080 + 13 * 4)
1180 #define PCMD14 __REG(0x40F00080 + 14 * 4)
1181 #define PCMD15 __REG(0x40F00080 + 15 * 4)
1182 #define PCMD16 __REG(0x40F00080 + 16 * 4)
1183 #define PCMD17 __REG(0x40F00080 + 17 * 4)
1184 #define PCMD18 __REG(0x40F00080 + 18 * 4)
1185 #define PCMD19 __REG(0x40F00080 + 19 * 4)
1186 #define PCMD20 __REG(0x40F00080 + 20 * 4)
1187 #define PCMD21 __REG(0x40F00080 + 21 * 4)
1188 #define PCMD22 __REG(0x40F00080 + 22 * 4)
1189 #define PCMD23 __REG(0x40F00080 + 23 * 4)
1190 #define PCMD24 __REG(0x40F00080 + 24 * 4)
1191 #define PCMD25 __REG(0x40F00080 + 25 * 4)
1192 #define PCMD26 __REG(0x40F00080 + 26 * 4)
1193 #define PCMD27 __REG(0x40F00080 + 27 * 4)
1194 #define PCMD28 __REG(0x40F00080 + 28 * 4)
1195 #define PCMD29 __REG(0x40F00080 + 29 * 4)
1196 #define PCMD30 __REG(0x40F00080 + 30 * 4)
1197 #define PCMD31 __REG(0x40F00080 + 31 * 4)
1199 #define PCMD_MBC (1<<12)
1200 #define PCMD_DCE (1<<11)
1201 #define PCMD_LC (1<<10)
1202 /* FIXME: PCMD_SQC need be checked. */
1203 #define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */
1204 /* bit 9 should be 0 all day. */
1205 #define PVCR_VCSA (0x1<<14)
1206 #define PVCR_CommandDelay (0xf80)
1207 /* define MACRO for Power Manager General Configuration Register (PCFR) */
1208 #define PCFR_FVC (0x1 << 10)
1209 #define PCFR_PI2C_EN (0x1 << 6)
1211 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1212 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
1213 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1214 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
1215 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
1216 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
1218 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1219 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1220 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1221 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1223 #define RCSR_GPR (1 << 3) /* GPIO Reset */
1224 #define RCSR_SMR (1 << 2) /* Sleep Mode */
1225 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
1226 #define RCSR_HWR (1 << 0) /* Hardware Reset */
1229 * SSP Serial Port Registers
1231 #define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
1232 #define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
1233 #define SSSR __REG(0x41000008) /* SSP Status Register */
1234 #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
1235 #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1238 * MultiMediaCard (MMC) controller
1240 #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1241 #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1242 #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1243 #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1244 #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1245 #define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1246 #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1247 #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1248 #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1249 #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1250 #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1251 #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1252 #define MMC_CMD __REG(0x41100030) /* Index of current command */
1253 #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1254 #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1255 #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1256 #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1257 #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1262 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1263 #define CKEN __REG(0x41300004) /* Clock Enable Register */
1264 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1266 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1267 #if !defined(CONFIG_PXA27X)
1268 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1270 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1272 #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1273 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1274 #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1275 #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1276 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1277 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1278 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1279 #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1280 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1281 #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1282 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1283 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1284 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1285 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1286 #if defined(CONFIG_PXA27X)
1287 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1288 #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
1290 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1291 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1292 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1293 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1294 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1295 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1296 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
1297 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
1299 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1300 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1302 #if !defined(CONFIG_PXA27X)
1303 #define CCCR_L09 (0x1F)
1304 #define CCCR_L27 (0x1)
1305 #define CCCR_L32 (0x2)
1306 #define CCCR_L36 (0x3)
1307 #define CCCR_L40 (0x4)
1308 #define CCCR_L45 (0x5)
1310 #define CCCR_M1 (0x1 << 5)
1311 #define CCCR_M2 (0x2 << 5)
1312 #define CCCR_M4 (0x3 << 5)
1314 #define CCCR_N10 (0x2 << 7)
1315 #define CCCR_N15 (0x3 << 7)
1316 #define CCCR_N20 (0x4 << 7)
1317 #define CCCR_N25 (0x5 << 7)
1318 #define CCCR_N30 (0x6 << 7)
1324 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1325 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1326 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1327 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1328 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1329 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1330 #define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
1331 #define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
1332 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1333 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1334 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
1336 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1337 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1338 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1339 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1340 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1341 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1342 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1343 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1345 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1346 #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
1347 #define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
1348 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1349 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
1350 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1351 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
1352 #define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
1353 #define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
1354 #define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
1355 #define LCCR0_DIS (1 << 10) /* LCD Disable */
1356 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1357 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1358 #define LCCR0_PDD_S 12
1359 #define LCCR0_BM (1 << 20) /* Branch mask */
1360 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1361 #if defined(CONFIG_PXA27X)
1362 #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
1363 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
1364 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
1367 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1368 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
1369 (((Pixel) - 1) << FShft (LCCR1_PPL))
1371 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1372 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1373 /* pulse Width [1..64 Tpix] */ \
1374 (((Tpix) - 1) << FShft (LCCR1_HSW))
1376 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1377 /* count - 1 [Tpix] */
1378 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1379 /* [1..256 Tpix] */ \
1380 (((Tpix) - 1) << FShft (LCCR1_ELW))
1382 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1383 /* Wait count - 1 [Tpix] */
1384 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1385 /* [1..256 Tpix] */ \
1386 (((Tpix) - 1) << FShft (LCCR1_BLW))
1389 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1390 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1391 (((Line) - 1) << FShft (LCCR2_LPP))
1393 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1394 /* Width - 1 [Tln] (L_FCLK) */
1395 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1396 /* Width [1..64 Tln] */ \
1397 (((Tln) - 1) << FShft (LCCR2_VSW))
1399 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1401 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1402 /* [0..255 Tln] */ \
1403 ((Tln) << FShft (LCCR2_EFW))
1405 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1406 /* Wait count [Tln] */
1407 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1408 /* [0..255 Tln] */ \
1409 ((Tln) << FShft (LCCR2_BFW))
1412 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
1413 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1414 #define LCCR3_ACB_S 8
1417 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1418 #define LCCR3_API_S 16
1419 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1420 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1421 #define LCCR3_PCP (1 << 22) /* pixel clock polarity */
1422 #define LCCR3_OEP (1 << 23) /* output enable polarity */
1424 #define LCCR3_BPP (7 << 24) /* bits per pixel */
1425 #define LCCR3_BPP_S 24
1427 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1429 #define LCCR3_PDFOR_0 (0 << 30)
1430 #define LCCR3_PDFOR_1 (1 << 30)
1431 #define LCCR3_PDFOR_2 (2 << 30)
1432 #define LCCR3_PDFOR_3 (3 << 30)
1435 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
1436 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
1437 (((Div) << FShft (LCCR3_PCD)))
1440 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
1441 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
1442 ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
1444 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
1445 #define LCCR3_Acb(Acb) /* BAC Bias */ \
1446 (((Acb) << FShft (LCCR3_ACB)))
1448 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1449 /* pulse active High */
1450 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1452 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1454 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1457 #define LCSR0_LDD (1 << 0) /* LCD Disable Done */
1458 #define LCSR0_SOF (1 << 1) /* Start of frame */
1459 #define LCSR0_BER (1 << 2) /* Bus error */
1460 #define LCSR0_ABC (1 << 3) /* AC Bias count */
1461 #define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */
1462 #define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */
1463 #define LCSR0_OU (1 << 6) /* output FIFO underrun */
1464 #define LCSR0_QD (1 << 7) /* quick disable */
1465 #define LCSR0_EOF0 (1 << 8) /* end of frame */
1466 #define LCSR0_BS (1 << 9) /* branch status */
1467 #define LCSR0_SINT (1 << 10) /* subsequent interrupt */
1469 #define LCSR1_SOF1 (1 << 0)
1470 #define LCSR1_SOF2 (1 << 1)
1471 #define LCSR1_SOF3 (1 << 2)
1472 #define LCSR1_SOF4 (1 << 3)
1473 #define LCSR1_SOF5 (1 << 4)
1474 #define LCSR1_SOF6 (1 << 5)
1476 #define LCSR1_EOF1 (1 << 8)
1477 #define LCSR1_EOF2 (1 << 9)
1478 #define LCSR1_EOF3 (1 << 10)
1479 #define LCSR1_EOF4 (1 << 11)
1480 #define LCSR1_EOF5 (1 << 12)
1481 #define LCSR1_EOF6 (1 << 13)
1483 #define LCSR1_BS1 (1 << 16)
1484 #define LCSR1_BS2 (1 << 17)
1485 #define LCSR1_BS3 (1 << 18)
1486 #define LCSR1_BS4 (1 << 19)
1487 #define LCSR1_BS5 (1 << 20)
1488 #define LCSR1_BS6 (1 << 21)
1490 #define LCSR1_IU2 (1 << 25)
1491 #define LCSR1_IU3 (1 << 26)
1492 #define LCSR1_IU4 (1 << 27)
1493 #define LCSR1_IU5 (1 << 28)
1494 #define LCSR1_IU6 (1 << 29)
1496 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1497 #if defined(CONFIG_PXA27X)
1498 #define LDCMD_SOFINT (1 << 22)
1499 #define LDCMD_EOFINT (1 << 21)
1505 #define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
1506 #define MDCNFG_OFFSET 0x0
1507 #define MDREFR_OFFSET 0x4
1508 #define MSC0_OFFSET 0x8
1509 #define MSC1_OFFSET 0xC
1510 #define MSC2_OFFSET 0x10
1511 #define MECR_OFFSET 0x14
1512 #define SXLCR_OFFSET 0x18
1513 #define SXCNFG_OFFSET 0x1C
1514 #define FLYCNFG_OFFSET 0x20
1515 #define SXMRS_OFFSET 0x24
1516 #define MCMEM0_OFFSET 0x28
1517 #define MCMEM1_OFFSET 0x2C
1518 #define MCATT0_OFFSET 0x30
1519 #define MCATT1_OFFSET 0x34
1520 #define MCIO0_OFFSET 0x38
1521 #define MCIO1_OFFSET 0x3C
1522 #define MDMRS_OFFSET 0x40
1524 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
1525 #define MDCNFG_DE0 0x00000001
1526 #define MDCNFG_DE1 0x00000002
1527 #define MDCNFG_DE2 0x00010000
1528 #define MDCNFG_DE3 0x00020000
1529 #define MDCNFG_DWID0 0x00000004
1531 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
1532 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
1533 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
1534 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
1535 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
1536 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
1537 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
1538 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
1539 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
1540 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
1541 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
1542 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
1543 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
1544 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
1545 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
1546 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
1548 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1549 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1550 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
1551 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
1552 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
1553 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
1554 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
1555 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
1556 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
1557 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
1558 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
1559 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
1560 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
1562 #if defined(CONFIG_PXA27X)
1564 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
1566 #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
1567 #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
1568 #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
1569 #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
1570 #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
1571 #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
1572 #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
1573 #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
1574 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
1576 /* Interrupt Controller */
1578 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1579 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1580 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1581 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1582 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1584 /* General Purpose I/O */
1586 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
1587 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
1588 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1589 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1590 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1591 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */
1592 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1593 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1594 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1598 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1600 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1601 #define CKEN22_MEMC (1 << 22) /* Memory Controler */
1602 #define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
1603 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1604 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1605 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1606 #define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
1607 #define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
1608 #define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
1609 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1611 /* Memory controller */
1613 #define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */
1616 #define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
1617 #define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
1618 #define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1619 #define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1620 #define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
1621 #define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
1622 #define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
1623 #define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
1624 #define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
1625 #define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
1626 #define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
1627 #define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
1628 #define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
1629 #define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
1630 #define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
1631 #define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
1632 #define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
1633 #define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
1634 #define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
1635 #define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
1636 #define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
1637 #define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
1638 #define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
1640 #define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
1641 #define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
1642 #define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
1643 #define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
1644 #define CCR __REG(0x44000090) /* Cursor Control Register */
1646 #define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
1647 #define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
1649 #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
1650 #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
1652 #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
1653 #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
1654 #define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
1655 #define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
1656 #define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
1657 #define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
1659 #define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
1660 #define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
1661 #define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
1662 #define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
1663 #define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
1664 #define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
1666 #define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
1667 #define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
1668 #define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
1669 #define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
1670 #define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
1671 #define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
1673 #define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
1674 #define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
1675 #define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
1676 #define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
1677 #define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
1678 #define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
1680 #define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
1681 #define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
1682 #define CCR_CEN (1<<31) /* Enable bit for Cursor */
1684 /* Keypad controller */
1686 #define KPC __REG(0x41500000) /* Keypad Interface Control register */
1687 #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
1688 #define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
1689 #define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */
1690 #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
1691 #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
1692 #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
1693 #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
1694 #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
1695 #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
1697 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
1698 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
1699 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
1700 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
1701 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
1702 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
1703 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
1704 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
1705 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
1706 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
1707 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
1708 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
1709 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
1710 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
1711 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */
1712 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
1713 #define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */
1714 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
1715 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
1717 #define KPDK_DKP (0x1 << 31)
1718 #define KPDK_DK7 (0x1 << 7)
1719 #define KPDK_DK6 (0x1 << 6)
1720 #define KPDK_DK5 (0x1 << 5)
1721 #define KPDK_DK4 (0x1 << 4)
1722 #define KPDK_DK3 (0x1 << 3)
1723 #define KPDK_DK2 (0x1 << 2)
1724 #define KPDK_DK1 (0x1 << 1)
1725 #define KPDK_DK0 (0x1 << 0)
1727 #define KPREC_OF1 (0x1 << 31)
1728 #define kPREC_UF1 (0x1 << 30)
1729 #define KPREC_OF0 (0x1 << 15)
1730 #define KPREC_UF0 (0x1 << 14)
1732 #define KPMK_MKP (0x1 << 31)
1733 #define KPAS_SO (0x1 << 31)
1734 #define KPASMKPx_SO (0x1 << 31)
1736 #define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
1737 #define PSLR __REG(0x40F00034)
1738 #define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
1739 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
1740 #define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
1741 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
1742 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
1743 #define OSMR4 __REG(0x40A00080) /* */
1744 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
1745 #define OMCR4 __REG(0x40A000C0) /* */
1747 #endif /* CONFIG_PXA27X */
1749 #endif /* _PXA_REGS_H_ */
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