include/configs/MPC8308RDB.h

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   4  *
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1 /* E300 family */
  32 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  33 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  34 #define CONFIG_MPC8308RDB       1 /* MPC8308RDB board specific */
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 /*
  41  * On-board devices
  42  *
  43  * TSEC1 is SoC TSEC
  44  * TSEC2 is VSC switch
  45  */
  46 #define CONFIG_TSEC1
  47 #define CONFIG_VSC7385_ENET
  48
  49 /*
  50  * System Clock Setup
  51  */
  52 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  53 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  54
  55 /*
  56  * Hardware Reset Configuration Word
  57  * if CLKIN is 66.66MHz, then
  58  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  59  * We choose the A type silicon as default, so the core is 400Mhz.
  60  */
  61 #define CONFIG_SYS_HRCW_LOW (\
  62         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  63         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  64         HRCWL_SVCOD_DIV_2 |\
  65         HRCWL_CSB_TO_CLKIN_4X1 |\
  66         HRCWL_CORE_TO_CSB_3X1)
  67 /*
  68  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  69  * in 8308's HRCWH according to the manual, but original Freescale's
  70  * code has them and I've expirienced some problems using the board
  71  * with BDI3000 attached when I've tried to set these bits to zero
  72  * (UART doesn't work after the 'reset run' command).
  73  */
  74 #define CONFIG_SYS_HRCW_HIGH (\
  75         HRCWH_PCI_HOST |\
  76         HRCWH_PCI1_ARBITER_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT |\
  82         HRCWH_RL_EXT_LEGACY |\
  83         HRCWH_TSEC1M_IN_RGMII |\
  84         HRCWH_TSEC2M_IN_RGMII |\
  85         HRCWH_BIG_ENDIAN)
  86
  87 /*
  88  * System IO Config
  89  */
  90 #define CONFIG_SYS_SICRH (\
  91         SICRH_ESDHC_A_SD |\
  92         SICRH_ESDHC_B_SD |\
  93         SICRH_ESDHC_C_SD |\
  94         SICRH_GPIO_A_TSEC2 |\
  95         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  96         SICRH_IEEE1588_A_GPIO |\
  97         SICRH_USB |\
  98         SICRH_GTM_GPIO |\
  99         SICRH_IEEE1588_B_GPIO |\
 100         SICRH_ETSEC2_CRS |\
 101         SICRH_GPIOSEL_1 |\
 102         SICRH_TMROBI_V3P3 |\
 103         SICRH_TSOBI1_V2P5 |\
 104         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
 105 #define CONFIG_SYS_SICRL (\
 106         SICRL_SPI_PF0 |\
 107         SICRL_UART_PF0 |\
 108         SICRL_IRQ_PF0 |\
 109         SICRL_I2C2_PF0 |\
 110         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
 111
 112 /*
 113  * IMMR new address
 114  */
 115 #define CONFIG_SYS_IMMR         0xE0000000
 116
 117 /*
 118  * SERDES
 119  */
 120 #define CONFIG_FSL_SERDES
 121 #define CONFIG_FSL_SERDES1      0xe3000
 122
 123 /*
 124  * Arbiter Setup
 125  */
 126 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 127 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 128 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 129
 130 /*
 131  * DDR Setup
 132  */
 133 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 134 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 135 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 136 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 137 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 138                                 | DDRCDR_PZ_LOZ \
 139                                 | DDRCDR_NZ_LOZ \
 140                                 | DDRCDR_ODT \
 141                                 | DDRCDR_Q_DRN)
 142                                 /* 0x7b880001 */
 143 /*
 144  * Manually set up DDR parameters
 145  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 146  */
 147
 148 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 149
 150 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 151 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 152                                 | 0x00010000  /* ODT_WR to CSn */ \
 153                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 154                                 /* 0x80010102 */
 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 156 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 157                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 158                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 159                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 160                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 161                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 162                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 163                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 164                                 /* 0x00220802 */
 165 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 166                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 167                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 168                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 169                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 170                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 171                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 172                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 173                                 /* 0x27256222 */
 174 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 175                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 176                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 177                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 178                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 179                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 180                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 181                                 /* 0x121048c5 */
 182 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 183                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 184                                 /* 0x03600100 */
 185 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 186                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 187                                 | SDRAM_CFG_32_BE)
 188                                 /* 0x43080000 */
 189
 190 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 191 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 192                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 193                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 194 #define CONFIG_SYS_DDR_MODE2            0x00000000
 195
 196 /*
 197  * Memory test
 198  */
 199 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 200 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 201
 202 /*
 203  * The reserved memory
 204  */
 205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 206
 207 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 208 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 209
 210 /*
 211  * Initial RAM Base Address Setup
 212  */
 213 #define CONFIG_SYS_INIT_RAM_LOCK        1
 214 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 215 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000 /* Size of used area in RAM */
 216 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 218         (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
 219
 220 /*
 221  * Local Bus Configuration & Clock Setup
 222  */
 223 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 224 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 225 #define CONFIG_SYS_LBC_LBCR             0x00040000
 226
 227 /*
 228  * FLASH on the Local Bus
 229  */
 230 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 231 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 232 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 233
 234 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 235 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 236 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 237
 238 /* Window base at flash base */
 239 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 240 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 241
 242 #define CONFIG_SYS_BR0_PRELIM   (\
 243                 CONFIG_SYS_FLASH_BASE   /* Flash Base address */        |\
 244                 (2 << BR_PS_SHIFT)      /* 16 bit port size */          |\
 245                 BR_V)                   /* valid */
 246 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 247                                 | OR_UPM_XAM \
 248                                 | OR_GPCM_CSNT \
 249                                 | OR_GPCM_ACS_DIV2 \
 250                                 | OR_GPCM_XACS \
 251                                 | OR_GPCM_SCY_15 \
 252                                 | OR_GPCM_TRLX \
 253                                 | OR_GPCM_EHTR \
 254                                 | OR_GPCM_EAD)
 255
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 257 /* 127 64KB sectors and 8 8KB top sectors per device */
 258 #define CONFIG_SYS_MAX_FLASH_SECT       135
 259
 260 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 261 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 262
 263 /*
 264  * NAND Flash on the Local Bus
 265  */
 266 #define CONFIG_SYS_NAND_BASE            0xE0600000      /* 0xE0600000 */
 267 #define CONFIG_SYS_BR1_PRELIM   ( CONFIG_SYS_NAND_BASE \
 268                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 269                                 | BR_PS_8               /* Port Size = 8 bit */ \
 270                                 | BR_MS_FCM             /* MSEL = FCM */ \
 271                                 | BR_V )                /* valid */
 272 #define CONFIG_SYS_OR1_PRELIM   ( 0xFFFF8000            /* length 32K */ \
 273                                 | OR_FCM_CSCT \
 274                                 | OR_FCM_CST \
 275                                 | OR_FCM_CHT \
 276                                 | OR_FCM_SCY_1 \
 277                                 | OR_FCM_TRLX \
 278                                 | OR_FCM_EHTR )
 279                                 /* 0xFFFF8396 */
 280
 281 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 282 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 283
 284 #ifdef CONFIG_VSC7385_ENET
 285 #define CONFIG_TSEC2
 286 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 287 #define CONFIG_SYS_BR2_PRELIM           0xf0000801 /* VSC7385 Base address */
 288 #define CONFIG_SYS_OR2_PRELIM           0xfffe09ff /* VSC7385, 128K bytes*/
 289 /* Access window base at VSC7385 base */
 290 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 291 /* Access window size 128K */
 292 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 293 /* The flash address and size of the VSC7385 firmware image */
 294 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 295 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 296 #endif
 297 /*
 298  * Serial Port
 299  */
 300 #define CONFIG_CONS_INDEX       1
 301 #define CONFIG_SYS_NS16550
 302 #define CONFIG_SYS_NS16550_SERIAL
 303 #define CONFIG_SYS_NS16550_REG_SIZE     1
 304 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 305
 306 #define CONFIG_SYS_BAUDRATE_TABLE  \
 307         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 308
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 311
 312 /* Use the HUSH parser */
 313 #define CONFIG_SYS_HUSH_PARSER
 314 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 315
 316 /* Pass open firmware flat tree */
 317 #define CONFIG_OF_LIBFDT        1
 318 #define CONFIG_OF_BOARD_SETUP   1
 319 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 320
 321 /* I2C */
 322 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 323 #define CONFIG_FSL_I2C
 324 #define CONFIG_I2C_MULTI_BUS
 325 #define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
 326 #define CONFIG_SYS_I2C_SLAVE    0x7F
 327 #define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
 328 #define CONFIG_SYS_I2C_OFFSET   0x3000
 329 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 330
 331
 332 /*
 333  * Board info - revision and where boot from
 334  */
 335 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 336
 337 /*
 338  * Config on-board RTC
 339  */
 340 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 342
 343 /*
 344  * General PCI
 345  * Addresses are mapped 1-1.
 346  */
 347 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 348 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 349 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 350 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 351 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 352 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 353 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 354 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 355 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 356
 357 /* enable PCIE clock */
 358 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 359
 360 #define CONFIG_PCI
 361 #define CONFIG_PCIE
 362
 363 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 364
 365 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 366 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 367
 368 /*
 369  * TSEC
 370  */
 371 #define CONFIG_NET_MULTI
 372 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 373 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 374 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 375 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 376 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 377
 378 /*
 379  * TSEC ethernet configuration
 380  */
 381 #define CONFIG_MII              1 /* MII PHY management */
 382 #define CONFIG_TSEC1_NAME       "eTSEC0"
 383 #define CONFIG_TSEC2_NAME       "eTSEC1"
 384 #define TSEC1_PHY_ADDR          2
 385 #define TSEC2_PHY_ADDR          1
 386 #define TSEC1_PHYIDX            0
 387 #define TSEC2_PHYIDX            0
 388 #define TSEC1_FLAGS             TSEC_GIGABIT
 389 #define TSEC2_FLAGS             TSEC_GIGABIT
 390
 391 /* Options are: eTSEC[0-1] */
 392 #define CONFIG_ETHPRIME         "eTSEC0"
 393
 394 /*
 395  * Environment
 396  */
 397 #define CONFIG_ENV_IS_IN_FLASH  1
 398 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 399                                  CONFIG_SYS_MONITOR_LEN)
 400 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 401 #define CONFIG_ENV_SIZE         0x2000
 402 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 403 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 404
 405 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 406 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 407
 408 /*
 409  * BOOTP options
 410  */
 411 #define CONFIG_BOOTP_BOOTFILESIZE
 412 #define CONFIG_BOOTP_BOOTPATH
 413 #define CONFIG_BOOTP_GATEWAY
 414 #define CONFIG_BOOTP_HOSTNAME
 415
 416 /*
 417  * Command line configuration.
 418  */
 419 #include <config_cmd_default.h>
 420
 421 #define CONFIG_CMD_DATE
 422 #define CONFIG_CMD_DHCP
 423 #define CONFIG_CMD_I2C
 424 #define CONFIG_CMD_MII
 425 #define CONFIG_CMD_NET
 426 #define CONFIG_CMD_PCI
 427 #define CONFIG_CMD_PING
 428
 429 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 430
 431 /*
 432  * Miscellaneous configurable options
 433  */
 434 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 435 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 436 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 437
 438 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 439
 440 /* Print Buffer Size */
 441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 442 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 443 /* Boot Argument Buffer Size */
 444 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 445 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 446
 447 /*
 448  * For booting Linux, the board info and command line data
 449  * have to be in the first 256 MB of memory, since this is
 450  * the maximum mapped by the Linux kernel during initialization.
 451  */
 452 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 453
 454 /*
 455  * Core HID Setup
 456  */
 457 #define CONFIG_SYS_HID0_INIT    0x000000000
 458 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 459                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 460                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 461 #define CONFIG_SYS_HID2         HID2_HBE
 462
 463 /*
 464  * MMU Setup
 465  */
 466
 467 /* DDR: cache cacheable */
 468 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 469                                         BATL_MEMCOHERENCE)
 470 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 471                                         BATU_VS | BATU_VP)
 472 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 473 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 474
 475 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 476 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 477                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 478 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 479                                         BATU_VP)
 480 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 481 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 482
 483 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 484 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 485                                         BATL_MEMCOHERENCE)
 486 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 487                                         BATU_VS | BATU_VP)
 488 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 489                                         BATL_CACHEINHIBIT | \
 490                                         BATL_GUARDEDSTORAGE)
 491 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 492
 493 /* Stack in dcache: cacheable, no memory coherence */
 494 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 495 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 496                                         BATU_VS | BATU_VP)
 497 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 498 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 499
 500 /*
 501  * Environment Configuration
 502  */
 503
 504 #define CONFIG_ENV_OVERWRITE
 505
 506 #if defined(CONFIG_TSEC_ENET)
 507 #define CONFIG_HAS_ETH0
 508 #define CONFIG_HAS_ETH1
 509 #endif
 510
 511 #define CONFIG_BAUDRATE 115200
 512
 513 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 514
 515 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 516
 517 #define xstr(s) str(s)
 518 #define str(s)  #s
 519
 520 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 521         "netdev=eth0\0"                                                 \
 522         "consoledev=ttyS0\0"                                            \
 523         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 524                 "nfsroot=${serverip}:${rootpath}\0"                     \
 525         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 526         "addip=setenv bootargs ${bootargs} "                            \
 527                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 528                 ":${hostname}:${netdev}:off panic=1\0"                  \
 529         "addtty=setenv bootargs ${bootargs}"                            \
 530                 " console=${consoledev},${baudrate}\0"                  \
 531         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 532         "addmisc=setenv bootargs ${bootargs}\0"                         \
 533         "kernel_addr=FE080000\0"                                        \
 534         "fdt_addr=FE280000\0"                                           \
 535         "ramdisk_addr=FE290000\0"                                       \
 536         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 537         "kernel_addr_r=1000000\0"                                       \
 538         "fdt_addr_r=C00000\0"                                           \
 539         "hostname=mpc8308rdb\0"                                         \
 540         "bootfile=mpc8308rdb/uImage\0"                                  \
 541         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 542         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 543         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 544                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 545         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 546                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 547         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 548                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 549                 "run nfsargs addip addtty addmtd addmisc;"              \
 550                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 551         "bootcmd=run flash_self\0"                                      \
 552         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 553         "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)             \
 554                 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)      \
 555                 " +${filesize};cp.b ${fileaddr} "                       \
 556                 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"          \
 557         "upd=run load update\0"                                         \
 558
 559 #endif  /* __CONFIG_H */