3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
35 #define CONFIG_MPC852T 1
36 #define CONFIG_NC650 1
38 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
39 #undef CONFIG_8xx_CONS_SMC2
40 #undef CONFIG_8xx_CONS_NONE
41 #define CONFIG_BAUDRATE 115200
42 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
45 * 10 MHz - PLL input clock
47 #define CFG_8xx_OSCCLK 10000000
50 * 50 MHz - default CPU clock
52 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000
55 * 15 MHz - CPU minimum clock
57 #define CFG_8xx_CPUCLK_MIN 15000000
60 * 133 MHz - CPU maximum clock
62 #define CFG_8xx_CPUCLK_MAX 133000000
64 #define CFG_MEASURE_CPUCLK
65 #define CFG_8XX_XIN CFG_8xx_OSCCLK
67 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
69 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
71 #undef CONFIG_BOOTARGS
72 #define CONFIG_BOOTCOMMAND \
74 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
75 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
78 #undef CONFIG_WATCHDOG /* watchdog disabled */
80 #undef CONFIG_STATUS_LED /* Status LED disabled */
82 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
84 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
87 #define CFG_DISCOVER_PHY 1
90 /* enable I2C and select the hardware/software driver */
91 #undef CONFIG_HARD_I2C /* I2C with hardware support */
92 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
93 #define CFG_I2C_SPEED 100000 /* 100 kHz */
94 #define CFG_I2C_SLAVE 0x7f
97 * Software (bit-bang) I2C driver configuration
99 #define SCL 0x10000000 /* PA 3 */
100 #define SDA 0x40000000 /* PA 1 */
102 #define PAR immr->im_ioport.iop_papar
103 #define DIR immr->im_ioport.iop_padir
104 #define DAT immr->im_ioport.iop_padat
106 #define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;}
107 #define I2C_ACTIVE (DIR |= SDA)
108 #define I2C_TRISTATE (DIR &= ~SDA)
109 #define I2C_READ ((DAT & SDA) != 0)
110 #define I2C_SDA(bit) if (bit) DAT |= SDA; \
112 #define I2C_SCL(bit) if (bit) DAT |= SCL; \
114 #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
116 #define CFG_I2C_EEPROM_ADDR 0x50
117 #define CFG_I2C_EEPROM_ADDR_LEN 1
118 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
120 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
122 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
129 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
130 #include <cmd_confdefs.h>
133 * Miscellaneous configurable options
135 #define CFG_LONGHELP /* undef to save memory */
136 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
137 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
138 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
140 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
142 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
143 #define CFG_MAXARGS 16 /* max number of command args */
144 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
146 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
147 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
149 #define CFG_LOAD_ADDR 0x00100000
151 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
153 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
160 /*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
163 #define CFG_IMMR 0xF0000000
164 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
166 /*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
169 #define CFG_INIT_RAM_ADDR CFG_IMMR
170 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
171 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
172 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175 /*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
178 * Please note that CFG_SDRAM_BASE _must_ start at 0
180 #define CFG_SDRAM_BASE 0x00000000
181 #define CFG_FLASH_BASE 0x40000000
183 #define CFG_RESET_ADDRESS 0xFFF00100
185 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
186 #define CFG_MONITOR_BASE TEXT_BASE
187 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
190 * For booting Linux, the board info and command line data
191 * have to be in the first 8 MB of memory, since this is
192 * the maximum mapped by the Linux kernel during initialization.
194 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
198 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
199 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
201 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
205 #define CFG_ENV_IS_IN_FLASH 1
206 #define CFG_ENV_OFFSET 0x00740000
208 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
209 #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
211 /*-----------------------------------------------------------------------
212 * Cache Configuration
214 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
215 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
216 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
219 /*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
225 #if defined(CONFIG_WATCHDOG)
226 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
227 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
229 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
232 /*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
236 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
238 /*-----------------------------------------------------------------------
239 * TBSCR - Time Base Status and Control 11-26
240 *-----------------------------------------------------------------------
241 * Clear Reference Interrupt Status, Timebase freezing enabled
243 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
245 /*-----------------------------------------------------------------------
246 * PISCR - Periodic Interrupt Status and Control 11-31
247 *-----------------------------------------------------------------------
248 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
250 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
252 /*-----------------------------------------------------------------------
253 * SCCR - System Clock and reset Control Register 15-27
254 *-----------------------------------------------------------------------
255 * Set clock output, timebase and RTC source and divider,
256 * power management and some other internal clocks
258 #define SCCR_MASK SCCR_EBDF11
259 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
260 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
261 SCCR_DFLCD000 | SCCR_DFALCD00)
263 /*-----------------------------------------------------------------------
265 *-----------------------------------------------------------------------
271 * Init Memory Controller:
273 * BR0 and OR0 (FLASH)
276 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
278 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
279 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
281 /* FLASH timing: Default value of OR0 after reset */
282 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
283 OR_SCY_15_CLK | OR_TRLX)
285 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
286 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
287 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
290 * BR3 and OR3 (SDRAM)
292 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
293 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
296 * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
298 #define CFG_OR_TIMING_SDRAM 0x00000A00
300 #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
301 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
304 * 4096 Rows from SDRAM example configuration
305 * 1000 factor s -> ms
306 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
307 * 4 Number of refresh cycles per period
308 * 64 Refresh cycle in ms per number of rows
310 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
313 * Memory Periodic Timer Prescaler
316 /* periodic timer for refresh */
317 #define CFG_MAMR_PTA 39
319 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
320 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
321 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
323 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
324 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
325 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
328 * MAMR settings for SDRAM
331 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
332 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
333 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
334 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
335 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
336 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
339 * Internal Definitions
343 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
344 #define BOOTFLAG_WARM 0x02 /* Software reboot */
347 #endif /* __CONFIG_H */