include/configs/T1040QDS.h

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * T1040 QDS board configuration file
  28  */
  29 #define CONFIG_T1040QDS
  30 #define CONFIG_PHYS_64BIT
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE
  41 #define CONFIG_E500                     /* BOOKE e500 family */
  42 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  44 #define CONFIG_MP                       /* support multiple processors */
  45
  46 #ifndef CONFIG_SYS_TEXT_BASE
  47 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  48 #endif
  49
  50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  52 #endif
  53
  54 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  55 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  56 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  57 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  58 #define CONFIG_PCI_INDIRECT_BRIDGE
  59 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  60 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  61 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  62 #define CONFIG_PCIE4                    /* PCIE controler 4 */
  63
  64 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  66
  67 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  68
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #ifdef CONFIG_SYS_NO_FLASH
  72 #define CONFIG_ENV_IS_NOWHERE
  73 #else
  74 #define CONFIG_FLASH_CFI_DRIVER
  75 #define CONFIG_SYS_FLASH_CFI
  76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  77 #endif
  78
  79 #ifndef CONFIG_SYS_NO_FLASH
  80 #if defined(CONFIG_SPIFLASH)
  81 #define CONFIG_SYS_EXTRA_ENV_RELOC
  82 #define CONFIG_ENV_IS_IN_SPI_FLASH
  83 #define CONFIG_ENV_SPI_BUS              0
  84 #define CONFIG_ENV_SPI_CS               0
  85 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  86 #define CONFIG_ENV_SPI_MODE             0
  87 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  88 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  89 #define CONFIG_ENV_SECT_SIZE            0x10000
  90 #elif defined(CONFIG_SDCARD)
  91 #define CONFIG_SYS_EXTRA_ENV_RELOC
  92 #define CONFIG_ENV_IS_IN_MMC
  93 #define CONFIG_SYS_MMC_ENV_DEV          0
  94 #define CONFIG_ENV_SIZE                 0x2000
  95 #define CONFIG_ENV_OFFSET               (512 * 1658)
  96 #elif defined(CONFIG_NAND)
  97 #define CONFIG_SYS_EXTRA_ENV_RELOC
  98 #define CONFIG_ENV_IS_IN_NAND
  99 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 100 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 101 #else
 102 #define CONFIG_ENV_IS_IN_FLASH
 103 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 104 #define CONFIG_ENV_SIZE         0x2000
 105 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 106 #endif
 107 #else /* CONFIG_SYS_NO_FLASH */
 108 #define CONFIG_ENV_SIZE                0x2000
 109 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 110 #endif
 111
 112 #ifndef __ASSEMBLY__
 113 unsigned long get_board_sys_clk(void);
 114 unsigned long get_board_ddr_clk(void);
 115 #endif
 116
 117 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 118 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 119
 120 /*
 121  * These can be toggled for performance analysis, otherwise use default.
 122  */
 123 #define CONFIG_SYS_CACHE_STASHING
 124 #define CONFIG_BACKSIDE_L2_CACHE
 125 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 126 #define CONFIG_BTB                      /* toggle branch predition */
 127 #define CONFIG_DDR_ECC
 128 #ifdef CONFIG_DDR_ECC
 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 130 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 131 #endif
 132
 133 #define CONFIG_ENABLE_36BIT_PHYS
 134
 135 #define CONFIG_ADDR_MAP
 136 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 137
 138 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 139 #define CONFIG_SYS_MEMTEST_END          0x00400000
 140 #define CONFIG_SYS_ALT_MEMTEST
 141 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 142
 143 /*
 144  *  Config the L3 Cache as L3 SRAM
 145  */
 146 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 147
 148 #define CONFIG_SYS_DCSRBAR              0xf0000000
 149 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 150
 151 /* EEPROM */
 152 #define CONFIG_ID_EEPROM
 153 #define CONFIG_SYS_I2C_EEPROM_NXID
 154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 155 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 159
 160 /*
 161  * DDR Setup
 162  */
 163 #define CONFIG_VERY_BIG_RAM
 164 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 165 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 166
 167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 168 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 169 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 170
 171 #define CONFIG_DDR_SPD
 172 #ifndef CONFIG_SYS_FSL_DDR4
 173 #define CONFIG_SYS_FSL_DDR3
 174 #define CONFIG_FSL_DDR_INTERACTIVE
 175 #endif
 176
 177 #define CONFIG_SYS_SPD_BUS_NUM  0
 178 #define SPD_EEPROM_ADDRESS      0x51
 179
 180 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 181
 182 /*
 183  * IFC Definitions
 184  */
 185 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 186 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 187
 188 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 189 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 190                                 + 0x8000000) | \
 191                                 CSPR_PORT_SIZE_16 | \
 192                                 CSPR_MSEL_NOR | \
 193                                 CSPR_V)
 194 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 195 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 196                                 CSPR_PORT_SIZE_16 | \
 197                                 CSPR_MSEL_NOR | \
 198                                 CSPR_V)
 199 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 200 /* NOR Flash Timing Params */
 201 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 202 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 203                                 FTIM0_NOR_TEADC(0x5) | \
 204                                 FTIM0_NOR_TEAHC(0x5))
 205 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 206                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 207                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 208 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 209                                 FTIM2_NOR_TCH(0x4) | \
 210                                 FTIM2_NOR_TWPH(0x0E) | \
 211                                 FTIM2_NOR_TWP(0x1c))
 212 #define CONFIG_SYS_NOR_FTIM3    0x0
 213
 214 #define CONFIG_SYS_FLASH_QUIET_TEST
 215 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 216
 217 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 218 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 219 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 221
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO
 223 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 224                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 225 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 226 #define QIXIS_BASE              0xffdf0000
 227 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 228 #define QIXIS_LBMAP_SWITCH              0x06
 229 #define QIXIS_LBMAP_MASK                0x0f
 230 #define QIXIS_LBMAP_SHIFT               0
 231 #define QIXIS_LBMAP_DFLTBANK            0x00
 232 #define QIXIS_LBMAP_ALTBANK             0x04
 233 #define QIXIS_RST_CTL_RESET             0x31
 234 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 235 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 236 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 237 #define QIXIS_RST_FORCE_MEM             0x01
 238
 239 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 240 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 241                                 | CSPR_PORT_SIZE_8 \
 242                                 | CSPR_MSEL_GPCM \
 243                                 | CSPR_V)
 244 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 245 #define CONFIG_SYS_CSOR3        0x0
 246 /* QIXIS Timing parameters for IFC CS3 */
 247 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 248                                         FTIM0_GPCM_TEADC(0x0e) | \
 249                                         FTIM0_GPCM_TEAHC(0x0e))
 250 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 251                                         FTIM1_GPCM_TRAD(0x3f))
 252 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 253                                         FTIM2_GPCM_TCH(0x8) | \
 254                                         FTIM2_GPCM_TWP(0x1f))
 255 #define CONFIG_SYS_CS3_FTIM3            0x0
 256
 257 #define CONFIG_NAND_FSL_IFC
 258 #define CONFIG_SYS_NAND_BASE            0xff800000
 259 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 260
 261 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 262 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 263                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 264                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 265                                 | CSPR_V)
 266 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 267
 268 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 269                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 270                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 271                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 272                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 273                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 274                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 275
 276 #define CONFIG_SYS_NAND_ONFI_DETECTION
 277
 278 /* ONFI NAND Flash mode0 Timing Params */
 279 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 280                                         FTIM0_NAND_TWP(0x18)   | \
 281                                         FTIM0_NAND_TWCHT(0x07) | \
 282                                         FTIM0_NAND_TWH(0x0a))
 283 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 284                                         FTIM1_NAND_TWBE(0x39)  | \
 285                                         FTIM1_NAND_TRR(0x0e)   | \
 286                                         FTIM1_NAND_TRP(0x18))
 287 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 288                                         FTIM2_NAND_TREH(0x0a) | \
 289                                         FTIM2_NAND_TWHRE(0x1e))
 290 #define CONFIG_SYS_NAND_FTIM3           0x0
 291
 292 #define CONFIG_SYS_NAND_DDR_LAW         11
 293 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 294 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 295 #define CONFIG_MTD_NAND_VERIFY_WRITE
 296 #define CONFIG_CMD_NAND
 297
 298 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 299
 300 #if defined(CONFIG_NAND)
 301 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 302 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 303 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 304 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 305 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 306 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 307 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 308 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 309 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 310 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 311 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 312 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 313 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 314 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 315 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 316 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 317 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 318 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 319 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 320 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 321 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 322 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 323 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 324 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 325 #else
 326 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 327 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 328 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 329 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 330 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 331 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 332 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 333 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 334 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 335 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 336 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 337 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 338 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 339 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 340 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 341 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 342 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 343 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 344 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 345 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 346 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 347 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 348 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 349 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 350 #endif
 351
 352 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 353
 354 #if defined(CONFIG_RAMBOOT_PBL)
 355 #define CONFIG_SYS_RAMBOOT
 356 #endif
 357
 358 #define CONFIG_BOARD_EARLY_INIT_R
 359 #define CONFIG_MISC_INIT_R
 360
 361 #define CONFIG_HWCONFIG
 362
 363 /* define to use L1 as initial stack */
 364 #define CONFIG_L1_INIT_RAM
 365 #define CONFIG_SYS_INIT_RAM_LOCK
 366 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 369 /* The assembler doesn't like typecast */
 370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 371         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 372           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 373 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 374
 375 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 376                                         GENERATED_GBL_DATA_SIZE)
 377 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 378
 379 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 380 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 381
 382 /* Serial Port - controlled on board with jumper J8
 383  * open - index 2
 384  * shorted - index 1
 385  */
 386 #define CONFIG_CONS_INDEX       1
 387 #define CONFIG_SYS_NS16550
 388 #define CONFIG_SYS_NS16550_SERIAL
 389 #define CONFIG_SYS_NS16550_REG_SIZE     1
 390 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 391
 392 #define CONFIG_SYS_BAUDRATE_TABLE       \
 393         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 394
 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 397 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 398 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 399 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
 400 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 401
 402 /* Use the HUSH parser */
 403 #define CONFIG_SYS_HUSH_PARSER
 404 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 405
 406 /* Video */
 407 #define CONFIG_FSL_DIU_FB
 408 #ifdef CONFIG_FSL_DIU_FB
 409 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 410 #define CONFIG_VIDEO
 411 #define CONFIG_CMD_BMP
 412 #define CONFIG_CFB_CONSOLE
 413 #define CONFIG_VIDEO_SW_CURSOR
 414 #define CONFIG_VGA_AS_SINGLE_DEVICE
 415 #define CONFIG_VIDEO_LOGO
 416 #define CONFIG_VIDEO_BMP_LOGO
 417 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 418 /*
 419  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 420  * disable empty flash sector detection, which is I/O-intensive.
 421  */
 422 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 423 #endif
 424
 425 /* pass open firmware flat tree */
 426 #define CONFIG_OF_LIBFDT
 427 #define CONFIG_OF_BOARD_SETUP
 428 #define CONFIG_OF_STDOUT_VIA_ALIAS
 429
 430 /* new uImage format support */
 431 #define CONFIG_FIT
 432 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 433
 434 /* I2C */
 435 #define CONFIG_SYS_I2C
 436 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 437 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 438 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 439 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 440 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 441 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 442 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 443
 444 #define I2C_MUX_PCA_ADDR                0x77
 445 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 446
 447
 448 /* I2C bus multiplexer */
 449 #define I2C_MUX_CH_DEFAULT      0x8
 450 #define I2C_MUX_CH_DIU          0xC
 451
 452 /* LDI/DVI Encoder for display */
 453 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 454 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 455
 456 /*
 457  * RTC configuration
 458  */
 459 #define RTC
 460 #define CONFIG_RTC_DS3231               1
 461 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 462
 463 /*
 464  * eSPI - Enhanced SPI
 465  */
 466 #define CONFIG_FSL_ESPI
 467 #define CONFIG_SPI_FLASH
 468 #define CONFIG_SPI_FLASH_STMICRO
 469 #define CONFIG_SPI_FLASH_SST
 470 #define CONFIG_SPI_FLASH_EON
 471 #define CONFIG_CMD_SF
 472 #define CONFIG_SF_DEFAULT_SPEED         10000000
 473 #define CONFIG_SF_DEFAULT_MODE          0
 474
 475 /*
 476  * General PCI
 477  * Memory space is mapped 1-1, but I/O space must start from 0.
 478  */
 479
 480 #ifdef CONFIG_PCI
 481 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 482 #ifdef CONFIG_PCIE1
 483 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 484 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 485 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 486 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 487 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 488 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 489 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 490 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 491 #endif
 492
 493 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 494 #ifdef CONFIG_PCIE2
 495 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 496 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 497 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 498 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 499 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 500 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 501 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 502 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 503 #endif
 504
 505 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 506 #ifdef CONFIG_PCIE3
 507 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 508 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 509 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 510 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 511 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 512 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 513 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 514 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 515 #endif
 516
 517 /* controller 4, Base address 203000 */
 518 #ifdef CONFIG_PCIE4
 519 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 520 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 521 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 522 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 523 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 524 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 525 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 526 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 527 #endif
 528
 529 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 530 #define CONFIG_E1000
 531
 532 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 533 #define CONFIG_DOS_PARTITION
 534 #endif  /* CONFIG_PCI */
 535
 536 /* SATA */
 537 #define CONFIG_FSL_SATA_V2
 538 #ifdef CONFIG_FSL_SATA_V2
 539 #define CONFIG_LIBATA
 540 #define CONFIG_FSL_SATA
 541
 542 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 543 #define CONFIG_SATA1
 544 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 545 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 546 #define CONFIG_SATA2
 547 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 548 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 549
 550 #define CONFIG_LBA48
 551 #define CONFIG_CMD_SATA
 552 #define CONFIG_DOS_PARTITION
 553 #define CONFIG_CMD_EXT2
 554 #endif
 555
 556 /*
 557 * USB
 558 */
 559 #define CONFIG_HAS_FSL_DR_USB
 560
 561 #ifdef CONFIG_HAS_FSL_DR_USB
 562 #define CONFIG_USB_EHCI
 563
 564 #ifdef CONFIG_USB_EHCI
 565 #define CONFIG_CMD_USB
 566 #define CONFIG_USB_STORAGE
 567 #define CONFIG_USB_EHCI_FSL
 568 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 569 #define CONFIG_CMD_EXT2
 570 #endif
 571 #endif
 572
 573 #define CONFIG_MMC
 574
 575 #ifdef CONFIG_MMC
 576 #define CONFIG_FSL_ESDHC
 577 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 578 #define CONFIG_CMD_MMC
 579 #define CONFIG_GENERIC_MMC
 580 #define CONFIG_CMD_EXT2
 581 #define CONFIG_CMD_FAT
 582 #define CONFIG_DOS_PARTITION
 583 #endif
 584
 585 /* Qman/Bman */
 586 #ifndef CONFIG_NOBQFMAN
 587 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 588 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 589 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 590 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 591 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 592 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 593 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 594 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 595 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 596
 597 #define CONFIG_SYS_DPAA_FMAN
 598 #define CONFIG_SYS_DPAA_PME
 599
 600 /* Default address of microcode for the Linux Fman driver */
 601 #if defined(CONFIG_SPIFLASH)
 602 /*
 603  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 604  * env, so we got 0x110000.
 605  */
 606 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 607 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 608 #elif defined(CONFIG_SDCARD)
 609 /*
 610  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 611  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 612  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 613  */
 614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 615 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 616 #elif defined(CONFIG_NAND)
 617 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 618 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 619 #else
 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 621 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 622 #endif
 623 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 624 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 625 #endif /* CONFIG_NOBQFMAN */
 626
 627 #ifdef CONFIG_SYS_DPAA_FMAN
 628 #define CONFIG_FMAN_ENET
 629 #define CONFIG_PHYLIB_10G
 630 #define CONFIG_PHY_VITESSE
 631 #define CONFIG_PHY_REALTEK
 632 #define CONFIG_PHY_TERANETICS
 633 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 634 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 635 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 636 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 637 #endif
 638
 639 #ifdef CONFIG_FMAN_ENET
 640 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x01
 641 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x02
 642
 643 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 644 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 645 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 646 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 647
 648 #define CONFIG_MII              /* MII PHY management */
 649 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 650 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 651 #endif
 652
 653 /*
 654  * Environment
 655  */
 656 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 657 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 658
 659 /*
 660  * Command line configuration.
 661  */
 662 #include <config_cmd_default.h>
 663
 664 #define CONFIG_CMD_DATE
 665 #define CONFIG_CMD_DHCP
 666 #define CONFIG_CMD_EEPROM
 667 #define CONFIG_CMD_ELF
 668 #define CONFIG_CMD_ERRATA
 669 #define CONFIG_CMD_GREPENV
 670 #define CONFIG_CMD_IRQ
 671 #define CONFIG_CMD_I2C
 672 #define CONFIG_CMD_MII
 673 #define CONFIG_CMD_PING
 674 #define CONFIG_CMD_REGINFO
 675 #define CONFIG_CMD_SETEXPR
 676
 677 #ifdef CONFIG_PCI
 678 #define CONFIG_CMD_PCI
 679 #define CONFIG_CMD_NET
 680 #endif
 681
 682 /*
 683  * Miscellaneous configurable options
 684  */
 685 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 686 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 687 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 688 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 689 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 690 #ifdef CONFIG_CMD_KGDB
 691 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 692 #else
 693 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 694 #endif
 695 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 696 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 697 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 698
 699 /*
 700  * For booting Linux, the board info and command line data
 701  * have to be in the first 64 MB of memory, since this is
 702  * the maximum mapped by the Linux kernel during initialization.
 703  */
 704 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 705 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 706
 707 #ifdef CONFIG_CMD_KGDB
 708 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 709 #endif
 710
 711 /*
 712  * Environment Configuration
 713  */
 714 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 715 #define CONFIG_BOOTFILE         "uImage"
 716 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 717
 718 /* default location for tftp and bootm */
 719 #define CONFIG_LOADADDR         1000000
 720
 721 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 722
 723 #define CONFIG_BAUDRATE 115200
 724
 725 #define __USB_PHY_TYPE  utmi
 726
 727 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 728         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 729         "bank_intlv=cs0_cs1;"                                   \
 730         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 731         "netdev=eth0\0"                                         \
 732         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 733         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 734         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 735         "tftpflash=tftpboot $loadaddr $uboot && "               \
 736         "protect off $ubootaddr +$filesize && "                 \
 737         "erase $ubootaddr +$filesize && "                       \
 738         "cp.b $loadaddr $ubootaddr $filesize && "               \
 739         "protect on $ubootaddr +$filesize && "                  \
 740         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 741         "consoledev=ttyS0\0"                                    \
 742         "ramdiskaddr=2000000\0"                                 \
 743         "ramdiskfile=t1040qds/ramdisk.uboot\0"                  \
 744         "fdtaddr=c00000\0"                                      \
 745         "fdtfile=t1040qds/t1040qds.dtb\0"                       \
 746         "bdev=sda3\0"                                           \
 747         "c=ffe\0"
 748
 749 #define CONFIG_LINUX                       \
 750         "setenv bootargs root=/dev/ram rw "            \
 751         "console=$consoledev,$baudrate $othbootargs;"  \
 752         "setenv ramdiskaddr 0x02000000;"               \
 753         "setenv fdtaddr 0x00c00000;"                   \
 754         "setenv loadaddr 0x1000000;"                   \
 755         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 756
 757 #define CONFIG_HDBOOT                                   \
 758         "setenv bootargs root=/dev/$bdev rw "           \
 759         "console=$consoledev,$baudrate $othbootargs;"   \
 760         "tftp $loadaddr $bootfile;"                     \
 761         "tftp $fdtaddr $fdtfile;"                       \
 762         "bootm $loadaddr - $fdtaddr"
 763
 764 #define CONFIG_NFSBOOTCOMMAND                   \
 765         "setenv bootargs root=/dev/nfs rw "     \
 766         "nfsroot=$serverip:$rootpath "          \
 767         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 768         "console=$consoledev,$baudrate $othbootargs;"   \
 769         "tftp $loadaddr $bootfile;"             \
 770         "tftp $fdtaddr $fdtfile;"               \
 771         "bootm $loadaddr - $fdtaddr"
 772
 773 #define CONFIG_RAMBOOTCOMMAND                           \
 774         "setenv bootargs root=/dev/ram rw "             \
 775         "console=$consoledev,$baudrate $othbootargs;"   \
 776         "tftp $ramdiskaddr $ramdiskfile;"               \
 777         "tftp $loadaddr $bootfile;"                     \
 778         "tftp $fdtaddr $fdtfile;"                       \
 779         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 780
 781 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 782
 783 #ifdef CONFIG_SECURE_BOOT
 784 #include <asm/fsl_secure_boot.h>
 785 #endif
 786
 787 #endif  /* __CONFIG_H */