Changes since U-Boot 1.1.4:
======================================================================
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+ 405 SDRAM: - The SDRAM parameters can now be defined in the board
+ config file and the 405 SDRAM controller values will
+ be calculated upon bootup (see PPChameleonEVB).
+ When those settings are not defined in the board
+ config file, the register setup will be as it is now,
+ so this implementation should not break any current
+ design using this code.
+
+ Thanks to Andrea Marson from DAVE for this patch.
+
+ 440 DDR: - Added function sdram_tr1_set to auto calculate the
+ TR1 value for the DDR.
+ - Added ECC support (see p3p440).
+
+ Patch by Stefan Roese, 17 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+ was written to. It is need on some targets when BAT translation
+ is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+ Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+ timer and cpu_reset code from cpu/$(CPU) into the new
+ cpu/$(CPU)/$(SOC) directories
+ Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+ CFG_BOOTM_LEN to adjust this setting.
+
+ As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+ uImages was restricted to 4MBytes. This default size is now
+ increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+ in the board config file.
+
+ Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+ Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+ Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+ incorrectly generating start/stop conditions on the bus.
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+ should look at LSB of L1CSRn registers to determine if L1 cache is
+ enabled, not the MSB.
+ Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+ Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+ Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+ ethernet and iic adapter code.
+ Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+ Patch by Murray Jensen, 08 Jul 2005
+
* Fix compile problem
* Added PCI support for MPC8349ADS board