- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
- early_delay(20);
- clrbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
-
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl);
+ udelay(20);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_clr);
+
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_set);