* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include "mx28_init.h"
+#include "mxs_init.h"
+
+#ifdef CONFIG_SYS_SPL_VDDD_VAL
+#define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
+#else
+#define VDDD_VAL 1350
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_VAL
+#define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
+#else
+#define VDDIO_VAL 3300
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_VAL
+#define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
+#else
+#define VDDA_VAL 1800
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_VAL
+#define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
+#else
+#define VDDMEM_VAL 1700
+#endif
+
+#ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
+#define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
+#else
+#define VDDD_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
+#define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
+#else
+#define VDDIO_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
+#define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
+#else
+#define VDDA_BO_VAL 175
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#else
+#define VDDMEM_BO_VAL 25
+#endif
+
+#ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
+#if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
+#error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
+#endif
+#define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
+#else
+/* Brownout default at 3V */
+#define BATT_BO_VAL ((3000 - 2400) / 40)
+#endif
+
+#ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+static const int fixed_batt_supply = 1;
+#else
+static const int fixed_batt_supply;
+#endif
-void mx28_power_clock2xtal(void)
+static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+
+static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mx28_power_clock2pll(void)
+static void mxs_power_clock2pll(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mx28_power_clear_auto_restart(void)
+static int mxs_power_wait_rtc_stat(u32 mask)
{
- struct mxs_rtc_regs *rtc_regs =
- (struct mxs_rtc_regs *)MXS_RTC_BASE;
+ int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
+ u32 val;
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
- writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
- ;
+ while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
+ early_delay(1);
+ if (timeout-- < 0)
+ break;
+ }
+ return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
+}
- writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
- ;
+static int mxs_power_set_auto_restart(int on)
+{
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
/*
* Due to the hardware design bug of mx28 EVK-A
* we need to set the AUTO_RESTART bit.
*/
- if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
- return;
+ if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
+ return 1;
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
+ if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
+ RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
+ return 0;
- setbits_le32(&rtc_regs->hw_rtc_persistent0,
- RTC_PERSISTENT0_AUTO_RESTART);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
- ;
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
+ !on * RTC_PERSISTENT0_AUTO_RESTART,
+ !!on * RTC_PERSISTENT0_AUTO_RESTART);
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ return 0;
}
-void mx28_power_set_linreg(void)
+static void mxs_power_set_linreg(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mx28_get_batt_volt(void)
+static int mxs_get_batt_volt(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
return volt;
}
-int mx28_is_batt_ready(void)
+static int mxs_is_batt_ready(void)
{
- return (mx28_get_batt_volt() >= 3600);
+ return (mxs_get_batt_volt() >= 3600);
}
-int mx28_is_batt_good(void)
+static int mxs_is_batt_good(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
- uint32_t volt = mx28_get_batt_volt();
+ uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
return 1;
early_delay(500000);
- volt = mx28_get_batt_volt();
+ volt = mxs_get_batt_volt();
if (volt >= 3500)
return 0;
return 0;
}
-void mx28_power_setup_5v_detect(void)
+static void mxs_power_setup_5v_detect(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mx28_src_power_init(void)
+static void mxs_src_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
- setbits_le32(&power_regs->hw_power_battmonitor,
+ if (!fixed_batt_supply) {
+ /* FIXME: This requires the LRADC to be set up! */
+ setbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_EN_BATADJ);
+ } else {
+ clrbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_EN_BATADJ);
+ }
/* Increase the RCSCALE level for quick DCDC response to dynamic load */
clrsetbits_le32(&power_regs->hw_power_loopctrl,
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- /* 5V to battery handoff ... FIXME */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ if (!fixed_batt_supply) {
+ /* 5V to battery handoff ... FIXME */
+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ early_delay(30);
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ }
}
-void mx28_power_init_4p2_params(void)
+static void mxs_power_init_4p2_params(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_enable_4p2_dcdc_input(int xfer)
+static void mxs_enable_4p2_dcdc_input(int xfer)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mx28_power_init_4p2_regulator(void)
+static void mxs_power_init_4p2_regulator(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
- mx28_enable_4p2_dcdc_input(0);
+ mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mx28_power_init_dcdc_4p2_source(void)
+static void mxs_power_init_dcdc_4p2_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
hang();
}
- mx28_enable_4p2_dcdc_input(1);
+ mxs_enable_4p2_dcdc_input(1);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
}
}
-void mx28_power_enable_4p2(void)
+static void mxs_power_enable_4p2(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
- mx28_power_init_4p2_params();
- mx28_power_init_4p2_regulator();
+ mxs_power_init_4p2_params();
+ mxs_power_init_4p2_regulator();
/* Shutdown battery (none present) */
- if (!mx28_is_batt_ready()) {
+ if (!mxs_is_batt_ready()) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
}
- mx28_power_init_dcdc_4p2_source();
+ mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
&power_regs->hw_power_charge_clr);
}
-void mx28_boot_valid_5v(void)
+static void mxs_boot_valid_5v(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
&power_regs->hw_power_ctrl_clr);
- mx28_power_enable_4p2();
+ mxs_power_enable_4p2();
}
-void mx28_powerdown(void)
+static void mxs_powerdown(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
-void mx28_batt_boot(void)
+static void mxs_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- mx28_power_set_linreg();
+ mxs_power_set_linreg();
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_handle_5v_conflict(void)
+static void mxs_handle_5v_conflict(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
tmp = readl(&power_regs->hw_power_sts);
if (tmp & POWER_STS_VDDIO_BO) {
- mx28_powerdown();
+ /*
+ * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
+ * unreliable
+ */
+ mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
break;
} else {
- mx28_powerdown();
+ mxs_powerdown();
break;
}
if (tmp & POWER_STS_PSWITCH_MASK) {
- mx28_batt_boot();
+ mxs_batt_boot();
break;
}
}
}
-void mx28_5v_boot(void)
+static void mxs_5v_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
return;
}
- mx28_handle_5v_conflict();
+ mxs_handle_5v_conflict();
}
-void mx28_init_batt_bo(void)
+static void mxs_fixed_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_ENABLE_DCDC |
+ POWER_5VCTRL_ILIMIT_EQ_ZERO |
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
- /* Brownout at 3V */
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET |
+ POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET |
+ POWER_VDDIOCTRL_DISABLE_STEPPING);
+
+ /* Stop 5V detection */
+ writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
+ &power_regs->hw_power_5vctrl_clr);
+}
+
+static void mxs_init_batt_bo(void)
+{
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
- 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+ BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mx28_switch_vddd_to_dcdc_source(void)
+static void mxs_switch_vddd_to_dcdc_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mx28_power_configure_power_source(void)
+static void mxs_power_configure_power_source(void)
{
- int batt_ready, batt_good;
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
- mx28_src_power_init();
-
- batt_ready = mx28_is_batt_ready();
+ mxs_src_power_init();
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- batt_good = mx28_is_batt_good();
- if (batt_ready) {
- /* 5V source detected, good battery detected. */
- mx28_batt_boot();
- } else {
- if (batt_good) {
- /* 5V source detected, low battery detceted. */
+ if (!fixed_batt_supply) {
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (mxs_is_batt_ready()) {
+ /* 5V source detected, good battery detected. */
+ mxs_batt_boot();
} else {
- /* 5V source detected, bad battery detected. */
- writel(LRADC_CONVERSION_AUTOMATIC,
- &lradc_regs->hw_lradc_conversion_clr);
- clrbits_le32(&power_regs->hw_power_battmonitor,
- POWER_BATTMONITOR_BATT_VAL_MASK);
+ if (!mxs_is_batt_good()) {
+ /* 5V source detected, bad battery detected. */
+ writel(LRADC_CONVERSION_AUTOMATIC,
+ &lradc_regs->hw_lradc_conversion_clr);
+ clrbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_BATT_VAL_MASK);
+ }
+ mxs_5v_boot();
}
- mx28_5v_boot();
+ } else {
+ /* 5V not detected, booting from battery. */
+ mxs_batt_boot();
}
} else {
- /* 5V not detected, booting from battery. */
- mx28_batt_boot();
+ mxs_fixed_batt_boot();
}
- mx28_power_clock2pll();
+ mxs_power_clock2pll();
+
+ mxs_init_batt_bo();
- mx28_init_batt_bo();
+ mxs_switch_vddd_to_dcdc_source();
- mx28_switch_vddd_to_dcdc_source();
+#ifdef CONFIG_MX23
+ /* Fire up the VDDMEM LinReg now that we're all set. */
+ writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+ &power_regs->hw_power_vddmemctrl);
+#endif
}
-void mx28_enable_output_rail_protection(void)
+static void mxs_enable_output_rail_protection(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mx28_get_vddio_power_source_off(void)
+static int mxs_get_vddio_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
+ !(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
+
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
if (!(readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
}
return 0;
-
}
-int mx28_get_vddd_power_source_off(void)
+static int mxs_get_vddd_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
return 0;
}
-void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+static int mxs_get_vdda_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
- uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
-
- new_brownout = new_target - new_brownout;
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
-
- powered_by_linreg = mx28_get_vddio_power_source_off();
- if (new_target > cur_target) {
+ uint32_t tmp;
- if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vddioctrl);
- clrbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
+ tmp = readl(&power_regs->hw_power_vddactrl);
+ if (tmp & POWER_VDDACTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
}
+ }
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_BO_OFFSET_MASK);
- do {
- if (new_target - cur_target > 100)
- diff = cur_target + 100;
- else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDIO_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return 1;
}
- } else {
- do {
- if (cur_target - new_target > 100)
- diff = cur_target - 100;
- else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
+ }
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target < cur_target);
+ if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
+ return 1;
+ }
}
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ return 0;
}
-void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+struct mxs_vddx_cfg {
+ uint32_t *reg;
+ uint8_t step_mV;
+ uint16_t lowest_mV;
+ uint16_t highest_mV;
+ int (*powered_by_linreg)(void);
+ uint32_t trg_mask;
+ uint32_t bo_irq;
+ uint32_t bo_enirq;
+ uint32_t bo_offset_mask;
+ uint32_t bo_offset_offset;
+};
+
+#define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+ .reg = POWER_REG(hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+ .step_mV = 25,
+#else
+ .step_mV = 50,
+#endif
+ .lowest_mV = 2800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vddio_power_source_off,
+ .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
+ .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+ .reg = POWER_REG(hw_power_vdddctrl),
+ .step_mV = 25,
+ .lowest_mV = 800,
+ .highest_mV = 1575,
+ .powered_by_linreg = mxs_get_vddd_power_source_off,
+ .trg_mask = POWER_VDDDCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
+ .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vdda_cfg = {
+ .reg = POWER_REG(hw_power_vddactrl),
+ .step_mV = 50,
+ .lowest_mV = 2800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vdda_power_source_off,
+ .trg_mask = POWER_VDDACTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
+ .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
+};
+
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+ .reg = POWER_REG(hw_power_vddmemctrl),
+ .step_mV = 50,
+ .lowest_mV = 1500,
+ .highest_mV = 1700,
+ .powered_by_linreg = NULL,
+ .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
+ .bo_irq = 0,
+ .bo_enirq = 0,
+ .bo_offset_mask = 0,
+ .bo_offset_offset = 0,
+};
+#endif
+
+static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
+ uint32_t new_target, uint32_t new_brownout)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
+ int powered_by_linreg = 0;
+ int adjust_up;
+
+ if (new_target < cfg->lowest_mV)
+ new_target = cfg->lowest_mV;
+ if (new_target > cfg->highest_mV)
+ new_target = cfg->highest_mV;
+
+ new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
- new_brownout = new_target - new_brownout;
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
+ adjust_up = new_target > cur_target;
+ if (cfg->powered_by_linreg)
+ powered_by_linreg = cfg->powered_by_linreg();
- powered_by_linreg = mx28_get_vddd_power_source_off();
- if (new_target > cur_target) {
+ if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vdddctrl);
- clrbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
+ bo_int = readl(cfg->reg);
+ clrbits_le32(cfg->reg, cfg->bo_enirq);
}
+ setbits_le32(cfg->reg, cfg->bo_offset_mask);
+ }
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK);
-
- do {
- if (new_target - cur_target > 100)
+ do {
+ if (abs(new_target - cur_target) > 100) {
+ if (adjust_up)
diff = cur_target + 100;
else
- diff = new_target;
+ diff = cur_target - 100;
+ } else {
+ diff = new_target;
+ }
- diff -= 800;
- diff /= 25;
+ diff -= cfg->lowest_mV;
+ diff /= cfg->step_mV;
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
+ clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
+ if (powered_by_linreg ||
+ (readl(&power_regs->hw_power_sts) &
+ POWER_STS_VDD5V_GT_VDDIO)) {
+ early_delay(500);
+ } else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK)) {
}
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDD_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
}
- } else {
- do {
- if (cur_target - new_target > 100)
- diff = cur_target - 100;
- else
- diff = new_target;
-
- diff -= 800;
- diff /= 25;
-
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
+ } while (new_target > cur_target);
+
+ if (cfg->bo_irq) {
+ if (adjust_up && powered_by_linreg) {
+ writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+ if (bo_int & cfg->bo_enirq)
+ setbits_le32(cfg->reg, cfg->bo_enirq);
+ }
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target < cur_target);
+ clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+ new_brownout << cfg->bo_offset_offset);
}
-
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
-void mx28_setup_batt_detect(void)
+static void mxs_setup_batt_detect(void)
{
- mx28_lradc_init();
- mx28_lradc_enable_batt_measurement();
+ mxs_lradc_init();
+ mxs_lradc_enable_batt_measurement();
early_delay(10);
}
-void mx28_power_init(void)
+static void mxs_ungate_power(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
- mx28_power_clock2xtal();
- mx28_power_clear_auto_restart();
- mx28_power_set_linreg();
- mx28_power_setup_5v_detect();
+#ifdef CONFIG_MX23
+ writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
+#endif
+}
- mx28_setup_batt_detect();
+#ifdef CONFIG_CONFIG_MACH_MX28EVK
+#define auto_restart 1
+#else
+#define auto_restart 0
+#endif
- mx28_power_configure_power_source();
- mx28_enable_output_rail_protection();
+void mxs_power_init(void)
+{
+ mxs_ungate_power();
- mx28_power_set_vddio(3300, 3150);
+ mxs_power_clock2xtal();
+ if (mxs_power_set_auto_restart(auto_restart)) {
+ serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
+ }
+ mxs_power_set_linreg();
- mx28_power_set_vddd(1350, 1200);
+ if (!fixed_batt_supply) {
+ mxs_power_setup_5v_detect();
+ mxs_setup_batt_detect();
+ }
+ mxs_power_configure_power_source();
+ mxs_enable_output_rail_protection();
+
+ mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
+ mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
+ mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
+#ifdef CONFIG_MX23
+ mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
+
+ setbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_LINREG);
+ early_delay(500);
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_ILIMIT);
+#else
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_LINREG);
+#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
-
- writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
-
- early_delay(1000);
+ if (!fixed_batt_supply)
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_set);
}
-#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void)
+#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
+void mxs_power_wait_pswitch(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
projects / karo-tx-uboot.git / blobdiff