*/
#include <common.h>
+#include <errno.h>
+#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/common_def.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
-#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+//#include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
DECLARE_GLOBAL_DATA_PTR;
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-#endif
+static const struct gpio_bank gpio_bank_am33xx[4] = {
+ { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+};
-void reset_cpu(unsigned long ignored)
-{
- /* clear RESET flags */
- writel(~0, PRM_RSTST);
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
-}
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
}
#endif
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_SPL_BUILD
-#ifndef CONFIG_HW_WATCHDOG
- struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-#endif
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
-
- /* UART softreset */
- u32 regVal;
- struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ int ret;
- enable_uart0_pin_mux();
-
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
+ ret = omap_mmc_init(0, 0, 0);
+ if (ret)
+ return ret;
- /* Initialize the Timer */
- timer_init();
+ return omap_mmc_init(1, 0, 0);
+}
+#endif
- preloader_console_init();
+void setup_clocks_for_console(void)
+{
+ /* Not yet implemented */
+ return;
+}
- config_ddr();
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
+ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
- /* Enable MMC0 */
- enable_mmc0_pin_mux();
-#endif
-}
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN (1 << 0)
+#define CM_PHY_OTG_PWRDN (1 << 1)
+#define OTGVDET_EN (1 << 19)
+#define OTGSESSENDEN (1 << 20)
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
{
- int ret = 0;
-#ifdef CONFIG_OMAP_MMC_DEV_0
- ret = omap_mmc_init(0, 0, 0);
- if (ret)
- printf("Error %d while initializing MMC dev 0\n", ret);
-#endif
-#ifdef CONFIG_OMAP_MMC_DEV_1
- ret = omap_mmc_init(1, 0, 0);
- if (ret)
- printf("Error %d while initializing MMC dev 1\n", ret);
-#endif
- return ret;
+ if (on) {
+ clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+ OTGVDET_EN | OTGSESSENDEN);
+ } else {
+ clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+ }
}
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
}
+
+struct omap_musb_board_data otg0_board_data = {
+ .set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+ .mode = CONFIG_AM335X_USB0_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg0_board_data,
+};
#endif
-static u32 cortex_rev(void)
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
{
-
- unsigned int rev;
-
- /* Read Main ID Register (MIDR) */
- asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
-
- return rev;
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
}
-void omap_rev_string(void)
-{
- u32 omap_rev = cortex_rev();
- u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
- u32 major_rev = (omap_rev & 0x00000F00) >> 8;
- u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
+struct omap_musb_board_data otg1_board_data = {
+ .set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+ .mode = CONFIG_AM335X_USB1_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg1_board_data,
+};
+#endif
+#endif
- printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+ musb_register(&otg0_plat, &otg0_board_data,
+ (void *)AM335X_USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+ musb_register(&otg1_plat, &otg1_board_data,
+ (void *)AM335X_USB1_OTG_BASE);
+#endif
+ return 0;
}
projects / karo-tx-uboot.git / blobdiff