Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / imx-common / cpu.c

diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 3d58d8ae9160c7f0ff2e0fceeb03d7a80aeab537..9aad798c1e2e7140fd59f211d2c544b73ad57fb7 100644 (file)
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -29,12 +29,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
 
-static char *get_reset_cause(void)
+char *get_reset_cause(void)
 {
        u32 cause;
        struct src *src_regs = (struct src *)SRC_BASE_ADDR;
@@ -125,5 +126,22 @@ int cpu_mmc_init(bd_t *bis)
 
 void reset_cpu(ulong addr)
 {
+       struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+       /* Clear the reset status flags */
+       writel(readl(&src_regs->srsr), &src_regs->srsr);
+
        __raw_writew(4, WDOG1_BASE_ADDR);
 }
+
+u32 get_ahb_clk(void)
+{
+       struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg, ahb_podf;
+
+       reg = __raw_readl(&imx_ccm->cbcdr);
+       reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+       ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+       return get_periph_clk() / (ahb_podf + 1);
+}