Merge branch 'master' of git://git.denx.de/u-boot-imx

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / keystone / clock.c

diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index 03c1d9f660fffcf29df7e25d999a97491f05f400..d13fbc1a4bb99cb4e59bb62663644e7462e58cba 100644 (file)
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -11,6 +11,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
+#define MAX_SPEEDS             13
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
        int i;
@@ -172,7 +174,7 @@ void init_pll(const struct pll_init_data *data)
                 * bypass disabled
                 */
                bwadj = pllm >> 1;
-               tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
+               tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
                        (pllm << PLL_MULT_SHIFT) |
                        (plld & PLL_DIV_MASK) |
                        (pllod << PLL_CLKOD_SHIFT);
@@ -183,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
                tmp &= ~(PLL_BWADJ_HI_MASK);
                tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
-               /* set PLL Select (bit 13) for PASS PLL */
-               if (data->pll == PASS_PLL)
-                       tmp |= PLLCTL_PAPLL;
-
                __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
                /* Reset bit: bit 14 for both DDR3 & PASS PLL */
@@ -218,3 +216,57 @@ void init_plls(int num_pll, struct pll_init_data *config)
        for (i = 0; i < num_pll; i++)
                init_pll(&config[i]);
 }
+
+static int get_max_speed(u32 val, int *speeds)
+{
+       int j;
+
+       if (!val)
+               return speeds[0];
+
+       for (j = 1; j < MAX_SPEEDS; j++) {
+               if (val == 1)
+                       return speeds[j];
+               val >>= 1;
+       }
+
+       return SPD800;
+}
+
+#ifdef CONFIG_SOC_K2HK
+static u32 read_efuse_bootrom(void)
+{
+       return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
+               __raw_readl(KS2_REV1_DEVSPEED);
+}
+#else
+static inline u32 read_efuse_bootrom(void)
+{
+       return __raw_readl(KS2_EFUSE_BOOTROM);
+}
+#endif
+
+inline int get_max_dev_speed(void)
+{
+       return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
+}
+
+#ifndef CONFIG_SOC_K2E
+inline int get_max_arm_speed(void)
+{
+       return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+}
+#endif
+
+void pass_pll_pa_clk_enable(void)
+{
+       u32 reg;
+
+       reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+       reg |= PLLCTL_PAPLL;
+       writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+       /* wait till clock is enabled */
+       sdelay(15000);
+}