#include <generated/asm-offsets.h>
#include <linux/linkage.h>
+.section ".text.init", "x"
+
+.macro init_arm_erratum
+ /* ARM erratum ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+.endm
+
/*
* L2CC Cache setup/invalidation/disable
*/
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
+ ldr r0, =0xC0 | /* tag RAM */ \
+ 0x4 | /* data RAM */ \
+ 1 << 24 | /* disable write allocate delay */ \
+ 1 << 23 | /* disable write allocate combine */ \
+ 1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
+ orrls r0, r0, #1 << 25
#endif
mcr 15, 1, r0, c9, c0, 2
ldr r1, =0x00000203
str r1, [r0, #0x40]
- ldr r1, =0x0
- str r1, [r0, #0x44]
+ str r4, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
.endm /* init_m4if */
.macro setup_pll pll, freq
- ldr r2, =\pll
+ ldr r0, =\pll
+ adr r2, W_DP_\freq
+ bl setup_pll_func
+.endm
+
+#define W_DP_OP 0
+#define W_DP_MFD 4
+#define W_DP_MFN 8
+
+setup_pll_func:
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq
- str r1, [r2, #PLL_DP_OP]
- str r1, [r2, #PLL_DP_HFS_OP]
+ ldr r1, [r2, #W_DP_OP]
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq
- str r1, [r2, #PLL_DP_MFD]
- str r1, [r2, #PLL_DP_HFS_MFD]
+ ldr r1, [r2, #W_DP_MFD]
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq
- str r1, [r2, #PLL_DP_MFN]
- str r1, [r2, #PLL_DP_HFS_MFN]
+ ldr r1, [r2, #W_DP_MFN]
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-101:
- ldr r1, [r2, #PLL_DP_CTL]
+ str r1, [r0, #PLL_DP_CTL]
+1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
- beq 101b
-.endm
+ beq 1b
+
+ /* r10 saved upper lr */
+ mov pc, lr
.macro setup_pll_errata pll, freq
ldr r2, =\pll
- mov r1, #0x0
- str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
.endm
.macro init_clock
+#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
-#elif defined(CONFIG_TX53)
- @ CCGR registers have been setup via DCD
-#else
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR7]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x0F00030F
- str r1, [r0, #CLKCTL_CCGR6]
-#endif
/* Switch ARM to step clock */
mov r1, #0x4
#endif
#endif
-#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
- ldr r1, =0x000010C0
- orr r1, r1, #CONFIG_SYS_DDR_CLKSEL
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
/* Switch peripheral to PLL2 */
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
-#elif defined(CONFIG_TX53)
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL 3 */
- ldr r1, [r0, #CLKCTL_CBCMR]
- bic r1, #(0x3 << 12)
- orr r1, r1, #(1 << 12)
+ ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, [r0, #CLKCTL_CBCDR]
- orr r1, r1, #(1 << 25)
- str r1, [r0, #CLKCTL_CBCDR]
-1:
- /* make sure change is effective */
- ldr r1, [r0, #CLKCTL_CDHIPR]
- tst r1, #0x7f
- bne 1b
-#if CONFIG_SYS_SDRAM_CLK == 400
- setup_pll PLL2_BASE_ADDR, 400
-#elif CONFIG_SYS_SDRAM_CLK == 333
- setup_pll PLL2_BASE_ADDR, 333
-#else
-#error Unsupported CONFIG_SYS_SDRAM_CLK
-#endif
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, [r0, #CLKCTL_CBCDR]
- bic r1, #(1 << 25)
- str r1, [r0, #CLKCTL_CBCDR]
-
- ldr r1, [r0, #CLKCTL_CBCMR]
- bic r1, #(3 << 12)
- orr r1, #(2 << 12)
- str r1, [r0, #CLKCTL_CBCMR]
-
- /* make sure change is effective */
-1:
- ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-#endif
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
-#else
- mov r1, #0
-#endif
+
str r1, [r0, #CLKCTL_CACRR]
+
/* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
+ str r4, [r0, #CLKCTL_CCSR]
-#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
-#endif
-#ifndef CONFIG_TX53
+
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
- str r1, [r0, #CLKCTL_CCGR7]
-#endif
-#endif
-#if !defined(CONFIG_TX53)
-#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ str r4, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+#else /* CONFIG_MX53 */
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x0F00030F
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1_BASE_ADDR, 800
+
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02888945
+ orr r1, r1, #(1 << 16)
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL2_BASE_ADDR, 400
+
/* Switch peripheral to PLL2 */
ldr r1, =0x00808145
orr r1, r1, #(2 << 10)
ldr r1, =0x00016154
str r1, [r0, #CLKCTL_CBCMR]
- /* Change uart clk parent to pll2*/
+
+ /*change uart clk parent to pll2*/
ldr r1, [r0, #CLKCTL_CSCMR1]
bic r1, #(0x3 << 24)
orr r1, r1, #(0x1 << 24)
str r1, [r0, #CLKCTL_CSCMR1]
+
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ setup_pll PLL4_BASE_ADDR, 455
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000124
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* make uart div=6 */
ldr r1, [r0, #CLKCTL_CSCDR1]
bic r1, #(0x3f << 0)
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
-#endif
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
-#endif
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+
+#endif /* CONFIG_MX53 */
.endm
.macro setup_wdog
strh r1, [r0]
.endm
-.section ".text.init", "x"
-
ENTRY(lowlevel_init)
-#if defined(CONFIG_MX51)
+ mov r10, lr
+ mov r4, #0 /* Fix R4 to 0 */
+
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
+ orr r1, r1, #1 << 23
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
+ orr r1, r1, #1 << 23
str r1, [r0, #0x4]
#endif
+ init_arm_erratum
+
init_l2cc
init_aips
init_clock
- /* r12 saved upper lr*/
- mov pc,lr
+ mov pc, r10
ENDPROC(lowlevel_init)
/* Board level setting value */
-W_DP_OP_864: .word DP_OP_864
-W_DP_MFD_864: .word DP_MFD_864
-W_DP_MFN_864: .word DP_MFN_864
-W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_665: .word DP_OP_665
-W_DP_MFD_665: .word DP_MFD_665
-W_DP_MFN_665: .word DP_MFN_665
-W_DP_OP_600: .word DP_OP_600
-W_DP_MFD_600: .word DP_MFD_600
-W_DP_MFN_600: .word DP_MFN_600
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_333: .word DP_OP_333
-W_DP_MFD_333: .word DP_MFD_333
-W_DP_MFN_333: .word DP_MFN_333
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864: .word DP_OP_864
+ .word DP_MFD_864
+ .word DP_MFN_864
+W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
+#else
+W_DP_800: .word DP_OP_800
+ .word DP_MFD_800
+ .word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665: .word DP_OP_665
+ .word DP_MFD_665
+ .word DP_MFN_665
+W_DP_600: .word DP_OP_600
+ .word DP_MFD_600
+ .word DP_MFN_600
+#endif
+W_DP_216: .word DP_OP_216
+ .word DP_MFD_216
+ .word DP_MFN_216
+W_DP_400: .word DP_OP_400
+ .word DP_MFD_400
+ .word DP_MFN_400
+W_DP_455: .word DP_OP_455
+ .word DP_MFD_455
+ .word DP_MFN_455
projects / karo-tx-uboot.git / blobdiff