+#else /* CONFIG_TX53 */
+ /* Switch peripheral to PLL 3 */
+ ldr r1, [r0, #CLKCTL_CBCMR]
+ bic r1, #(0x3 << 12)
+ orr r1, r1, #(1 << 12)
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ ldr r1, [r0, #CLKCTL_CBCDR]
+ orr r1, r1, #(1 << 25)
+ str r1, [r0, #CLKCTL_CBCDR]
+1:
+ /* make sure change is effective */
+ ldr r1, [r0, #CLKCTL_CDHIPR]
+ tst r1, #0x7f
+ bne 1b
+
+#if CONFIG_SYS_SDRAM_CLK == 533
+ setup_pll PLL2_BASE_ADDR, 533
+#elif CONFIG_SYS_SDRAM_CLK == 400
+ setup_pll PLL2_BASE_ADDR, 400
+#elif CONFIG_SYS_SDRAM_CLK == 333
+ setup_pll PLL2_BASE_ADDR, 333
+#else
+#error Unsupported CONFIG_SYS_SDRAM_CLK
+#endif
+
+ /* Switch peripheral to PLL2 */
+ ldr r1, [r0, #CLKCTL_CBCDR]
+ bic r1, #(1 << 25)
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, [r0, #CLKCTL_CBCMR]
+ bic r1, #(3 << 12)
+ orr r1, #(2 << 12)
+ str r1, [r0, #CLKCTL_CBCMR]
+#endif
+ setup_pll PLL3_BASE_ADDR, 216
+