Merge 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index cf3a38e81393dbb5cbbbc193a25c25a4b6a7ee5a..f12bba2944a915558c24738760f80d0d72d2b3b3 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -94,12 +95,38 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
                div = __raw_readl(&imx_ccm->analog_pll_enet);
                div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 
-               return (div == 3 ? 125000000 : 25000000 * (div << 1));
+               return 25000000 * (div + (div >> 1) + 1);
        default:
                return 0;
        }
        /* NOTREACHED */
 }
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+       u32 div;
+       u64 freq;
+
+       switch (pll) {
+       case PLL_BUS:
+               if (pfd_num == 3) {
+                       /* No PFD3 on PPL2 */
+                       return 0;
+               }
+               div = __raw_readl(&imx_ccm->analog_pfd_528);
+               freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+               break;
+       case PLL_USBOTG:
+               div = __raw_readl(&imx_ccm->analog_pfd_480);
+               freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+               break;
+       default:
+               /* No PFD on other PLL                                       */
+               return 0;
+       }
+
+       return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+                             ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
 
 static u32 get_mcu_main_clk(void)
 {
@@ -144,13 +171,14 @@ u32 get_periph_clk(void)
                        freq = decode_pll(PLL_BUS, MXC_HCLK);
                        break;
                case 1:
-                       freq = PLL2_PFD2_FREQ;
+                       freq = mxc_get_pll_pfd(PLL_BUS, 2);
                        break;
                case 2:
-                       freq = PLL2_PFD0_FREQ;
+                       freq = mxc_get_pll_pfd(PLL_BUS, 0);
                        break;
                case 3:
-                       freq = PLL2_PFD2_DIV_FREQ;
+                       /* static / 2 divider */
+                       freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
                        break;
                default:
                        break;
@@ -184,7 +212,7 @@ static u32 get_ipg_per_clk(void)
 static u32 get_uart_clk(void)
 {
        u32 reg, uart_podf;
-       u32 freq = PLL3_80M;
+       u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
 #ifdef CONFIG_MX6SL
        if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
@@ -204,7 +232,7 @@ static u32 get_cspi_clk(void)
        reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
        cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       return  PLL3_60M / (cspi_podf + 1);
+       return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
 
 static u32 get_axi_clk(void)
@@ -217,9 +245,9 @@ static u32 get_axi_clk(void)
 
        if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
                if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-                       root_freq = PLL2_PFD2_FREQ;
+                       root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
                else
-                       root_freq = PLL3_PFD1_FREQ;
+                       root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
        } else
                root_freq = get_periph_clk();
 
@@ -244,10 +272,10 @@ static u32 get_emi_slow_clk(void)
                root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
                break;
        case 2:
-               root_freq = PLL2_PFD2_FREQ;
+               root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
                break;
        case 3:
-               root_freq = PLL2_PFD0_FREQ;
+               root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
                break;
        }
 
@@ -270,19 +298,31 @@ static u32 get_mmdc_ch0_clk(void)
                freq = decode_pll(PLL_BUS, MXC_HCLK);
                break;
        case 1:
-               freq = PLL2_PFD2_FREQ;
+               freq = mxc_get_pll_pfd(PLL_BUS, 2);
                break;
        case 2:
-               freq = PLL2_PFD0_FREQ;
+               freq = mxc_get_pll_pfd(PLL_BUS, 0);
                break;
        case 3:
-               freq = PLL2_PFD2_DIV_FREQ;
+               /* static / 2 divider */
+               freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
        }
 
        return freq / (podf + 1);
 
 }
+#else
+static u32 get_mmdc_ch0_clk(void)
+{
+       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+       u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+                               MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+       return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+#endif
 
+#ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(void)
 {
        u32 reg = 0;
@@ -311,16 +351,6 @@ int enable_fec_anatop_clock(void)
 
        return 0;
 }
-
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-       u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-                               MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-       return get_periph_clk() / (mmdc_ch0_podf + 1);
-}
 #endif
 
 static u32 get_usdhc_clk(u32 port)
@@ -359,9 +389,9 @@ static u32 get_usdhc_clk(u32 port)
        }
 
        if (clk_sel)
-               root_freq = PLL2_PFD0_FREQ;
+               root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
        else
-               root_freq = PLL2_PFD2_FREQ;
+               root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 
        return root_freq / (usdhc_podf + 1);
 }