Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / emif-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 11e830a533bd6106bf92325d5fbdac6518e2267a..ece365507c21510f8953299e0a12a5ad91798d09 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -6,28 +6,12 @@
  *
  * Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
@@ -209,7 +193,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-       if (omap_revision() >= OMAP5430_ES1_0) {
+       if ((omap_revision() >= OMAP5430_ES1_0) ||
+                               (omap_revision() == DRA752_ES1_0)) {
                writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
                        &emif->emif_l3_config);
        } else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -263,6 +248,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
        __udelay(130);
 }
 
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+       config_data_eye_leveling_samples(base);
+
+       writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+       writel(regs->sdram_config, &emif->emif_sdram_config);
+}
+
 static void ddr3_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -273,6 +270,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
         * defined, contents of mode Registers must be fully initialized.
         * H/W takes care of this initialization
         */
+       writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
        writel(regs->sdram_config_init, &emif->emif_sdram_config);
 
        writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
@@ -290,7 +288,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        /* enable leveling */
        writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 
-       ddr3_leveling(base, regs);
+       if (omap_revision() == DRA752_ES1_0)
+               ddr3_sw_leveling(base, regs);
+       else
+               ddr3_leveling(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1078,7 +1079,10 @@ static void do_sdram_init(u32 base)
        if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
                set_lpmode_selfrefresh(base);
                emif_reset_phy(base);
-               ddr3_leveling(base, regs);
+               if (omap_revision() == DRA752_ES1_0)
+                       ddr3_sw_leveling(base, regs);
+               else
+                       ddr3_leveling(base, regs);
        }
 
        /* Write to the shadow registers */
@@ -1180,6 +1184,9 @@ void dmm_init(u32 base)
        /* TRAP for invalid TILER mappings in section 0 */
        lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+       if (omap_revision() >= OMAP4460_ES1_0)
+               lis_map_regs_calculated.is_ma_present = 1;
+
        lisa_map_regs = &lis_map_regs_calculated;
 #endif
        struct dmm_lisa_map_regs *hw_lisa_map_regs =