Merge branch 'u-boot/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap3 / clock.c

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 567817e0ec3b062c3ee2a66c901b14ab1b44a8b2..1bc27bdc7fdabc81a599eb012a65d8b783c6b45f 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -9,25 +9,12 @@
  *      Richard Woodruff <r-woodruff2@ti.com>
  *      Syed Mohammed Khasim <khasim@ti.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/clocks_omap3.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
@@ -196,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
                 * if running from flash, jump to small relocated code
                 * area in SRAM.
                 */
-               f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
-                               SRAM_VECT_CODE);
+               f_lock_pll = (void *) (SRAM_CLK_CODE);
 
                p0 = readl(&prcm_base->clken_pll);
                sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
@@ -414,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
                 * if running from flash, jump to small relocated code
                 * area in SRAM.
                 */
-               f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
-                               SRAM_VECT_CODE);
+               f_lock_pll = (void *) (SRAM_CLK_CODE);
 
                p0 = readl(&prcm_base->clken_pll);
                sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
@@ -491,6 +476,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
        wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 }
 
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+       struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+       dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+       /* Moving it to the right sysclk base */
+       ptr = ptr + clk_index;
+
+       /* PER2 DPLL (DPLL5) */
+       sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+       wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+       sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+       sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+       sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+       sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
+       wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
 {
        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -572,6 +575,22 @@ void prcm_init(void)
        }
 
        if (get_cpu_family() == CPU_OMAP36XX) {
+               /*
+                * In warm reset conditions on OMAP36xx/AM/DM37xx
+                * the rom code incorrectly sets the DPLL4 clock
+                * input divider to /6.5. Section 3.5.3.3.3.2.1 of
+                * the AM/DM37x TRM explains that the /6.5 divider
+                * is used only when the input clock is 13MHz.
+                *
+                * If the part is in this cpu family *and* the input
+                * clock *is not* 13 MHz, then reset the DPLL4 clock
+                * input divider to /1 as it should never set to /6.5
+                * in this case.
+                */
+               if (sys_clkin_sel != 1) /* 13 MHz */
+                       /* Bit 8: DPLL4_CLKINP_DIV */
+                       sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+
                /* Unlock MPU DPLL (slows things down, and needed later) */
                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
                wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
@@ -579,7 +598,7 @@ void prcm_init(void)
 
                dpll3_init_36xx(0, clk_index);
                dpll4_init_36xx(0, clk_index);
-               dpll5_init_34xx(0, clk_index);
+               dpll5_init_36xx(0, clk_index);
                iva_init_36xx(0, clk_index);
                mpu_init_36xx(0, clk_index);
 
@@ -689,7 +708,7 @@ void per_clocks_enable(void)
        sr32(&prcm_base->iclken_per, 17, 1, 1);
 #endif
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
        /* Turn on all 3 I2C clocks */
        sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
        sr32(&prcm_base->iclken1_core, 15, 3, 0x7);     /* I2C1,2,3 = on */
@@ -711,8 +730,6 @@ void per_clocks_enable(void)
                sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
                sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
        }
-       sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
-       sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
 
        sdelay(1000);
 }