* Copyright (C) 2004-2010
* Texas Instruments Incorporated - http://www.ti.com/
*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
* Author :
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Shashi Ranjan <shashiranjanmca05@gmail.com>
* Manikandan Pillai <mani.pillai@ti.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
/*
* make_cs1_contiguous -
- * - For es2 and above remap cs1 behind cs0 to allow command line
- * mem=xyz use all memory with out discontinuous support compiled in.
- * Could do it at the ATAG, but there really is two banks...
- * - Called as part of 2nd phase DDR init.
+ * - When we have CS1 populated we want to have it mapped after cs0 to allow
+ * command line mem=xyz use all memory with out discontinuous support
+ * compiled in. We could do it in the ATAG, but there really is two banks...
*/
void make_cs1_contiguous(void)
{
return 0;
offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x30) << 17;
+ offset = (offset & 15) << 27 | (offset & 0x300) << 17;
return offset;
}
+/*
+ * write_sdrc_timings -
+ * - Takes CS and associated timings and initalize SDRAM
+ * - Test CS to make sure it's OK for use
+ */
+static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
+ struct board_sdrc_timings *timings)
+{
+ /* Setup timings we got from the board. */
+ writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+ writel(timings->ctrla, &sdrc_actim_base->ctrla);
+ writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+ writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(timings->mr, &sdrc_base->cs[cs].mr);
+
+ /*
+ * Test ram in this bank
+ * Disable if bad or not present
+ */
+ if (!mem_ok(cs))
+ writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
/*
* do_sdrc_init -
- * - Initialize the SDRAM for use.
- * - code called once in C-Stack only context for CS0 and a possible 2nd
- * time depending on memory configuration from stack+global context
+ * - Code called once in C-Stack only context for CS0 and with early being
+ * true and a possible 2nd time depending on memory configuration from
+ * stack+global context.
*/
void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+ struct board_sdrc_timings timings;
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+
+ /*
+ * When called in the early context this may be SPL and we will
+ * need to set all of the timings. This ends up being board
+ * specific so we call a helper function to take care of this
+ * for us. Otherwise, to be safe, we need to copy the settings
+ * from the first bank to the second. We will setup CS0,
+ * then set cs_cfg to the appropriate value then try and
+ * setup CS1.
+ */
+#ifdef CONFIG_SPL_BUILD
+ get_board_mem_timings(&timings);
+#endif
if (early) {
/* reset sdrc controller */
writel(SOFTRESET, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
writel(SDRC_SHARING, &sdrc_base->sharing);
- /* Disable Power Down of CKE cuz of 1 CKE on combo part */
+ /* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
&sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
- }
+#ifdef CONFIG_SPL_BUILD
+ write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
+ make_cs1_contiguous();
+ write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
+#endif
- /*
- * SDRC timings are set up by x-load or config header
- * We don't need to redo them here.
- * Older x-loads configure only CS0
- * configure CS1 to handle this ommission
- */
- if (cs) {
- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
- sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- writel(readl(&sdrc_base->cs[CS0].mcfg),
- &sdrc_base->cs[CS1].mcfg);
- writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
- &sdrc_base->cs[CS1].rfr_ctrl);
- writel(readl(&sdrc_actim_base0->ctrla),
- &sdrc_actim_base1->ctrla);
- writel(readl(&sdrc_actim_base0->ctrlb),
- &sdrc_actim_base1->ctrlb);
-
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(readl(&sdrc_base->cs[CS0].mr),
- &sdrc_base->cs[CS1].mr);
}
/*
- * Test ram in this bank
- * Disable if bad or not present
+ * If we aren't using SPL we have been loaded by some
+ * other means which may not have correctly initialized
+ * both CS0 and CS1 (such as some older versions of x-loader)
+ * so we may be asked now to setup CS1.
*/
- if (!mem_ok(cs))
- writel(0, &sdrc_base->cs[cs].mcfg);
+ if (cs == CS1) {
+ timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+ timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+ timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+ timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+ timings.mr = readl(&sdrc_base->cs[CS0].mr);
+ write_sdrc_timings(cs, sdrc_actim_base1, &timings);
+ }
}
/*
*/
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
/*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
+ * We always need to have cs_cfg point at where the second
+ * bank would be, if present. Failure to do so can lead to
+ * strange situations where memory isn't detected and
+ * configured correctly. CS0 will already have been setup
+ * at this point.
*/
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
- do_sdrc_init(CS1, NOT_EARLY);
- make_cs1_contiguous();
+ make_cs1_contiguous();
+ do_sdrc_init(CS1, NOT_EARLY);
+ size1 = get_sdr_cs_size(CS1);
- size1 = get_sdr_cs_size(CS1);
- }
gd->ram_size = size0 + size1;
return 0;
void dram_init_banksize (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
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