#include <common.h>
#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
+#include <miiphy.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+#if defined(CONFIG_DISPLAY_CPUINFO)
/*
- * Write the reset manager register to cause reset
+ * Print CPU information
*/
-void reset_cpu(ulong addr)
+int print_cpuinfo(void)
{
- /* request a warm reset */
- writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
- /*
- * infinite loop here as watchdog will trigger and reset
- * the processor
- */
- while (1)
- ;
+ puts("CPU : Altera SOCFPGA Platform\n");
+ return 0;
}
+#endif
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
{
- writel(0, &reset_manager_base->per_mod_reset);
+ return 0;
}
-int dram_init(void)
+
+/*
+ * DesignWare Ethernet initialization
+ */
+int cpu_eth_init(bd_t *bis)
{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+ /* initialize and register the emac */
+ return designware_initialize(CONFIG_EMAC_BASE,
+ CONFIG_PHY_INTERFACE_MODE);
+#else
return 0;
+#endif
}