_bss_start_ofs:
.word __bss_start - _start
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
- .word __image_copy_end - _start
-
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
reset:
bl save_boot_params
/*
- * set the cpu to SVC32 mode
+ * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
+ * except if in HYP mode already
*/
mrs r0, cpsr
- bic r0, r0, #0x1f
- orr r0, r0, #0xd3
+ and r1, r0, #0x1f @ mask mode bits
+ teq r1, #0x1a @ test for HYP mode
+ bicne r0, r0, #0x1f @ clear all mode bits
+ orrne r0, r0, #0x13 @ set SVC mode
+ orr r0, r0, #0xc0 @ disable FIQ and IRQ
msr cpsr,r0
/*
bx lr
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA)
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
-#endif /* !Tegra */
bx lr
@ spots for abort stack
str lr, [r0] @ save caller lr in position 0
@ of saved stack
- mrs r0, spsr @ get the spsr
+ mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of
@ saved stack
+ ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm