Merge branch 'master' of git://git.denx.de/u-boot-atmel

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 1eae9767d0da4ecad39f70be69727d904a141732..e2a78676b1654fc6fece0f6fe9058957fe04c595 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -16,12 +16,39 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       struct sunxi_prcm_reg * const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+       /* Set PLL ldo voltage without this PLL6 does not work properly */
+       clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+                       PRCM_PLL_CTRL_LDO_KEY);
+       clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+               PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+               PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+       clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+       clock_set_pll1(408000000);
+
+       writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+
+       writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+       writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
 void clock_init_uart(void)
 {
+#if CONFIG_CONS_INDEX < 5
        struct sunxi_ccm_reg *const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-#if CONFIG_CONS_INDEX < 5
        /* uart clock source is apb2 */
        writel(APB2_CLK_SRC_OSC24M|
               APB2_CLK_RATE_N_1|
@@ -41,9 +68,6 @@ void clock_init_uart(void)
        /* enable R_PIO and R_UART clocks, and de-assert resets */
        prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
 #endif
-
-       /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
-       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
 
 int clock_twi_onoff(int port, int state)
@@ -65,6 +89,87 @@ int clock_twi_onoff(int port, int state)
        return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int p = 0;
+       int k = 1;
+       int m = 1;
+
+       if (clk > 1152000000) {
+               k = 2;
+       } else if (clk > 768000000) {
+               k = 3;
+               m = 2;
+       }
+
+       /* Switch to 24MHz clock while changing PLL1 */
+       writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+              ATB_DIV_2 << ATB_DIV_SHIFT |
+              CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_axi_cfg);
+
+       /*
+        * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
+        * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
+        */
+       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
+              CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+              CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+       sdelay(200);
+
+       /* Switch CPU to PLL1 */
+       writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+              ATB_DIV_2 << ATB_DIV_SHIFT |
+              CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll3(unsigned int clk)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+
+       if (clk == 0) {
+               clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+               return;
+       }
+
+       /* PLL3 rate = 24000000 * n / m */
+       writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+              CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
+              &ccm->pll3_cfg);
+}
+
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int max_n = 32;
+       int k = 1, m = 2;
+
+       if (sigma_delta_enable)
+               writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
+
+       /* PLL5 rate = 24000000 * n * k / m */
+       if (clk > 24000000 * k * max_n / m) {
+               m = 1;
+               if (clk > 24000000 * k * max_n / m)
+                       k = 2;
+       }
+       writel(CCM_PLL5_CTRL_EN |
+              (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
+              CCM_PLL5_CTRL_UPD |
+              CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
+              CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+       udelay(5500);
+}
+
 unsigned int clock_get_pll6(void)
 {
        struct sunxi_ccm_reg *const ccm =
@@ -74,3 +179,15 @@ unsigned int clock_get_pll6(void)
        int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
        return 24000000 * n * k / 2;
 }
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+       int pll = clock_get_pll6() * 2;
+       int div = 1;
+
+       while ((pll / div) > hz)
+               div++;
+
+       writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
+              clk_cfg);
+}