am33xx: Update DT files, add am335x_gp_evm_config target

[karo-tx-uboot.git] / arch / arm / dts / zynq-zc770-xm010.dts

diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 5e661749772b3b1ce235e3c1923c2fa71dd079b9..da3a182ea1e1706a513048949686d5f01051e5b3 100644 (file)
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -1,7 +1,7 @@
 /*
  * Xilinx ZC770 XM010 board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -9,15 +9,85 @@
 #include "zynq-7000.dtsi"
 
 / {
-       model = "Zynq ZC770 XM010 Board";
        compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+       model = "Xilinx Zynq";
 
        aliases {
+               ethernet0 = &gem0;
+               i2c0 = &i2c0;
                serial0 = &uart1;
+               spi0 = &spi1;
        };
 
-       memory {
+       chosen {
+               bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+               linux,stdout-path = &uart1;
+               stdout-path = &uart1;
+       };
+
+       memory@0 {
                device_type = "memory";
-               reg = <0 0x40000000>;
+               reg = <0x0 0x40000000>;
+       };
+
+       usb_phy0: phy0 {
+               compatible = "usb-nop-xceiv";
+               #phy-cells = <0>;
+       };
+};
+
+&spi1 {
+       status = "okay";
+       num-cs = <4>;
+       is-decoded-cs = <0>;
+       flash@0 {
+               compatible = "sst25wf080";
+               reg = <1>;
+               spi-max-frequency = <1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               partition@test {
+                       label = "spi-flash";
+                       reg = <0x0 0x100000>;
+               };
+       };
+};
+
+&can0 {
+       status = "okay";
+};
+
+&gem0 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy>;
+
+       ethernet_phy: ethernet-phy@7 {
+               reg = <7>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       m24c02_eeprom@52 {
+               compatible = "at,24c02";
+               reg = <0x52>;
        };
+
+};
+
+&sdhci0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "host";
+       usb-phy = <&usb_phy0>;
 };