config: rename CONFIG_MX* to CONFIG_SOC_MX*

[karo-tx-uboot.git] / arch / arm / imx-common / iomux-v3.c

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index da093fbe1489ec516dfd41ea136377f0529563df..9ec1a3cf9e3b1b337fc408deb861c9d585933ffa 100644 (file)
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -6,23 +6,14 @@
  *
  * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#if !defined(CONFIG_SOC_MX25) && !defined(CONFIG_SOC_VF610)
+#include <asm/arch/sys_proto.h>
+#endif
 #include <asm/imx-common/iomux-v3.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -30,7 +21,7 @@ static void *base = (void *)IOMUXC_BASE_ADDR;
 /*
  * configures a single pad in the iomuxer
  */
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 {
        u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
        u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
@@ -42,29 +33,62 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
+#if defined CONFIG_SOC_MX6SL
+       /* Check whether LVE bit needs to be set */
+       if (pad_ctrl & PAD_CTL_LVE) {
+               pad_ctrl &= ~PAD_CTL_LVE;
+               pad_ctrl |= PAD_CTL_LVE_BIT;
+       }
+#endif
+#ifdef DEBUG
+       printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
+               i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
+               pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
+#endif
+
        if (mux_ctrl_ofs)
                __raw_writel(mux_mode, base + mux_ctrl_ofs);
 
        if (sel_input_ofs)
                __raw_writel(sel_input, base + sel_input_ofs);
 
-       if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+       if (pad & PAD_CTRL_VALID)
+               __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+                       base + pad_ctrl_ofs);
+#else
+       if ((pad & PAD_CTRL_VALID) && pad_ctrl_ofs)
                __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
-       return 0;
+#endif
 }
 
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+                                     unsigned count)
 {
-       iomux_v3_cfg_t *p = pad_list;
+       iomux_v3_cfg_t const *p = pad_list;
+       int stride;
        int i;
-       int ret;
 
+#if defined(CONFIG_SOC_MX6QDL)
+       stride = 2;
+       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+               p += 1;
+#else
+       stride = 1;
+#endif
        for (i = 0; i < count; i++) {
-               ret = imx_iomux_v3_setup_pad(*p);
-               if (ret)
-                       return ret;
-               p++;
+               imx_iomux_v3_setup_pad(*p);
+               p += stride;
        }
-       return 0;
+}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+                               int num_bits, int value)
+{
+       u32 reg = readl(base + group * 4);
+
+       reg &= ~(((1 << num_bits) - 1) << start_bit);
+       reg |= value << start_bit;
+       writel(reg, base + group * 4);
 }