am335x: Update timings for the beaglebone again

[karo-tx-uboot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index ae43ef8778580aba42f8784d6eaa55e35be2073a..914df015250f87ac2f18eb87fd600641b1b7835d 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -28,6 +28,7 @@
 #define VTP_CTRL_START_EN      (0x1)
 #define PHY_DLL_LOCK_DIFF      0x0
 #define DDR_CKE_CTRL_NORMAL    0x1
+#define PHY_EN_DYN_PWRDN       (0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY     0x100005
@@ -82,6 +83,23 @@
 #define MT41J256M8HX15E_PHY_FIFO_WE            0x100
 #define MT41J256M8HX15E_IOCTRL_VALUE           0x18B
 
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY    0x100007
+#define MT41K256M16HA125E_EMIF_TIM1            0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2            0x26437FDA
+#define MT41K256M16HA125E_EMIF_TIM3            0x501F83FF
+#define MT41K256M16HA125E_EMIF_SDCFG           0x61C052B2
+#define MT41K256M16HA125E_EMIF_SDREF           0xC30
+#define MT41K256M16HA125E_ZQ_CFG               0x50074BE4
+#define MT41K256M16HA125E_DLL_LOCK_DIFF                0x1
+#define MT41K256M16HA125E_RATIO                        0x80
+#define MT41K256M16HA125E_INVERT_CLKOUT                0x0
+#define MT41K256M16HA125E_RD_DQS               0x3A
+#define MT41K256M16HA125E_WR_DQS               0x42
+#define MT41K256M16HA125E_PHY_WR_DATA          0x7E
+#define MT41K256M16HA125E_PHY_FIFO_WE          0x9B
+#define MT41K256M16HA125E_IOCTRL_VALUE         0x18B
+
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
 #define MT41J512M8RH125_EMIF_READ_LATENCY      0x06
 #define MT41J512M8RH125_EMIF_TIM1              0x0888A39B
@@ -99,20 +117,65 @@
 #define MT41J512M8RH125_PHY_WR_DATA            0x74
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
+/**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs);
+void config_sdram(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs);
+void set_sdram_timings(const struct emif_regs *regs, int nr);
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs);
+void config_ddr_phy(const struct emif_regs *regs, int nr);
+
+struct ddr_cmd_regs {
+       unsigned int resv0[7];
+       unsigned int cm0csratio;        /* offset 0x01C */
+       unsigned int resv1[2];
+       unsigned int cm0dldiff;         /* offset 0x028 */
+       unsigned int cm0iclkout;        /* offset 0x02C */
+       unsigned int resv2[8];
+       unsigned int cm1csratio;        /* offset 0x050 */
+       unsigned int resv3[2];
+       unsigned int cm1dldiff;         /* offset 0x05C */
+       unsigned int cm1iclkout;        /* offset 0x060 */
+       unsigned int resv4[8];
+       unsigned int cm2csratio;        /* offset 0x084 */
+       unsigned int resv5[2];
+       unsigned int cm2dldiff;         /* offset 0x090 */
+       unsigned int cm2iclkout;        /* offset 0x094 */
+       unsigned int resv6[3];
+};
+
+struct ddr_data_regs {
+       unsigned int dt0rdsratio0;      /* offset 0x0C8 */
+       unsigned int resv1[4];
+       unsigned int dt0wdsratio0;      /* offset 0x0DC */
+       unsigned int resv2[4];
+       unsigned int dt0wiratio0;       /* offset 0x0F0 */
+       unsigned int resv3;
+       unsigned int dt0wimode0;        /* offset 0x0F8 */
+       unsigned int dt0giratio0;       /* offset 0x0FC */
+       unsigned int resv4;
+       unsigned int dt0gimode0;        /* offset 0x104 */
+       unsigned int dt0fwsratio0;      /* offset 0x108 */
+       unsigned int resv5[4];
+       unsigned int dt0dqoffset;       /* offset 0x11C */
+       unsigned int dt0wrsratio0;      /* offset 0x120 */
+       unsigned int resv6[4];
+       unsigned int dt0rdelays0;       /* offset 0x134 */
+       unsigned int dt0dldiff0;        /* offset 0x138 */
+       unsigned int resv7[12];
+};
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
@@ -193,12 +256,12 @@ struct ddr_data {
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int data_macrono, const struct ddr_data *data);
+void config_ddr_data(const struct ddr_data *data, int nr);
 
 /**
  * This structure represents the DDR io control on AM33XX devices.
@@ -226,6 +289,6 @@ struct ddr_ctrl {
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
                const struct ddr_data *data, const struct cmd_control *ctrl,
-               const struct emif_regs *regs);
+               const struct emif_regs *regs, int nr);
 
 #endif  /* _DDR_DEFS_H */