Merge branch 'master' of git://git.denx.de/u-boot-video

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 8117f4f91aed0872fe45a2b96b10efda96850c36..8984e423e61f7087db1c118f539d6bb6e8754265 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -23,6 +23,8 @@
 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
 #define __ASM_ARCH_MX5_IMX_REGS_H__
 
+#define ARCH_MXC
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
@@ -96,6 +98,7 @@
 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define I2C3_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000EC000)
 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
 #endif
 /*
@@ -215,16 +218,6 @@
  */
 #define WBED           1
 
-/*
- * WEIM WCR
- */
-#define BCM            1
-#define GBCD(x)                (((x) & 0x3) << 1)
-#define INTEN          (1 << 4)
-#define INTPOL         (1 << 5)
-#define WDOG_EN                (1 << 8)
-#define WDOG_LIMIT(x)  (((x) & 0x3) << 9)
-
 #define CS0_128                                        0
 #define CS0_64M_CS1_64M                                1
 #define CS0_64M_CS1_32M_CS2_32M                        2
@@ -237,6 +230,7 @@
 #define MXC_CSPICTRL_EN                (1 << 0)
 #define MXC_CSPICTRL_MODE      (1 << 1)
 #define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
@@ -273,6 +267,8 @@
 /* M4IF */
 #define M4IF_FBPM0     0x40
 #define M4IF_FIDBP     0x48
+#define M4IF_GENP_WEIM_MM_MASK         0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
 
 /* Assuming 24MHz input clock with doubler ON */
 /*                            MFI         PDF */
@@ -305,6 +301,10 @@
 #define DP_MFD_400     (3 - 1)
 #define DP_MFN_400     1
 
+#define DP_OP_455      ((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455     (48 - 1)
+#define DP_MFN_455     23
+
 #define DP_OP_216      ((6 << 4) + ((3 - 1)  << 0))
 #define DP_MFD_216     (4 - 1)
 #define DP_MFN_216     3
@@ -318,6 +318,8 @@
 #define BOARD_REV_1_0           0x0
 #define BOARD_REV_2_0           0x1
 
+#define BOARD_VER_OFFSET       0x8
+
 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -458,6 +460,24 @@ struct src {
        u32     simr;
 };
 
+struct srtc_regs {
+       u32     lpscmr;         /* 0x00 */
+       u32     lpsclr;         /* 0x04 */
+       u32     lpsar;          /* 0x08 */
+       u32     lpsmcr;         /* 0x0c */
+       u32     lpcr;           /* 0x10 */
+       u32     lpsr;           /* 0x14 */
+       u32     lppdr;          /* 0x18 */
+       u32     lpgr;           /* 0x1c */
+       u32     hpcmr;          /* 0x20 */
+       u32     hpclr;          /* 0x24 */
+       u32     hpamr;          /* 0x28 */
+       u32     hpalr;          /* 0x2c */
+       u32     hpcr;           /* 0x30 */
+       u32     hpisr;          /* 0x34 */
+       u32     hpienr;         /* 0x38 */
+};
+
 /* CSPI registers */
 struct cspi_regs {
        u32 rxdata;
@@ -481,7 +501,7 @@ struct iim_regs {
        u32     sdat;
        u32     prev;
        u32     srev;
-       u32     preg_p;
+       u32     prg_p;
        u32     scs0;
        u32     scs1;
        u32     scs2;
@@ -490,12 +510,22 @@ struct iim_regs {
        struct fuse_bank {
                u32     fuse_regs[0x20];
                u32     fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
        } bank[4];
+#elif defined(CONFIG_MX53)
+       } bank[5];
+#endif
 };
 
 struct fuse_bank0_regs {
-       u32     fuse0_23[24];
+       u32     fuse0_7[8];
+       u32     uid[8];
+       u32     fuse16_23[8];
+#if defined(CONFIG_MX51)
+       u32     imei[8];
+#elif defined(CONFIG_MX53)
        u32     gp[8];
+#endif
 };
 
 struct fuse_bank1_regs {
@@ -504,6 +534,14 @@ struct fuse_bank1_regs {
        u32     fuse15_31[0x11];
 };
 
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+       u32     fuse0_4[5];
+       u32     gp[3];
+       u32     fuse8_31[0x18];
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif                         /* __ASM_ARCH_MX5_IMX_REGS_H__ */